tree 14b8d1a014349568be39753f879c152e1e3f2b41
parent 0f67e90e1caea4a0a14d2c60102547bce29f7f08
author Ralf Baechle <ralf@linux-mips.org> 1195663184 +0000
committer Ralf Baechle <ralf@linux-mips.org> 1196097974 +0000

[MIPS] Handle R4000/R4400 mfc0 from count register.

The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.