commit 7149c1becddf49022fe0aad2fa395377cd8f753e
author Chen-Yu Tsai <wens@csie.org> Fri Mar 24 16:33:07 2017 +0800
committer Maxime Ripard <maxime.ripard@free-electrons.com> Thu Apr 13 14:09:30 2017 +0200
tree 08527bf607b508675ad05582f2c0c5d60bc3f415
parent 95ad8ed9c87fae043c347ba6cba05aabe5b04d76

clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code

We ignore the d1 and d2 dividers in the audio PLL, and force them to
1 (register value 0) at probe time. However the comment preceding the
audio PLL definition says we enforce the default value, which is not
the same.

Fix the preceding comment to match what we do in code.

Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>