[SUNGEM]: Unbreak Sun GEM chips.
Revert: 40727198bfb2ce5842a6e8c7f89cf8a40ff7bf14
These PHY changes hang the sungem driver on startup with Sun chips on
sparc64. Hopefully we can redo these changes in a way that doesn't
break non-Apple systems.
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
index 55f3b85..28ce47a 100644
--- a/drivers/net/sungem.c
+++ b/drivers/net/sungem.c
@@ -1653,40 +1653,36 @@
/* Init PHY interface and start link poll state machine */
static void gem_init_phy(struct gem *gp)
{
- u32 mif_cfg;
+ u32 mifcfg;
/* Revert MIF CFG setting done on stop_phy */
- mif_cfg = readl(gp->regs + MIF_CFG);
- mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
- mif_cfg |= MIF_CFG_MDI0;
- writel(mif_cfg, gp->regs + MIF_CFG);
- writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
- writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
+ mifcfg = readl(gp->regs + MIF_CFG);
+ mifcfg &= ~MIF_CFG_BBMODE;
+ writel(mifcfg, gp->regs + MIF_CFG);
if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
int i;
- u16 ctrl;
-#ifdef CONFIG_PPC_PMAC
- pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
-#endif
-
- /* Some PHYs used by apple have problem getting back
- * to us, we do an additional reset here
+ /* Those delay sucks, the HW seem to love them though, I'll
+ * serisouly consider breaking some locks here to be able
+ * to schedule instead
*/
- phy_write(gp, MII_BMCR, BMCR_RESET);
- for (i = 0; i < 50; i++) {
- if ((phy_read(gp, MII_BMCR) & BMCR_RESET) == 0)
+ for (i = 0; i < 3; i++) {
+#ifdef CONFIG_PPC_PMAC
+ pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
+ msleep(20);
+#endif
+ /* Some PHYs used by apple have problem getting back to us,
+ * we do an additional reset here
+ */
+ phy_write(gp, MII_BMCR, BMCR_RESET);
+ msleep(20);
+ if (phy_read(gp, MII_BMCR) != 0xffff)
break;
- msleep(10);
+ if (i == 2)
+ printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
+ gp->dev->name);
}
- if (i == 50)
- printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
- gp->dev->name);
- /* Make sure isolate is off */
- ctrl = phy_read(gp, MII_BMCR);
- if (ctrl & BMCR_ISOLATE)
- phy_write(gp, MII_BMCR, ctrl & ~BMCR_ISOLATE);
}
if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
@@ -2123,7 +2119,7 @@
/* Must be invoked with no lock held. */
static void gem_stop_phy(struct gem *gp, int wol)
{
- u32 mif_cfg;
+ u32 mifcfg;
unsigned long flags;
/* Let the chip settle down a bit, it seems that helps
@@ -2134,9 +2130,9 @@
/* Make sure we aren't polling PHY status change. We
* don't currently use that feature though
*/
- mif_cfg = readl(gp->regs + MIF_CFG);
- mif_cfg &= ~MIF_CFG_POLL;
- writel(mif_cfg, gp->regs + MIF_CFG);
+ mifcfg = readl(gp->regs + MIF_CFG);
+ mifcfg &= ~MIF_CFG_POLL;
+ writel(mifcfg, gp->regs + MIF_CFG);
if (wol && gp->has_wol) {
unsigned char *e = &gp->dev->dev_addr[0];
@@ -2186,8 +2182,7 @@
/* According to Apple, we must set the MDIO pins to this begnign
* state or we may 1) eat more current, 2) damage some PHYs
*/
- mif_cfg = 0;
- writel(mif_cfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
+ writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
writel(0, gp->regs + MIF_BBCLK);
writel(0, gp->regs + MIF_BBDATA);
writel(0, gp->regs + MIF_BBOENAB);
