tree b01c7e1679e07578760b810bb91bc03b4503f93a
parent b23083a9c6829675d367b4f06a64d74ead82eb14
author Thierry Reding <treding@nvidia.com> 1430750669 +0200
committer Thierry Reding <treding@nvidia.com> 1437035911 +0200

soc/tegra: fuse: Add spare bit offset for Tegra124

The offset of the first spare bit register on Tegra124 is 0x300, but
account for the fixed offset of 0x100 in the fuse accessor.

Signed-off-by: Thierry Reding <treding@nvidia.com>