)]}'
{
  "commit": "93dc68876b608da041fe40ed39424b0fcd5aa2fb",
  "tree": "dcd4dc84c5a0da7ce4c1581b3ee6f81fdb969765",
  "parents": [
    "6e7aceeb7c70b9ebad79bcfe91fcf738826e8e6d"
  ],
  "author": {
    "name": "Catalin Marinas",
    "email": "catalin.marinas@arm.com",
    "time": "Tue Mar 26 23:35:04 2013 +0100"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Wed Apr 03 16:45:49 2013 +0100"
  },
  "message": "ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)\n\nOn Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down\nall use of the old entries. This patch implements the erratum workaround\nwhich consists of:\n\n1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.\n2. Send IPI to the CPUs that are running the same mm (and ASID) as the\n   one being invalidated (or all the online CPUs for global pages).\n3. CPU receiving the IPI executes a DMB and CLREX (part of the exception\n   return code already).\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
  "tree_diff": [
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