)]}'
{
  "commit": "998ef5d81c74c752d74c7925bc370909b84adb9d",
  "tree": "1e1b8b2385fdf3bba639ef55110a389db914f483",
  "parents": [
    "3473f26592c1c365d376aee29433d7db75f14d1e"
  ],
  "author": {
    "name": "Gregory CLEMENT",
    "email": "gregory.clement@free-electrons.com",
    "time": "Thu Aug 06 15:07:04 2015 +0100"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Fri Aug 07 19:57:02 2015 +0100"
  },
  "message": "ARM: 8408/1: Fix the secondary_startup function in Big Endian case\n\nSince the commit \"b2c3e38a5471 ARM: redo TTBR setup code for LPAE\",\nthe setup code had been reworked. As a result the secondary CPUs\nfailed to come online in Big Endian.\n\nAs explained by Russell, the new code expected the value in r4/r5 to\nbe the least significant 32bits in r4 and the most significant 32bits\nin r5. However, in the secondary code, we load this using ldrd, which\non BE reverses that.\n\nThis patch swap r4/r5 after the ldrd. It is done using the xor\ninstructions in order to not use a temporary register.\n\nSigned-off-by: Gregory CLEMENT \u003cgregory.clement@free-electrons.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bd755d97e459d77ff05cc8a1264f336c58c1b598",
      "old_mode": 33188,
      "old_path": "arch/arm/kernel/head.S",
      "new_id": "29e2991465cb27b579f729deec65e2293a0a04b5",
      "new_mode": 33188,
      "new_path": "arch/arm/kernel/head.S"
    }
  ]
}