)]}'
{
  "commit": "a0c4da24eafb32a3ce44f37b7c3412c6ffb6e37c",
  "tree": "b512d984cd6e3745822640edde9fa96af8cceafd",
  "parents": [
    "cc889e0f6ce6a63c62db17d702ecfed86d58083f"
  ],
  "author": {
    "name": "Jesse Barnes",
    "email": "jbarnes@virtuousgeek.org",
    "time": "Fri Jun 15 11:55:13 2012 -0700"
  },
  "committer": {
    "name": "Daniel Vetter",
    "email": "daniel.vetter@ffwll.ch",
    "time": "Wed Jun 20 14:21:23 2012 +0200"
  },
  "message": "drm/i915: ValleyView mode setting limits and PLL functions\n\nAdd some VLV limit structures and update the PLL code.\n\nv2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits\nv3: re-add dpio write function\nv4: squash in Vijay\u0027s fixes for the PLL limits and clean up the m/n finder\n\nSigned-off-by: Shobhit Kumar \u003cshobhit.kumar@intel.com\u003e\nSigned-off-by: Vijay Purushothaman \u003cvijay.a.purushothaman@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "782e5d1dc21856b6d0dc299d13c1a6632edbd23b",
      "old_mode": 33188,
      "old_path": "drivers/gpu/drm/i915/i915_reg.h",
      "new_id": "b6f5f1040d77bdf04dde0ea797b9e275e83cf8e9",
      "new_mode": 33188,
      "new_path": "drivers/gpu/drm/i915/i915_reg.h"
    },
    {
      "type": "modify",
      "old_id": "97301621f48a956fe31539a4f7af428307222482",
      "old_mode": 33188,
      "old_path": "drivers/gpu/drm/i915/intel_display.c",
      "new_id": "7794c1a630c0e0150093388d2b96820369ec1a79",
      "new_mode": 33188,
      "new_path": "drivers/gpu/drm/i915/intel_display.c"
    }
  ]
}