)]}'
{
  "commit": "a2e8bda41866718ade4856d31f6c87e7234a3add",
  "tree": "12a1516541f379890a5708c0a624d86e475c617d",
  "parents": [
    "36997e433b4b4a2630cd4b7e3d467e4bc66deee6"
  ],
  "author": {
    "name": "Andreas Sandberg",
    "email": "andreas.sandberg@arm.com",
    "time": "Tue Dec 01 13:48:56 2015 +0000"
  },
  "committer": {
    "name": "Andreas Sandberg",
    "email": "andreas.sandberg@arm.com",
    "time": "Tue Mar 06 12:22:04 2018 +0000"
  },
  "message": "gem5: Add support for gem5\u0027s extended GIC mode\n\ngem5\u0027s GIC model contains a gem5-specific extension that enables\nsupport for up to 255 CPUs. When enabled, the GIC interprets registers\nwhere a CPU bitmask would normally be present as a CPU ID.\n\nThis extensions need to be enabled by setting the OF compatible string\nto \"gem5,gic\".\n\nKudos to Matt Evans for the original version of this patch.\n\nChange-Id: I1a8776f1adcbfcd97813573050a8595176de6a7e\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Stephan Diestelhorst \u003cstephan.diestelhorst@arm.com\u003e\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\n[Ported to 4.4]\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n[gabor.dozsa@arm.com: Ported to 4.9 and merged initialization fixup from 4.4.]\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "651d726e8b123f541281504ed14e4d7ed6cea5e6",
      "old_mode": 33188,
      "old_path": "drivers/irqchip/irq-gic.c",
      "new_id": "2b062541d9aa7368b40d216caa7aec9bcaea6828",
      "new_mode": 33188,
      "new_path": "drivers/irqchip/irq-gic.c"
    }
  ]
}