* Xilinx NWL PCIe Root Port Bridge DT description

Required properties:
- compatible: Should contain "xlnx,nwl-pcie-2.11"
- #address-cells: Address representation for root ports, set to <3>
- #size-cells: Size representation for root ports, set to <2>
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.
- reg: Should contain Bridge, PCIe Controller registers location,
	configuration space, and length
- reg-names: Must include the following entries:
	"breg": bridge registers
	"pcireg": PCIe controller registers
	"cfg": configuration space region
- device_type: must be "pci"
- interrupts: Should contain NWL PCIe interrupt
- interrupt-names: Must include the following entries:
	"msi1, msi0": interrupt asserted when MSI is received
	"intx": interrupt asserted when a legacy interrupt is received
	"misc": interrupt asserted when miscellaneous is received
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
	mapping of the PCI interface to interrupt numbers.
- ranges: ranges for the PCI memory regions (I/O space region is not
	supported by hardware)
	Please refer to the standard PCI bus binding document for a more
	detailed explanation
- msi-controller: indicates that this is MSI controller node
- msi-parent:  MSI parent of the root complex itself
- legacy-interrupt-controller: Interrupt controller device node for Legacy interrupts
	- interrupt-controller: identifies the node as an interrupt controller
	- #interrupt-cells: should be set to 1
	- #address-cells: specifies the number of cells needed to encode an
		address. The value must be 0.


Example:
++++++++

nwl_pcie: pcie@fd0e0000 {
	#address-cells = <3>;
	#size-cells = <2>;
	compatible = "xlnx,nwl-pcie-2.11";
	#interrupt-cells = <1>;
	msi-controller;
	device_type = "pci";
	interrupt-parent = <&gic>;
	interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
	interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
	interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
			<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
			<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
			<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;

	msi-parent = <&nwl_pcie>;
	reg = <0x0 0xfd0e0000 0x0 0x1000>,
	      <0x0 0xfd480000 0x0 0x1000>,
	      <0x80 0x00000000 0x0 0x1000000>;
	reg-names = "breg", "pcireg", "cfg";
	ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
		  0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */

	pcie_intc: legacy-interrupt-controller {
		interrupt-controller;
		#address-cells = <0>;
		#interrupt-cells = <1>;
	};

};