#
# Intel pin control drivers
#

config PINCTRL_BAYTRAIL
	bool "Intel Baytrail GPIO pin control"
	depends on GPIOLIB && ACPI
	select GPIOLIB_IRQCHIP
	select PINMUX
	select PINCONF
	select GENERIC_PINCONF
	help
	  driver for memory mapped GPIO functionality on Intel Baytrail
	  platforms. Supports 3 banks with 102, 28 and 44 gpios.
	  Most pins are usually muxed to some other functionality by firmware,
	  so only a small amount is available for gpio use.

	  Requires ACPI device enumeration code to set up a platform device.

config PINCTRL_CHERRYVIEW
	tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
	depends on ACPI
	select PINMUX
	select PINCONF
	select GENERIC_PINCONF
	select GPIOLIB
	select GPIOLIB_IRQCHIP
	help
	  Cherryview/Braswell pinctrl driver provides an interface that
	  allows configuring of SoC pins and using them as GPIOs.

config PINCTRL_MERRIFIELD
	tristate "Intel Merrifield pinctrl driver"
	depends on X86_INTEL_MID
	select PINMUX
	select PINCONF
	select GENERIC_PINCONF
	help
	  Merrifield Family-Level Interface Shim (FLIS) driver provides an
	  interface that allows configuring of SoC pins and using them as
	  GPIOs.

config PINCTRL_INTEL
	tristate
	select PINMUX
	select PINCONF
	select GENERIC_PINCONF
	select GPIOLIB
	select GPIOLIB_IRQCHIP

config PINCTRL_BROXTON
	tristate "Intel Broxton pinctrl and GPIO driver"
	depends on ACPI
	select PINCTRL_INTEL
	help
	  Broxton pinctrl driver provides an interface that allows
	  configuring of SoC pins and using them as GPIOs.

config PINCTRL_GEMINILAKE
	tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
	depends on ACPI
	select PINCTRL_INTEL
	help
	  This pinctrl driver provides an interface that allows configuring
	  of Intel Gemini Lake SoC pins and using them as GPIOs.

config PINCTRL_SUNRISEPOINT
	tristate "Intel Sunrisepoint pinctrl and GPIO driver"
	depends on ACPI
	select PINCTRL_INTEL
	help
	  Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
	  provides an interface that allows configuring of PCH pins and
	  using them as GPIOs.