| /****************************************************************************** |
| * |
| * Copyright(c) 2016 Realtek Corporation. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of version 2 of the GNU General Public License as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, but WITHOUT |
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| * more details. |
| * |
| * The full GNU General Public License is included in this distribution in the |
| * file called LICENSE. |
| * |
| * Contact Information: |
| * wlanfae <wlanfae@realtek.com> |
| * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, |
| * Hsinchu 300, Taiwan. |
| * |
| * Larry Finger <Larry.Finger@lwfinger.net> |
| * |
| *****************************************************************************/ |
| #ifndef __RTL_WLAN_BITDEF_H__ |
| #define __RTL_WLAN_BITDEF_H__ |
| |
| /*-------------------------Modification Log----------------------------------- |
| * Base on MAC_Register.doc SVN391 |
| *-------------------------Modification Log----------------------------------- |
| */ |
| |
| /*--------------------------Include File--------------------------------------*/ |
| /*--------------------------Include File--------------------------------------*/ |
| |
| /* 3 ============Programming guide Start===================== */ |
| /* |
| * 1. For all bit define, it should be prefixed by "BIT_" |
| * 2. For all bit mask, it should be prefixed by "BIT_MASK_" |
| * 3. For all bit shift, it should be prefixed by "BIT_SHIFT_" |
| * 4. For other case, prefix is not needed |
| * |
| * Example: |
| * #define BIT_SHIFT_MAX_TXDMA 16 |
| * #define BIT_MASK_MAX_TXDMA 0x7 |
| * #define BIT_MAX_TXDMA(x) \ |
| * (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA) |
| * #define BIT_GET_MAX_TXDMA(x) \ |
| * (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) |
| * |
| */ |
| /* 3 ============Programming guide End===================== */ |
| |
| #define CPU_OPT_WIDTH 0x1F |
| |
| #define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 |
| #define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff |
| #define BIT_WATCH_DOG_RECORD_V1(x) \ |
| (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1) |
| #define BIT_GET_WATCH_DOG_RECORD_V1(x) \ |
| (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1) |
| |
| #define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9) |
| |
| #define BIT_ISO_MD2PP BIT(0) |
| |
| #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 |
| #define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL |
| #define BIT_R_WMAC_IPV6_MYIPAD(x) \ |
| (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) |
| #define BIT_GET_R_WMAC_IPV6_MYIPAD(x) \ |
| (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_SHIFT_SDIO_INT_TIMEOUT 16 |
| #define BIT_MASK_SDIO_INT_TIMEOUT 0xffff |
| #define BIT_SDIO_INT_TIMEOUT(x) \ |
| (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT) |
| #define BIT_GET_SDIO_INT_TIMEOUT(x) \ |
| (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_PWC_EV12V BIT(15) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_IO_ERR_STATUS BIT(15) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_PWC_EV25V BIT(14) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_PA33V_EN BIT(13) |
| #define BIT_PA12V_EN BIT(12) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_UA33V_EN BIT(11) |
| #define BIT_UA12V_EN BIT(10) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_RFDIO BIT(9) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_REPLY_ERRCRC_IN_DATA BIT(9) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_EB2CORE BIT(8) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_EN_CMD53_OVERLAP BIT(8) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_DIOE BIT(7) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_REPLY_ERR_IN_R5 BIT(7) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_WLPON2PP BIT(6) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_R18A_EN BIT(6) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_IP2MAC_WA2PP BIT(5) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_INIT_CMD_EN BIT(5) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_PD2CORE BIT(4) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_PA2PCIE BIT(3) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_UD2CORE BIT(2) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_EN_RXDMA_MASK_INT BIT(2) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_UA2USB BIT(1) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_EN_MASK_TIMER BIT(1) |
| |
| /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ |
| |
| #define BIT_ISO_WD2PP BIT(0) |
| |
| /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ |
| |
| #define BIT_CMD_ERR_STOP_INT_EN BIT(0) |
| |
| /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ |
| |
| #define BIT_FEN_MREGEN BIT(15) |
| #define BIT_FEN_HWPDN BIT(14) |
| |
| /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ |
| |
| #define BIT_EN_25_1 BIT(13) |
| |
| /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ |
| |
| #define BIT_FEN_ELDR BIT(12) |
| #define BIT_FEN_DCORE BIT(11) |
| #define BIT_FEN_CPUEN BIT(10) |
| #define BIT_FEN_DIOE BIT(9) |
| #define BIT_FEN_PCIED BIT(8) |
| #define BIT_FEN_PPLL BIT(7) |
| #define BIT_FEN_PCIEA BIT(6) |
| #define BIT_FEN_DIO_PCIE BIT(5) |
| #define BIT_FEN_USBD BIT(4) |
| #define BIT_FEN_UPLL BIT(3) |
| #define BIT_FEN_USBA BIT(2) |
| |
| /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ |
| |
| #define BIT_FEN_BB_GLB_RSTN BIT(1) |
| #define BIT_FEN_BBRSTB BIT(0) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_SOP_EABM BIT(31) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_SOP_ACKF BIT(30) |
| #define BIT_SOP_ERCK BIT(29) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_SOP_ESWR BIT(28) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_SOP_PWMM BIT(27) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_SOP_EECK BIT(26) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_SOP_EXTL BIT(24) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_SYM_OP_RING_12M BIT(22) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_ROP_SWPR BIT(21) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_DIS_HW_LPLDM BIT(20) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_OPT_SWRST_WLMCU BIT(19) |
| #define BIT_RDY_SYSPWR BIT(17) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_EN_WLON BIT(16) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_APDM_HPDN BIT(15) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_AFSM_PCIE_SUS_EN BIT(12) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_AFSM_WLSUS_EN BIT(11) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_APFM_SWLPS BIT(10) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_APFM_OFFMAC BIT(9) |
| #define BIT_APFN_ONMAC BIT(8) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_CHIP_PDN_EN BIT(7) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_RDY_MACDIS BIT(6) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_RING_CLK_12M_EN BIT(4) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_PFM_WOWL BIT(3) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_PFM_LDKP BIT(2) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_WL_HCI_ALD BIT(1) |
| |
| /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ |
| |
| #define BIT_PFM_LDALL BIT(0) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_LDO_DUMMY BIT(15) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_CPU_CLK_EN BIT(14) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_SYMREG_CLK_EN BIT(13) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_HCI_CLK_EN BIT(12) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_MAC_CLK_EN BIT(11) |
| #define BIT_SEC_CLK_EN BIT(10) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_PHY_SSC_RSTB BIT(9) |
| #define BIT_EXT_32K_EN BIT(8) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_WL_CLK_TEST BIT(7) |
| #define BIT_OP_SPS_PWM_EN BIT(6) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_LOADER_CLK_EN BIT(5) |
| #define BIT_MACSLP BIT(4) |
| #define BIT_WAKEPAD_EN BIT(3) |
| #define BIT_ROMD16V_EN BIT(2) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_CKANA12M_EN BIT(1) |
| |
| /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ |
| |
| #define BIT_CNTD16V_EN BIT(0) |
| |
| /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ |
| |
| #define BIT_SHIFT_VPDIDX 8 |
| #define BIT_MASK_VPDIDX 0xff |
| #define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX) |
| #define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX) |
| |
| #define BIT_SHIFT_EEM1_0 6 |
| #define BIT_MASK_EEM1_0 0x3 |
| #define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0) |
| #define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0) |
| |
| #define BIT_AUTOLOAD_SUS BIT(5) |
| |
| /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ |
| |
| #define BIT_EERPOMSEL BIT(4) |
| |
| /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ |
| |
| #define BIT_EECS_V1 BIT(3) |
| #define BIT_EESK_V1 BIT(2) |
| #define BIT_EEDI_V1 BIT(1) |
| #define BIT_EEDO_V1 BIT(0) |
| |
| /* 2 REG_EE_VPD (Offset 0x000C) */ |
| |
| #define BIT_SHIFT_VPD_DATA 0 |
| #define BIT_MASK_VPD_DATA 0xffffffffL |
| #define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA) |
| #define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_C2_L_BIT0 BIT(31) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SHIFT_C1_L 29 |
| #define BIT_MASK_C1_L 0x3 |
| #define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L) |
| #define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SHIFT_REG_FREQ_L 25 |
| #define BIT_MASK_REG_FREQ_L 0x7 |
| #define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L) |
| #define BIT_GET_REG_FREQ_L(x) \ |
| (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L) |
| |
| #define BIT_REG_EN_DUTY BIT(24) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SHIFT_REG_MODE 22 |
| #define BIT_MASK_REG_MODE 0x3 |
| #define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE) |
| #define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_REG_EN_SP BIT(21) |
| #define BIT_REG_AUTO_L BIT(20) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SW18_SELD_BIT0 BIT(19) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SW18_POWOCP BIT(18) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SHIFT_OCP_L1 15 |
| #define BIT_MASK_OCP_L1 0x7 |
| #define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1) |
| #define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SHIFT_CF_L 13 |
| #define BIT_MASK_CF_L 0x3 |
| #define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L) |
| #define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SW18_FPWM BIT(11) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_SW18_SWEN BIT(9) |
| #define BIT_SW18_LDEN BIT(8) |
| #define BIT_MAC_ID_EN BIT(7) |
| |
| /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ |
| |
| #define BIT_AFE_BGEN BIT(0) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_POW_ZCD_L BIT(31) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_CRCERR_MSK BIT(31) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_AUTOZCD_L BIT(30) |
| #define BIT_SDIO_HSISR3_IND_MSK BIT(30) |
| #define BIT_SDIO_HSISR2_IND_MSK BIT(29) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_REG_DELAY 28 |
| #define BIT_MASK_REG_DELAY 0x3 |
| #define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY) |
| #define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_HEISR_IND_MSK BIT(28) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_CTWEND_MSK BIT(27) |
| #define BIT_SDIO_ATIMEND_E_MSK BIT(26) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIIO_ATIMEND_MSK BIT(25) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_OCPINT_MSK BIT(24) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_V15ADJ_L1_V1 24 |
| #define BIT_MASK_V15ADJ_L1_V1 0x7 |
| #define BIT_V15ADJ_L1_V1(x) \ |
| (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1) |
| #define BIT_GET_V15ADJ_L1_V1(x) \ |
| (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_PSTIMEOUT_MSK BIT(23) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_GTINT4_MSK BIT(22) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_GTINT3_MSK BIT(21) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_HSISR_IND_MSK BIT(20) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_VOL_L1_V1 20 |
| #define BIT_MASK_VOL_L1_V1 0xf |
| #define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1) |
| #define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_CPWM2_MSK BIT(19) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_CPWM1_MSK BIT(18) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_C2HCMD_INT_MSK BIT(17) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_IN_L1_V1 17 |
| #define BIT_MASK_IN_L1_V1 0x7 |
| #define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1) |
| #define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_BCNERLY_INT_MSK BIT(16) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_TBOX_L1 15 |
| #define BIT_MASK_TBOX_L1 0x3 |
| #define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1) |
| #define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SW18_SEL BIT(13) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SW18_SD BIT(10) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_TXBCNERR_MSK BIT(7) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_R3_L 7 |
| #define BIT_MASK_R3_L 0x3 |
| #define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L) |
| #define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_TXBCNOK_MSK BIT(6) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_SW18_R2 5 |
| #define BIT_MASK_SW18_R2 0x3 |
| #define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2) |
| #define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_RXFOVW_MSK BIT(5) |
| #define BIT_SDIO_TXFOVW_MSK BIT(4) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_SW18_R1 3 |
| #define BIT_MASK_SW18_R1 0x3 |
| #define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1) |
| #define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_RXERR_MSK BIT(3) |
| #define BIT_SDIO_TXERR_MSK BIT(2) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_SDIO_AVAL_MSK BIT(1) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_SHIFT_C3_L_C3 1 |
| #define BIT_MASK_C3_L_C3 0x3 |
| #define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3) |
| #define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3) |
| |
| /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ |
| |
| #define BIT_RX_REQUEST_MSK BIT(0) |
| |
| /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ |
| |
| #define BIT_C2_L_BIT1 BIT(0) |
| |
| /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ |
| |
| #define BIT_SPS18_OCP_DIS BIT(31) |
| |
| /* 2 REG_SDIO_HISR (Offset 0x10250018) */ |
| |
| #define BIT_SDIO_CRCERR BIT(31) |
| |
| /* 2 REG_SDIO_HISR (Offset 0x10250018) */ |
| |
| #define BIT_SDIO_HSISR3_IND BIT(30) |
| #define BIT_SDIO_HSISR2_IND BIT(29) |
| #define BIT_SDIO_HEISR_IND BIT(28) |
| |
| /* 2 REG_SDIO_HISR (Offset 0x10250018) */ |
| |
| #define BIT_SDIO_CTWEND BIT(27) |
| #define BIT_SDIO_ATIMEND_E BIT(26) |
| #define BIT_SDIO_ATIMEND BIT(25) |
| #define BIT_SDIO_OCPINT BIT(24) |
| #define BIT_SDIO_PSTIMEOUT BIT(23) |
| #define BIT_SDIO_GTINT4 BIT(22) |
| #define BIT_SDIO_GTINT3 BIT(21) |
| #define BIT_SDIO_HSISR_IND BIT(20) |
| #define BIT_SDIO_CPWM2 BIT(19) |
| #define BIT_SDIO_CPWM1 BIT(18) |
| #define BIT_SDIO_C2HCMD_INT BIT(17) |
| |
| /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ |
| |
| #define BIT_SHIFT_SPS18_OCP_TH 16 |
| #define BIT_MASK_SPS18_OCP_TH 0x7fff |
| #define BIT_SPS18_OCP_TH(x) \ |
| (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH) |
| #define BIT_GET_SPS18_OCP_TH(x) \ |
| (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH) |
| |
| /* 2 REG_SDIO_HISR (Offset 0x10250018) */ |
| |
| #define BIT_SDIO_BCNERLY_INT BIT(16) |
| #define BIT_SDIO_TXBCNERR BIT(7) |
| #define BIT_SDIO_TXBCNOK BIT(6) |
| #define BIT_SDIO_RXFOVW BIT(5) |
| #define BIT_SDIO_TXFOVW BIT(4) |
| #define BIT_SDIO_RXERR BIT(3) |
| #define BIT_SDIO_TXERR BIT(2) |
| #define BIT_SDIO_AVAL BIT(1) |
| |
| /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ |
| |
| #define BIT_SHIFT_OCP_WINDOW 0 |
| #define BIT_MASK_OCP_WINDOW 0xffff |
| #define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW) |
| #define BIT_GET_OCP_WINDOW(x) \ |
| (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW) |
| |
| /* 2 REG_SDIO_HISR (Offset 0x10250018) */ |
| |
| #define BIT_RX_REQUEST BIT(0) |
| |
| /* 2 REG_RSV_CTRL (Offset 0x001C) */ |
| |
| #define BIT_HREG_DBG BIT(23) |
| |
| /* 2 REG_RSV_CTRL (Offset 0x001C) */ |
| |
| #define BIT_WLMCUIOIF BIT(8) |
| |
| /* 2 REG_RSV_CTRL (Offset 0x001C) */ |
| |
| #define BIT_LOCK_ALL_EN BIT(7) |
| |
| /* 2 REG_RSV_CTRL (Offset 0x001C) */ |
| |
| #define BIT_R_DIS_PRST BIT(6) |
| |
| /* 2 REG_RSV_CTRL (Offset 0x001C) */ |
| |
| #define BIT_WLOCK_1C_B6 BIT(5) |
| |
| /* 2 REG_RSV_CTRL (Offset 0x001C) */ |
| |
| #define BIT_WLOCK_40 BIT(4) |
| #define BIT_WLOCK_08 BIT(3) |
| #define BIT_WLOCK_04 BIT(2) |
| #define BIT_WLOCK_00 BIT(1) |
| #define BIT_WLOCK_ALL BIT(0) |
| |
| /* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */ |
| |
| #define BIT_SHIFT_RX_REQ_LEN_V1 0 |
| #define BIT_MASK_RX_REQ_LEN_V1 0x3ffff |
| #define BIT_RX_REQ_LEN_V1(x) \ |
| (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1) |
| #define BIT_GET_RX_REQ_LEN_V1(x) \ |
| (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1) |
| |
| /* 2 REG_RF_CTRL (Offset 0x001F) */ |
| |
| #define BIT_RF_SDMRSTB BIT(2) |
| |
| /* 2 REG_RF_CTRL (Offset 0x001F) */ |
| |
| #define BIT_RF_RSTB BIT(1) |
| |
| /* 2 REG_RF_CTRL (Offset 0x001F) */ |
| |
| #define BIT_RF_EN BIT(0) |
| |
| /* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */ |
| |
| #define BIT_SHIFT_FREE_TXPG_SEQ 0 |
| #define BIT_MASK_FREE_TXPG_SEQ 0xff |
| #define BIT_FREE_TXPG_SEQ(x) \ |
| (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ) |
| #define BIT_GET_FREE_TXPG_SEQ(x) \ |
| (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_SHIFT_LPLDH12_RSV 29 |
| #define BIT_MASK_LPLDH12_RSV 0x7 |
| #define BIT_LPLDH12_RSV(x) \ |
| (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV) |
| #define BIT_GET_LPLDH12_RSV(x) \ |
| (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_LPLDH12_SLP BIT(28) |
| |
| #define BIT_SHIFT_LPLDH12_VADJ 24 |
| #define BIT_MASK_LPLDH12_VADJ 0xf |
| #define BIT_LPLDH12_VADJ(x) \ |
| (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ) |
| #define BIT_GET_LPLDH12_VADJ(x) \ |
| (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_LDH12_EN BIT(16) |
| |
| /* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ |
| |
| #define BIT_SHIFT_MID_FREEPG_V1 16 |
| #define BIT_MASK_MID_FREEPG_V1 0xfff |
| #define BIT_MID_FREEPG_V1(x) \ |
| (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1) |
| #define BIT_GET_MID_FREEPG_V1(x) \ |
| (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_WLBBOFF_BIG_PWC_EN BIT(14) |
| #define BIT_WLBBOFF_SMALL_PWC_EN BIT(13) |
| #define BIT_WLMACOFF_BIG_PWC_EN BIT(12) |
| #define BIT_WLPON_PWC_EN BIT(11) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_POW_REGU_P1 BIT(10) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_LDOV12W_EN BIT(8) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_EX_XTAL_DRV_DIGI BIT(7) |
| #define BIT_EX_XTAL_DRV_USB BIT(6) |
| #define BIT_EX_XTAL_DRV_AFE BIT(5) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_EX_XTAL_DRV_RF2 BIT(4) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_EX_XTAL_DRV_RF1 BIT(3) |
| #define BIT_POW_REGU_P0 BIT(2) |
| |
| /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ |
| |
| #define BIT_POW_PLL_LDO BIT(0) |
| |
| /* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ |
| |
| #define BIT_SHIFT_HIQ_FREEPG_V1 0 |
| #define BIT_MASK_HIQ_FREEPG_V1 0xfff |
| #define BIT_HIQ_FREEPG_V1(x) \ |
| (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1) |
| #define BIT_GET_HIQ_FREEPG_V1(x) \ |
| (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_AGPIO_GPE BIT(31) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_XTAL_CAP_XI 25 |
| #define BIT_MASK_XTAL_CAP_XI 0x3f |
| #define BIT_XTAL_CAP_XI(x) \ |
| (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI) |
| #define BIT_GET_XTAL_CAP_XI(x) \ |
| (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_XTAL_DRV_DIGI 23 |
| #define BIT_MASK_XTAL_DRV_DIGI 0x3 |
| #define BIT_XTAL_DRV_DIGI(x) \ |
| (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI) |
| #define BIT_GET_XTAL_DRV_DIGI(x) \ |
| (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI) |
| |
| #define BIT_XTAL_DRV_USB_BIT1 BIT(22) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_MAC_CLK_SEL 20 |
| #define BIT_MASK_MAC_CLK_SEL 0x3 |
| #define BIT_MAC_CLK_SEL(x) \ |
| (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL) |
| #define BIT_GET_MAC_CLK_SEL(x) \ |
| (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_XTAL_DRV_USB_BIT0 BIT(19) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_XTAL_DRV_AFE 17 |
| #define BIT_MASK_XTAL_DRV_AFE 0x3 |
| #define BIT_XTAL_DRV_AFE(x) \ |
| (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE) |
| #define BIT_GET_XTAL_DRV_AFE(x) \ |
| (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE) |
| |
| /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ |
| |
| #define BIT_SHIFT_PUB_FREEPG_V1 16 |
| #define BIT_MASK_PUB_FREEPG_V1 0xfff |
| #define BIT_PUB_FREEPG_V1(x) \ |
| (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1) |
| #define BIT_GET_PUB_FREEPG_V1(x) \ |
| (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_XTAL_DRV_RF2 15 |
| #define BIT_MASK_XTAL_DRV_RF2 0x3 |
| #define BIT_XTAL_DRV_RF2(x) \ |
| (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2) |
| #define BIT_GET_XTAL_DRV_RF2(x) \ |
| (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_XTAL_DRV_RF1 13 |
| #define BIT_MASK_XTAL_DRV_RF1 0x3 |
| #define BIT_XTAL_DRV_RF1(x) \ |
| (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1) |
| #define BIT_GET_XTAL_DRV_RF1(x) \ |
| (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_XTAL_DELAY_DIGI BIT(12) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_XTAL_DELAY_USB BIT(11) |
| #define BIT_XTAL_DELAY_AFE BIT(10) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_XTAL_LDO_VREF 7 |
| #define BIT_MASK_XTAL_LDO_VREF 0x7 |
| #define BIT_XTAL_LDO_VREF(x) \ |
| (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF) |
| #define BIT_GET_XTAL_LDO_VREF(x) \ |
| (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_XTAL_XQSEL_RF BIT(6) |
| #define BIT_XTAL_XQSEL BIT(5) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_XTAL_GMN_V2 3 |
| #define BIT_MASK_XTAL_GMN_V2 0x3 |
| #define BIT_XTAL_GMN_V2(x) \ |
| (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2) |
| #define BIT_GET_XTAL_GMN_V2(x) \ |
| (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_SHIFT_XTAL_GMP_V2 1 |
| #define BIT_MASK_XTAL_GMP_V2 0x3 |
| #define BIT_XTAL_GMP_V2(x) \ |
| (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2) |
| #define BIT_GET_XTAL_GMP_V2(x) \ |
| (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2) |
| |
| /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ |
| |
| #define BIT_XTAL_EN BIT(0) |
| |
| /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ |
| |
| #define BIT_SHIFT_LOW_FREEPG_V1 0 |
| #define BIT_MASK_LOW_FREEPG_V1 0xfff |
| #define BIT_LOW_FREEPG_V1(x) \ |
| (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1) |
| #define BIT_GET_LOW_FREEPG_V1(x) \ |
| (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_REG_C3_V4 30 |
| #define BIT_MASK_REG_C3_V4 0x3 |
| #define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4) |
| #define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4) |
| |
| #define BIT_REG_CP_BIT1 BIT(29) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_REG_RS_V4 26 |
| #define BIT_MASK_REG_RS_V4 0x7 |
| #define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4) |
| #define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4) |
| |
| /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ |
| |
| #define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24 |
| #define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff |
| #define BIT_NOAC_OQT_FREEPG_V1(x) \ |
| (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1) |
| #define BIT_GET_NOAC_OQT_FREEPG_V1(x) \ |
| (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_REG__CS 24 |
| #define BIT_MASK_REG__CS 0x3 |
| #define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS) |
| #define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_REG_CP_OFFSET 21 |
| #define BIT_MASK_REG_CP_OFFSET 0x7 |
| #define BIT_REG_CP_OFFSET(x) \ |
| (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET) |
| #define BIT_GET_REG_CP_OFFSET(x) \ |
| (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_CP_BIAS 18 |
| #define BIT_MASK_CP_BIAS 0x7 |
| #define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS) |
| #define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_REG_IDOUBLE_V2 BIT(17) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_EN_SYN BIT(16) |
| |
| #define BIT_SHIFT_AC_OQT_FREEPG_V1 16 |
| #define BIT_MASK_AC_OQT_FREEPG_V1 0xff |
| #define BIT_AC_OQT_FREEPG_V1(x) \ |
| (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1) |
| #define BIT_GET_AC_OQT_FREEPG_V1(x) \ |
| (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_MCCO 14 |
| #define BIT_MASK_MCCO 0x3 |
| #define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO) |
| #define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_REG_LDO_SEL 12 |
| #define BIT_MASK_REG_LDO_SEL 0x3 |
| #define BIT_REG_LDO_SEL(x) \ |
| (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL) |
| #define BIT_GET_REG_LDO_SEL(x) \ |
| (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL) |
| |
| #define BIT_REG_KVCO_V2 BIT(10) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_AGPIO_GPO BIT(9) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_AGPIO_DRV 7 |
| #define BIT_MASK_AGPIO_DRV 0x3 |
| #define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV) |
| #define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_SHIFT_XTAL_CAP_XO 1 |
| #define BIT_MASK_XTAL_CAP_XO 0x3f |
| #define BIT_XTAL_CAP_XO(x) \ |
| (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO) |
| #define BIT_GET_XTAL_CAP_XO(x) \ |
| (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO) |
| |
| /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ |
| |
| #define BIT_POW_PLL BIT(0) |
| |
| /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ |
| |
| #define BIT_SHIFT_EXQ_FREEPG_V1 0 |
| #define BIT_MASK_EXQ_FREEPG_V1 0xfff |
| #define BIT_EXQ_FREEPG_V1(x) \ |
| (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1) |
| #define BIT_GET_EXQ_FREEPG_V1(x) \ |
| (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) |
| |
| /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ |
| |
| #define BIT_SHIFT_PS 7 |
| #define BIT_MASK_PS 0x7 |
| #define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS) |
| #define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS) |
| |
| /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ |
| |
| #define BIT_PSEN BIT(6) |
| #define BIT_DOGENB BIT(5) |
| |
| /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ |
| |
| #define BIT_REG_MBIAS BIT(4) |
| |
| /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ |
| |
| #define BIT_SHIFT_REG_R3_V4 1 |
| #define BIT_MASK_REG_R3_V4 0x7 |
| #define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4) |
| #define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4) |
| |
| /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ |
| |
| #define BIT_REG_CP_BIT0 BIT(0) |
| |
| /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ |
| |
| #define BIT_EF_FLAG BIT(31) |
| |
| #define BIT_SHIFT_EF_PGPD 28 |
| #define BIT_MASK_EF_PGPD 0x7 |
| #define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD) |
| #define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD) |
| |
| #define BIT_SHIFT_EF_RDT 24 |
| #define BIT_MASK_EF_RDT 0xf |
| #define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT) |
| #define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT) |
| |
| #define BIT_SHIFT_EF_PGTS 20 |
| #define BIT_MASK_EF_PGTS 0xf |
| #define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS) |
| #define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS) |
| |
| /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ |
| |
| #define BIT_EF_PDWN BIT(19) |
| |
| /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ |
| |
| #define BIT_EF_ALDEN BIT(18) |
| |
| /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ |
| |
| #define BIT_SHIFT_HTSFR1 16 |
| #define BIT_MASK_HTSFR1 0xffff |
| #define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1) |
| #define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1) |
| |
| /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ |
| |
| #define BIT_SHIFT_EF_ADDR 8 |
| #define BIT_MASK_EF_ADDR 0x3ff |
| #define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) |
| #define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR) |
| |
| #define BIT_SHIFT_EF_DATA 0 |
| #define BIT_MASK_EF_DATA 0xff |
| #define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA) |
| #define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA) |
| |
| /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ |
| |
| #define BIT_SHIFT_HTSFR0 0 |
| #define BIT_MASK_HTSFR0 0xffff |
| #define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0) |
| #define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0) |
| |
| /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ |
| |
| #define BIT_LDOE25_EN BIT(31) |
| |
| /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ |
| |
| #define BIT_SHIFT_LDOE25_V12ADJ_L 27 |
| #define BIT_MASK_LDOE25_V12ADJ_L 0xf |
| #define BIT_LDOE25_V12ADJ_L(x) \ |
| (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L) |
| #define BIT_GET_LDOE25_V12ADJ_L(x) \ |
| (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L) |
| |
| /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ |
| |
| #define BIT_EF_CRES_SEL BIT(26) |
| |
| /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ |
| |
| #define BIT_SHIFT_EF_SCAN_START_V1 16 |
| #define BIT_MASK_EF_SCAN_START_V1 0x3ff |
| #define BIT_EF_SCAN_START_V1(x) \ |
| (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1) |
| #define BIT_GET_EF_SCAN_START_V1(x) \ |
| (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1) |
| |
| /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ |
| |
| #define BIT_SHIFT_EF_SCAN_END 12 |
| #define BIT_MASK_EF_SCAN_END 0xf |
| #define BIT_EF_SCAN_END(x) \ |
| (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END) |
| #define BIT_GET_EF_SCAN_END(x) \ |
| (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END) |
| |
| /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ |
| |
| #define BIT_EF_PD_DIS BIT(11) |
| |
| /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ |
| |
| #define BIT_SHIFT_EF_CELL_SEL 8 |
| #define BIT_MASK_EF_CELL_SEL 0x3 |
| #define BIT_EF_CELL_SEL(x) \ |
| (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL) |
| #define BIT_GET_EF_CELL_SEL(x) \ |
| (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL) |
| |
| /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ |
| |
| #define BIT_EF_TRPT BIT(7) |
| |
| #define BIT_SHIFT_EF_TTHD 0 |
| #define BIT_MASK_EF_TTHD 0x7f |
| #define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD) |
| #define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SHIFT_DBG_SEL_V1 16 |
| #define BIT_MASK_DBG_SEL_V1 0xff |
| #define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1) |
| #define BIT_GET_DBG_SEL_V1(x) \ |
| (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SHIFT_DBG_SEL_BYTE 14 |
| #define BIT_MASK_DBG_SEL_BYTE 0x3 |
| #define BIT_DBG_SEL_BYTE(x) \ |
| (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE) |
| #define BIT_GET_DBG_SEL_BYTE(x) \ |
| (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SHIFT_STD_L1_V1 12 |
| #define BIT_MASK_STD_L1_V1 0x3 |
| #define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1) |
| #define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SYSON_DBG_PAD_E2 BIT(11) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SYSON_LED_PAD_E2 BIT(10) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SYSON_GPEE_PAD_E2 BIT(9) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SYSON_PCI_PAD_E2 BIT(8) |
| |
| #define BIT_SHIFT_MATCH_CNT 8 |
| #define BIT_MASK_MATCH_CNT 0xff |
| #define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT) |
| #define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_AUTO_SW_LDO_VOL_EN BIT(7) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SHIFT_SYSON_SPS0WWV_WT 4 |
| #define BIT_MASK_SYSON_SPS0WWV_WT 0x3 |
| #define BIT_SYSON_SPS0WWV_WT(x) \ |
| (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT) |
| #define BIT_GET_SYSON_SPS0WWV_WT(x) \ |
| (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SHIFT_SYSON_SPS0LDO_WT 2 |
| #define BIT_MASK_SYSON_SPS0LDO_WT 0x3 |
| #define BIT_SYSON_SPS0LDO_WT(x) \ |
| (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT) |
| #define BIT_GET_SYSON_SPS0LDO_WT(x) \ |
| (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT) |
| |
| /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ |
| |
| #define BIT_SHIFT_SYSON_RCLK_SCALE 0 |
| #define BIT_MASK_SYSON_RCLK_SCALE 0x3 |
| #define BIT_SYSON_RCLK_SCALE(x) \ |
| (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE) |
| #define BIT_GET_SYSON_RCLK_SCALE(x) \ |
| (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) |
| |
| /* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ |
| |
| #define BIT_SYS_CLK BIT(0) |
| |
| /* 2 REG_CAL_TIMER (Offset 0x003C) */ |
| |
| #define BIT_SHIFT_CAL_SCAL 0 |
| #define BIT_MASK_CAL_SCAL 0xff |
| #define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL) |
| #define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL) |
| |
| /* 2 REG_ACLK_MON (Offset 0x003E) */ |
| |
| #define BIT_SHIFT_RCLK_MON 5 |
| #define BIT_MASK_RCLK_MON 0x7ff |
| #define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON) |
| #define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON) |
| |
| #define BIT_CAL_EN BIT(4) |
| |
| #define BIT_SHIFT_DPSTU 2 |
| #define BIT_MASK_DPSTU 0x3 |
| #define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU) |
| #define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU) |
| |
| #define BIT_SUS_16X BIT(1) |
| |
| /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ |
| |
| #define BIT_INDIRECT_REG_RDY BIT(20) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_FSPI_EN BIT(19) |
| |
| /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ |
| |
| #define BIT_INDIRECT_REG_R BIT(19) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_WL_RTS_EXT_32K_SEL BIT(18) |
| |
| /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ |
| |
| #define BIT_INDIRECT_REG_W BIT(18) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_WLGP_SPI_EN BIT(16) |
| |
| /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ |
| |
| #define BIT_SHIFT_INDIRECT_REG_SIZE 16 |
| #define BIT_MASK_INDIRECT_REG_SIZE 0x3 |
| #define BIT_INDIRECT_REG_SIZE(x) \ |
| (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE) |
| #define BIT_GET_INDIRECT_REG_SIZE(x) \ |
| (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_SIC_LBK BIT(15) |
| #define BIT_ENHTP BIT(14) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_ENSIC BIT(12) |
| #define BIT_SIC_SWRST BIT(11) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_PO_WIFI_PTA_PINS BIT(10) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_PO_BT_PTA_PINS BIT(9) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_ENUART BIT(8) |
| |
| #define BIT_SHIFT_BTMODE 6 |
| #define BIT_MASK_BTMODE 0x3 |
| #define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE) |
| #define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE) |
| |
| #define BIT_ENBT BIT(5) |
| #define BIT_EROM_EN BIT(4) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_WLRFE_6_7_EN BIT(3) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_WLRFE_4_5_EN BIT(2) |
| |
| /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ |
| |
| #define BIT_SHIFT_GPIOSEL 0 |
| #define BIT_MASK_GPIOSEL 0x3 |
| #define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL) |
| #define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL) |
| |
| /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ |
| |
| #define BIT_SHIFT_INDIRECT_REG_ADDR 0 |
| #define BIT_MASK_INDIRECT_REG_ADDR 0xffff |
| #define BIT_INDIRECT_REG_ADDR(x) \ |
| (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR) |
| #define BIT_GET_INDIRECT_REG_ADDR(x) \ |
| (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR) |
| |
| /* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ |
| |
| #define BIT_SHIFT_GPIO_MOD_7_TO_0 24 |
| #define BIT_MASK_GPIO_MOD_7_TO_0 0xff |
| #define BIT_GPIO_MOD_7_TO_0(x) \ |
| (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0) |
| #define BIT_GET_GPIO_MOD_7_TO_0(x) \ |
| (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0) |
| |
| #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16 |
| #define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff |
| #define BIT_GPIO_IO_SEL_7_TO_0(x) \ |
| (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) |
| #define BIT_GET_GPIO_IO_SEL_7_TO_0(x) \ |
| (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0) |
| |
| #define BIT_SHIFT_GPIO_OUT_7_TO_0 8 |
| #define BIT_MASK_GPIO_OUT_7_TO_0 0xff |
| #define BIT_GPIO_OUT_7_TO_0(x) \ |
| (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0) |
| #define BIT_GET_GPIO_OUT_7_TO_0(x) \ |
| (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0) |
| |
| #define BIT_SHIFT_GPIO_IN_7_TO_0 0 |
| #define BIT_MASK_GPIO_IN_7_TO_0 0xff |
| #define BIT_GPIO_IN_7_TO_0(x) \ |
| (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0) |
| #define BIT_GET_GPIO_IN_7_TO_0(x) \ |
| (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0) |
| |
| /* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ |
| |
| #define BIT_SHIFT_INDIRECT_REG_DATA 0 |
| #define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL |
| #define BIT_INDIRECT_REG_DATA(x) \ |
| (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA) |
| #define BIT_GET_INDIRECT_REG_DATA(x) \ |
| (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA) |
| |
| /* 2 REG_GPIO_INTM (Offset 0x0048) */ |
| |
| #define BIT_SHIFT_MUXDBG_SEL 30 |
| #define BIT_MASK_MUXDBG_SEL 0x3 |
| #define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL) |
| #define BIT_GET_MUXDBG_SEL(x) \ |
| (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL) |
| |
| /* 2 REG_GPIO_INTM (Offset 0x0048) */ |
| |
| #define BIT_EXTWOL_SEL BIT(17) |
| |
| /* 2 REG_GPIO_INTM (Offset 0x0048) */ |
| |
| #define BIT_EXTWOL_EN BIT(16) |
| |
| /* 2 REG_GPIO_INTM (Offset 0x0048) */ |
| |
| #define BIT_GPIOF_INT_MD BIT(15) |
| #define BIT_GPIOE_INT_MD BIT(14) |
| #define BIT_GPIOD_INT_MD BIT(13) |
| #define BIT_GPIOC_INT_MD BIT(12) |
| #define BIT_GPIOB_INT_MD BIT(11) |
| #define BIT_GPIOA_INT_MD BIT(10) |
| #define BIT_GPIO9_INT_MD BIT(9) |
| #define BIT_GPIO8_INT_MD BIT(8) |
| #define BIT_GPIO7_INT_MD BIT(7) |
| #define BIT_GPIO6_INT_MD BIT(6) |
| #define BIT_GPIO5_INT_MD BIT(5) |
| #define BIT_GPIO4_INT_MD BIT(4) |
| #define BIT_GPIO3_INT_MD BIT(3) |
| #define BIT_GPIO2_INT_MD BIT(2) |
| #define BIT_GPIO1_INT_MD BIT(1) |
| #define BIT_GPIO0_INT_MD BIT(0) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_GPIO3_WL_CTRL_EN BIT(27) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_LNAON_SEL_EN BIT(26) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_PAPE_SEL_EN BIT(25) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_DPDT_WLBT_SEL BIT(24) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_DPDT_SEL_EN BIT(23) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_GPIO13_14_WL_CTRL_EN BIT(22) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_LED2DIS BIT(21) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_LED2PL BIT(20) |
| #define BIT_LED2SV BIT(19) |
| |
| #define BIT_SHIFT_LED2CM 16 |
| #define BIT_MASK_LED2CM 0x7 |
| #define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM) |
| #define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM) |
| |
| #define BIT_LED1DIS BIT(15) |
| #define BIT_LED1PL BIT(12) |
| #define BIT_LED1SV BIT(11) |
| |
| #define BIT_SHIFT_LED1CM 8 |
| #define BIT_MASK_LED1CM 0x7 |
| #define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM) |
| #define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM) |
| |
| #define BIT_LED0DIS BIT(7) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_SHIFT_AFE_LDO_SWR_CHECK 5 |
| #define BIT_MASK_AFE_LDO_SWR_CHECK 0x3 |
| #define BIT_AFE_LDO_SWR_CHECK(x) \ |
| (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK) |
| #define BIT_GET_AFE_LDO_SWR_CHECK(x) \ |
| (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK) |
| |
| /* 2 REG_LED_CFG (Offset 0x004C) */ |
| |
| #define BIT_LED0PL BIT(4) |
| #define BIT_LED0SV BIT(3) |
| |
| #define BIT_SHIFT_LED0CM 0 |
| #define BIT_MASK_LED0CM 0x7 |
| #define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM) |
| #define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_PDNINT_EN BIT(31) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_NFC_INT_PAD_EN BIT(30) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_SPS_OCP_INT_EN BIT(29) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_PWMERR_INT_EN BIT(28) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIOF_INT_EN BIT(27) |
| #define BIT_FS_GPIOE_INT_EN BIT(26) |
| #define BIT_FS_GPIOD_INT_EN BIT(25) |
| #define BIT_FS_GPIOC_INT_EN BIT(24) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIOB_INT_EN BIT(23) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIOA_INT_EN BIT(22) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO9_INT_EN BIT(21) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO8_INT_EN BIT(20) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO7_INT_EN BIT(19) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO6_INT_EN BIT(18) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO5_INT_EN BIT(17) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO4_INT_EN BIT(16) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO3_INT_EN BIT(15) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO2_INT_EN BIT(14) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO1_INT_EN BIT(13) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_GPIO0_INT_EN BIT(12) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_HCI_SUS_EN BIT(11) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_HCI_RES_EN BIT(10) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_HCI_RESET_EN BIT(9) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_GEN1GEN2_SWITCH BIT(5) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_HCI_TXDMA_REQ_HIMR BIT(4) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_32K_ENTER_SETTING_MAK BIT(2) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_USB_LPMRSM_MSK BIT(1) |
| |
| /* 2 REG_FSIMR (Offset 0x0050) */ |
| |
| #define BIT_FS_USB_LPMINT_MSK BIT(0) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_PDNINT BIT(31) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_SPS_OCP_INT BIT(29) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_PWMERR_INT BIT(28) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIOF_INT BIT(27) |
| #define BIT_FS_GPIOE_INT BIT(26) |
| #define BIT_FS_GPIOD_INT BIT(25) |
| #define BIT_FS_GPIOC_INT BIT(24) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIOB_INT BIT(23) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIOA_INT BIT(22) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO9_INT BIT(21) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO8_INT BIT(20) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO7_INT BIT(19) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO6_INT BIT(18) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO5_INT BIT(17) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO4_INT BIT(16) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO3_INT BIT(15) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO2_INT BIT(14) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO1_INT BIT(13) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_GPIO0_INT BIT(12) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_HCI_SUS_INT BIT(11) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_HCI_RES_INT BIT(10) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_HCI_RESET_INT BIT(9) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_ACT2RECOVERY BIT(6) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_HCI_TXDMA_REQ_HISR BIT(4) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_32K_LEAVE_SETTING_INT BIT(3) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_32K_ENTER_SETTING_INT BIT(2) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_USB_LPMRSM_INT BIT(1) |
| |
| /* 2 REG_FSISR (Offset 0x0054) */ |
| |
| #define BIT_FS_USB_LPMINT_INT BIT(0) |
| |
| /* 2 REG_HSIMR (Offset 0x0058) */ |
| |
| #define BIT_GPIOF_INT_EN BIT(31) |
| #define BIT_GPIOE_INT_EN BIT(30) |
| #define BIT_GPIOD_INT_EN BIT(29) |
| #define BIT_GPIOC_INT_EN BIT(28) |
| #define BIT_GPIOB_INT_EN BIT(27) |
| #define BIT_GPIOA_INT_EN BIT(26) |
| #define BIT_GPIO9_INT_EN BIT(25) |
| #define BIT_GPIO8_INT_EN BIT(24) |
| #define BIT_GPIO7_INT_EN BIT(23) |
| #define BIT_GPIO6_INT_EN BIT(22) |
| #define BIT_GPIO5_INT_EN BIT(21) |
| #define BIT_GPIO4_INT_EN BIT(20) |
| #define BIT_GPIO3_INT_EN BIT(19) |
| |
| /* 2 REG_HSIMR (Offset 0x0058) */ |
| |
| #define BIT_GPIO1_INT_EN BIT(17) |
| #define BIT_GPIO0_INT_EN BIT(16) |
| |
| /* 2 REG_HSIMR (Offset 0x0058) */ |
| |
| #define BIT_GPIO2_INT_EN_V1 BIT(16) |
| |
| /* 2 REG_HSIMR (Offset 0x0058) */ |
| |
| #define BIT_PDNINT_EN BIT(7) |
| |
| /* 2 REG_HSIMR (Offset 0x0058) */ |
| |
| #define BIT_RON_INT_EN BIT(6) |
| |
| /* 2 REG_HSIMR (Offset 0x0058) */ |
| |
| #define BIT_SPS_OCP_INT_EN BIT(5) |
| |
| /* 2 REG_HSIMR (Offset 0x0058) */ |
| |
| #define BIT_GPIO15_0_INT_EN BIT(0) |
| |
| /* 2 REG_HSISR (Offset 0x005C) */ |
| |
| #define BIT_GPIOF_INT BIT(31) |
| #define BIT_GPIOE_INT BIT(30) |
| #define BIT_GPIOD_INT BIT(29) |
| #define BIT_GPIOC_INT BIT(28) |
| #define BIT_GPIOB_INT BIT(27) |
| #define BIT_GPIOA_INT BIT(26) |
| #define BIT_GPIO9_INT BIT(25) |
| #define BIT_GPIO8_INT BIT(24) |
| #define BIT_GPIO7_INT BIT(23) |
| |
| /* 2 REG_HSISR (Offset 0x005C) */ |
| |
| #define BIT_GPIO6_INT BIT(22) |
| #define BIT_GPIO5_INT BIT(21) |
| #define BIT_GPIO4_INT BIT(20) |
| #define BIT_GPIO3_INT BIT(19) |
| |
| /* 2 REG_HSISR (Offset 0x005C) */ |
| |
| #define BIT_GPIO1_INT BIT(17) |
| #define BIT_GPIO0_INT BIT(16) |
| |
| /* 2 REG_HSISR (Offset 0x005C) */ |
| |
| #define BIT_GPIO2_INT_V1 BIT(16) |
| |
| /* 2 REG_HSISR (Offset 0x005C) */ |
| |
| #define BIT_PDNINT BIT(7) |
| |
| /* 2 REG_HSISR (Offset 0x005C) */ |
| |
| #define BIT_RON_INT BIT(6) |
| |
| /* 2 REG_HSISR (Offset 0x005C) */ |
| |
| #define BIT_SPS_OCP_INT BIT(5) |
| |
| /* 2 REG_HSISR (Offset 0x005C) */ |
| |
| #define BIT_GPIO15_0_INT BIT(0) |
| #define BIT_MCUFWDL_EN BIT(0) |
| |
| /* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ |
| |
| #define BIT_SHIFT_GPIO_MOD_15_TO_8 24 |
| #define BIT_MASK_GPIO_MOD_15_TO_8 0xff |
| #define BIT_GPIO_MOD_15_TO_8(x) \ |
| (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8) |
| #define BIT_GET_GPIO_MOD_15_TO_8(x) \ |
| (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8) |
| |
| #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16 |
| #define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff |
| #define BIT_GPIO_IO_SEL_15_TO_8(x) \ |
| (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) |
| #define BIT_GET_GPIO_IO_SEL_15_TO_8(x) \ |
| (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8) |
| |
| #define BIT_SHIFT_GPIO_OUT_15_TO_8 8 |
| #define BIT_MASK_GPIO_OUT_15_TO_8 0xff |
| #define BIT_GPIO_OUT_15_TO_8(x) \ |
| (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8) |
| #define BIT_GET_GPIO_OUT_15_TO_8(x) \ |
| (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8) |
| |
| #define BIT_SHIFT_GPIO_IN_15_TO_8 0 |
| #define BIT_MASK_GPIO_IN_15_TO_8 0xff |
| #define BIT_GPIO_IN_15_TO_8(x) \ |
| (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8) |
| #define BIT_GET_GPIO_IN_15_TO_8(x) \ |
| (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8) |
| |
| /* 2 REG_SDIO_H2C (Offset 0x10250060) */ |
| |
| #define BIT_SHIFT_SDIO_H2C_MSG 0 |
| #define BIT_MASK_SDIO_H2C_MSG 0xffffffffL |
| #define BIT_SDIO_H2C_MSG(x) \ |
| (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG) |
| #define BIT_GET_SDIO_H2C_MSG(x) \ |
| (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_PAPE_WLBT_SEL BIT(29) |
| #define BIT_LNAON_WLBT_SEL BIT(28) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_BTGP_GPG3_FEN BIT(26) |
| #define BIT_BTGP_GPG2_FEN BIT(25) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_BTGP_JTAG_EN BIT(24) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_XTAL_CLK_EXTARNAL_EN BIT(23) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_BTGP_UART0_EN BIT(22) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_BTGP_UART1_EN BIT(21) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_BTGP_SPI_EN BIT(20) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_BTGP_GPIO_E2 BIT(19) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_BTGP_GPIO_EN BIT(18) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_SHIFT_BTGP_GPIO_SL 16 |
| #define BIT_MASK_BTGP_GPIO_SL 0x3 |
| #define BIT_BTGP_GPIO_SL(x) \ |
| (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL) |
| #define BIT_GET_BTGP_GPIO_SL(x) \ |
| (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_PAD_SDIO_SR BIT(14) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_GPIO14_OUTPUT_PL BIT(13) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_HOST_WAKE_PAD_PULL_EN BIT(12) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_HOST_WAKE_PAD_SL BIT(11) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_PAD_LNAON_SR BIT(10) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_PAD_LNAON_E2 BIT(9) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_SW_LNAON_G_SEL_DATA BIT(8) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_SW_LNAON_A_SEL_DATA BIT(7) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_PAD_PAPE_SR BIT(6) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_PAD_PAPE_E2 BIT(5) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_SW_PAPE_G_SEL_DATA BIT(4) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_SW_PAPE_A_SEL_DATA BIT(3) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_PAD_DPDT_SR BIT(2) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_PAD_DPDT_PAD_E2 BIT(1) |
| |
| /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ |
| |
| #define BIT_SW_DPDT_SEL_DATA BIT(0) |
| |
| /* 2 REG_SDIO_C2H (Offset 0x10250064) */ |
| |
| #define BIT_SHIFT_SDIO_C2H_MSG 0 |
| #define BIT_MASK_SDIO_C2H_MSG 0xffffffffL |
| #define BIT_SDIO_C2H_MSG(x) \ |
| (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG) |
| #define BIT_GET_SDIO_C2H_MSG(x) \ |
| (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_ISO_BD2PP BIT(31) |
| #define BIT_LDOV12B_EN BIT(30) |
| #define BIT_CKEN_BTGPS BIT(29) |
| #define BIT_FEN_BTGPS BIT(28) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_MULRW BIT(27) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_BTCPU_BOOTSEL BIT(27) |
| #define BIT_SPI_SPEEDUP BIT(26) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24) |
| #define BIT_CLKREQ_PAD_TYPE_SEL BIT(23) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_EN_CPL_TIMEOUT_PS BIT(22) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_ISO_BTPON2PP BIT(22) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_REG_TXDMA_FAIL_PS BIT(21) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_EN_HWENTR_L1 BIT(19) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_BT_HWROF_EN BIT(19) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_EN_ADV_CLKGATE BIT(18) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_BT_FUNC_EN BIT(18) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_BT_HWPDN_SL BIT(17) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_BT_DISN_EN BIT(16) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_BT_PDN_PULL_EN BIT(15) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_WL_PDN_PULL_EN BIT(14) |
| #define BIT_EXTERNAL_REQUEST_PL BIT(13) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_ISO_BA2PP BIT(11) |
| #define BIT_BT_AFE_LDO_EN BIT(10) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_BT_AFE_PLL_EN BIT(9) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_BT_DIG_CLK_EN BIT(8) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_WL_DRV_EXIST_IDX BIT(5) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_DOP_EHPAD BIT(4) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_WL_HWROF_EN BIT(3) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_WL_FUNC_EN BIT(2) |
| |
| /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ |
| |
| #define BIT_WL_HWPDN_SL BIT(1) |
| #define BIT_WL_HWPDN_EN BIT(0) |
| |
| /* 2 REG_SDM_DEBUG (Offset 0x006C) */ |
| |
| #define BIT_SHIFT_WLCLK_PHASE 0 |
| #define BIT_MASK_WLCLK_PHASE 0x1f |
| #define BIT_WLCLK_PHASE(x) \ |
| (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE) |
| #define BIT_GET_WLCLK_PHASE(x) \ |
| (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_DBG_GNT_WL_BT BIT(27) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_LTE_MUX_CTRL_PATH BIT(26) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_LTE_COEX_UART BIT(25) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_3W_LTE_WL_GPIO BIT(24) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_SDIO_INT_POLARITY BIT(19) |
| #define BIT_SDIO_INT BIT(18) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_SDIO_OFF_EN BIT(17) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_SDIO_ON_EN BIT(16) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10) |
| #define BIT_PCIE_WAIT_TIME BIT(9) |
| |
| /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ |
| |
| #define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_SHIFT_TSFT_SEL 29 |
| #define BIT_MASK_TSFT_SEL 0x7 |
| #define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL) |
| #define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_SHIFT_RPWM 24 |
| #define BIT_MASK_RPWM 0xff |
| #define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM) |
| #define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM) |
| |
| #define BIT_ROM_DLEN BIT(19) |
| |
| #define BIT_SHIFT_ROM_PGE 16 |
| #define BIT_MASK_ROM_PGE 0x7 |
| #define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE) |
| #define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_USB_HOST_PWR_OFF_EN BIT(12) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_SYM_LPS_BLOCK_EN BIT(11) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_USB_LPM_ACT_EN BIT(10) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_USB_LPM_NY BIT(9) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_USB_SUS_DIS BIT(8) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_SHIFT_SDIO_PAD_E 5 |
| #define BIT_MASK_SDIO_PAD_E 0x7 |
| #define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E) |
| #define BIT_GET_SDIO_PAD_E(x) \ |
| (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_USB_LPPLL_EN BIT(4) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_ROP_SW15 BIT(2) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_PCI_CKRDY_OPT BIT(1) |
| |
| /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ |
| |
| #define BIT_PCI_VAUX_EN BIT(0) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_ZCD_HW_AUTO_EN BIT(27) |
| #define BIT_ZCD_REGSEL BIT(26) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_SHIFT_AUTO_ZCD_IN_CODE 21 |
| #define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f |
| #define BIT_AUTO_ZCD_IN_CODE(x) \ |
| (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE) |
| #define BIT_GET_AUTO_ZCD_IN_CODE(x) \ |
| (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_SHIFT_ZCD_CODE_IN_L 16 |
| #define BIT_MASK_ZCD_CODE_IN_L 0x1f |
| #define BIT_ZCD_CODE_IN_L(x) \ |
| (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L) |
| #define BIT_GET_ZCD_CODE_IN_L(x) \ |
| (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_SHIFT_LDO_HV5_DUMMY 14 |
| #define BIT_MASK_LDO_HV5_DUMMY 0x3 |
| #define BIT_LDO_HV5_DUMMY(x) \ |
| (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY) |
| #define BIT_GET_LDO_HV5_DUMMY(x) \ |
| (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12 |
| #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3 |
| #define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) \ |
| (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) \ |
| << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) |
| #define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) \ |
| (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & \ |
| BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10 |
| #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3 |
| #define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) \ |
| (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) \ |
| << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) |
| #define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) \ |
| (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & \ |
| BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8 |
| #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3 |
| #define BIT_REG_LOAD33_BIT0_TO_BIT1(x) \ |
| (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) \ |
| << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) |
| #define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) \ |
| (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & \ |
| BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_REG_BYPASS_L BIT(7) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_REG_LDOF_L BIT(6) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_REG_TYPE_L_V1 BIT(5) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_ARENB_L BIT(3) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_SHIFT_CFC_L 1 |
| #define BIT_MASK_CFC_L 0x3 |
| #define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L) |
| #define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L) |
| |
| /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ |
| |
| #define BIT_REG_OCPS_L_V1 BIT(0) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_ANA_PORT_EN BIT(22) |
| #define BIT_MAC_PORT_EN BIT(21) |
| #define BIT_BOOT_FSPI_EN BIT(20) |
| #define BIT_FW_INIT_RDY BIT(15) |
| #define BIT_FW_DW_RDY BIT(14) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_SHIFT_CPU_CLK_SEL 12 |
| #define BIT_MASK_CPU_CLK_SEL 0x3 |
| #define BIT_CPU_CLK_SEL(x) \ |
| (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL) |
| #define BIT_GET_CPU_CLK_SEL(x) \ |
| (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_CCLK_CHG_MASK BIT(11) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_EMEM_TXBUF_DW_RDY BIT(9) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_EMEM_CHKSUM_OK BIT(8) |
| #define BIT_EMEM_DW_OK BIT(7) |
| #define BIT_TOGGLING BIT(7) |
| #define BIT_DMEM_CHKSUM_OK BIT(6) |
| #define BIT_ACK BIT(6) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_DMEM_DW_OK BIT(5) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_IMEM_CHKSUM_OK BIT(4) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_IMEM_DW_OK BIT(3) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) |
| |
| /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ |
| |
| #define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) |
| |
| /* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ |
| |
| #define BIT_32K_PERMISSION BIT(0) |
| |
| /* 2 REG_MCU_TST_CFG (Offset 0x0084) */ |
| |
| #define BIT_SHIFT_LBKTST 0 |
| #define BIT_MASK_LBKTST 0xffff |
| #define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST) |
| #define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST) |
| |
| /* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ |
| |
| #define BIT_PAD_CLK_XHGE_EN BIT(3) |
| #define BIT_INTER_CLK_EN BIT(2) |
| #define BIT_EN_RPT_TXCRC BIT(1) |
| #define BIT_DIS_RXDMA_STS BIT(0) |
| |
| /* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ |
| |
| #define BIT_INTR_CTRL BIT(4) |
| #define BIT_SDIO_VOLTAGE BIT(3) |
| #define BIT_BYPASS_INIT BIT(2) |
| |
| /* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ |
| |
| #define BIT_HCI_RESUME_RDY BIT(1) |
| #define BIT_HCI_SUS_REQ BIT(0) |
| |
| /* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ |
| |
| #define BIT_SHIFT_HOST_MSG_E1 16 |
| #define BIT_MASK_HOST_MSG_E1 0xffff |
| #define BIT_HOST_MSG_E1(x) \ |
| (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1) |
| #define BIT_GET_HOST_MSG_E1(x) \ |
| (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1) |
| |
| #define BIT_SHIFT_HOST_MSG_E0 0 |
| #define BIT_MASK_HOST_MSG_E0 0xffff |
| #define BIT_HOST_MSG_E0(x) \ |
| (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0) |
| #define BIT_GET_HOST_MSG_E0(x) \ |
| (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0) |
| |
| /* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */ |
| |
| #define BIT_SHIFT_CMDIN_2RESP_TIMER 0 |
| #define BIT_MASK_CMDIN_2RESP_TIMER 0xffff |
| #define BIT_CMDIN_2RESP_TIMER(x) \ |
| (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER) |
| #define BIT_GET_CMDIN_2RESP_TIMER(x) \ |
| (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER) |
| |
| /* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ |
| |
| #define BIT_SHIFT_SDIO_CMD_CRC_V1 0 |
| #define BIT_MASK_SDIO_CMD_CRC_V1 0xff |
| #define BIT_SDIO_CMD_CRC_V1(x) \ |
| (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1) |
| #define BIT_GET_SDIO_CMD_CRC_V1(x) \ |
| (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1) |
| |
| /* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */ |
| |
| #define BIT_SHIFT_HOST_MSG_E3 16 |
| #define BIT_MASK_HOST_MSG_E3 0xffff |
| #define BIT_HOST_MSG_E3(x) \ |
| (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3) |
| #define BIT_GET_HOST_MSG_E3(x) \ |
| (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3) |
| |
| #define BIT_SHIFT_HOST_MSG_E2 0 |
| #define BIT_MASK_HOST_MSG_E2 0xffff |
| #define BIT_HOST_MSG_E2(x) \ |
| (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2) |
| #define BIT_GET_HOST_MSG_E2(x) \ |
| (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_EABM BIT(31) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_ACKF BIT(30) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_DLDM BIT(29) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_ESWR BIT(28) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_PWMM BIT(27) |
| #define BIT_WLLPSOP_EECK BIT(26) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_WLMACOFF BIT(25) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_EXTAL BIT(24) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WL_SYNPON_VOLTSPDN BIT(23) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_WLBBOFF BIT(22) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WLLPSOP_WLMEM_DS BIT(21) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12 |
| #define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf |
| #define BIT_LPLDH12_VADJ_STEP_DN(x) \ |
| (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) \ |
| << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) |
| #define BIT_GET_LPLDH12_VADJ_STEP_DN(x) \ |
| (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & \ |
| BIT_MASK_LPLDH12_VADJ_STEP_DN) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_SHIFT_V15ADJ_L1_STEP_DN 8 |
| #define BIT_MASK_V15ADJ_L1_STEP_DN 0x7 |
| #define BIT_V15ADJ_L1_STEP_DN(x) \ |
| (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN) |
| #define BIT_GET_V15ADJ_L1_STEP_DN(x) \ |
| (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN) |
| |
| #define BIT_REGU_32K_CLK_EN BIT(1) |
| #define BIT_DRV_WLAN_INT_CLR BIT(1) |
| |
| /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ |
| |
| #define BIT_WL_LPS_EN BIT(0) |
| |
| /* 2 REG_SDIO_HSISR (Offset 0x10250090) */ |
| |
| #define BIT_DRV_WLAN_INT BIT(0) |
| |
| /* 2 REG_SDIO_HSIMR (Offset 0x10250091) */ |
| |
| #define BIT_HISR_MASK BIT(0) |
| |
| /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ |
| |
| #define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31) |
| |
| /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ |
| |
| #define BIT_ORDER_SDM BIT(30) |
| #define BIT_RFE_SEL_SDM BIT(29) |
| |
| #define BIT_SHIFT_REF_SEL 25 |
| #define BIT_MASK_REF_SEL 0xf |
| #define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL) |
| #define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL) |
| |
| /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ |
| |
| #define BIT_SHIFT_F0F_SDM 12 |
| #define BIT_MASK_F0F_SDM 0x1fff |
| #define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM) |
| #define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM) |
| |
| /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ |
| |
| #define BIT_SHIFT_F0N_SDM 9 |
| #define BIT_MASK_F0N_SDM 0x7 |
| #define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM) |
| #define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM) |
| |
| /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ |
| |
| #define BIT_SHIFT_DIVN_SDM 3 |
| #define BIT_MASK_DIVN_SDM 0x3f |
| #define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM) |
| #define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM) |
| |
| /* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ |
| |
| #define BIT_WLGP_DBC1EN BIT(15) |
| |
| #define BIT_SHIFT_WLGP_DBC1 8 |
| #define BIT_MASK_WLGP_DBC1 0xf |
| #define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1) |
| #define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1) |
| |
| #define BIT_WLGP_DBC0EN BIT(7) |
| |
| #define BIT_SHIFT_WLGP_DBC0 0 |
| #define BIT_MASK_WLGP_DBC0 0xf |
| #define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0) |
| #define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0) |
| |
| /* 2 REG_RPWM2 (Offset 0x009C) */ |
| |
| #define BIT_SHIFT_RPWM2 16 |
| #define BIT_MASK_RPWM2 0xffff |
| #define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2) |
| #define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2) |
| |
| /* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ |
| |
| #define BIT_SHIFT_FSM_MON_SEL 24 |
| #define BIT_MASK_FSM_MON_SEL 0x7 |
| #define BIT_FSM_MON_SEL(x) \ |
| (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL) |
| #define BIT_GET_FSM_MON_SEL(x) \ |
| (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL) |
| |
| #define BIT_DOP_ELDO BIT(23) |
| #define BIT_FSM_MON_UPD BIT(15) |
| |
| #define BIT_SHIFT_FSM_PAR 0 |
| #define BIT_MASK_FSM_PAR 0x7fff |
| #define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR) |
| #define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR) |
| |
| /* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ |
| |
| #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0 |
| #define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7 |
| #define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ |
| (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) \ |
| << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) |
| #define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ |
| (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & \ |
| BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) |
| |
| /* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ |
| |
| #define BIT_BT_INT_EN BIT(31) |
| |
| #define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16 |
| #define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff |
| #define BIT_RD_WR_WIFI_BT_INFO(x) \ |
| (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO) |
| #define BIT_GET_RD_WR_WIFI_BT_INFO(x) \ |
| (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO) |
| |
| /* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ |
| |
| #define BIT_PMC_WR_OVF BIT(8) |
| |
| #define BIT_SHIFT_WLPMC_ERRINT 0 |
| #define BIT_MASK_WLPMC_ERRINT 0xff |
| #define BIT_WLPMC_ERRINT(x) \ |
| (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT) |
| #define BIT_GET_WLPMC_ERRINT(x) \ |
| (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT) |
| |
| /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ |
| |
| #define BIT_SHIFT_SEL_V 30 |
| #define BIT_MASK_SEL_V 0x3 |
| #define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V) |
| #define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V) |
| |
| /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ |
| |
| #define BIT_TXFIFO_TH_INT BIT(30) |
| |
| /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ |
| |
| #define BIT_SEL_LDO_PC BIT(29) |
| |
| /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ |
| |
| #define BIT_SHIFT_CK_MON_SEL 26 |
| #define BIT_MASK_CK_MON_SEL 0x7 |
| #define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL) |
| #define BIT_GET_CK_MON_SEL(x) \ |
| (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL) |
| |
| /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ |
| |
| #define BIT_CK_MON_EN BIT(25) |
| #define BIT_FREF_EDGE BIT(24) |
| #define BIT_CK320M_EN BIT(23) |
| #define BIT_CK_5M_EN BIT(22) |
| #define BIT_TESTEN BIT(21) |
| |
| /* 2 REG_HIMR0 (Offset 0x00B0) */ |
| |
| #define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31) |
| #define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30) |
| #define BIT_PSTIMEOUT_MSK BIT(29) |
| #define BIT_GTINT4_MSK BIT(28) |
| #define BIT_GTINT3_MSK BIT(27) |
| #define BIT_TXBCN0ERR_MSK BIT(26) |
| #define BIT_TXBCN0OK_MSK BIT(25) |
| #define BIT_TSF_BIT32_TOGGLE_MSK BIT(24) |
| #define BIT_BCNDMAINT0_MSK BIT(20) |
| #define BIT_BCNDERR0_MSK BIT(16) |
| #define BIT_HSISR_IND_ON_INT_MSK BIT(15) |
| |
| /* 2 REG_HIMR0 (Offset 0x00B0) */ |
| |
| #define BIT_BCNDMAINT_E_MSK BIT(14) |
| |
| /* 2 REG_HIMR0 (Offset 0x00B0) */ |
| |
| #define BIT_CTWEND_MSK BIT(12) |
| #define BIT_HISR1_IND_MSK BIT(11) |
| |
| /* 2 REG_HIMR0 (Offset 0x00B0) */ |
| |
| #define BIT_C2HCMD_MSK BIT(10) |
| #define BIT_CPWM2_MSK BIT(9) |
| #define BIT_CPWM_MSK BIT(8) |
| #define BIT_HIGHDOK_MSK BIT(7) |
| #define BIT_MGTDOK_MSK BIT(6) |
| #define BIT_BKDOK_MSK BIT(5) |
| #define BIT_BEDOK_MSK BIT(4) |
| #define BIT_VIDOK_MSK BIT(3) |
| #define BIT_VODOK_MSK BIT(2) |
| #define BIT_RDU_MSK BIT(1) |
| #define BIT_RXOK_MSK BIT(0) |
| |
| /* 2 REG_HISR0 (Offset 0x00B4) */ |
| |
| #define BIT_TIMEOUT_INTERRUPT2 BIT(31) |
| |
| /* 2 REG_HISR0 (Offset 0x00B4) */ |
| |
| #define BIT_TIMEOUT_INTERRUTP1 BIT(30) |
| |
| /* 2 REG_HISR0 (Offset 0x00B4) */ |
| |
| #define BIT_PSTIMEOUT BIT(29) |
| #define BIT_GTINT4 BIT(28) |
| #define BIT_GTINT3 BIT(27) |
| #define BIT_TXBCN0ERR BIT(26) |
| #define BIT_TXBCN0OK BIT(25) |
| #define BIT_TSF_BIT32_TOGGLE BIT(24) |
| #define BIT_BCNDMAINT0 BIT(20) |
| #define BIT_BCNDERR0 BIT(16) |
| #define BIT_HSISR_IND_ON_INT BIT(15) |
| |
| /* 2 REG_HISR0 (Offset 0x00B4) */ |
| |
| #define BIT_BCNDMAINT_E BIT(14) |
| |
| /* 2 REG_HISR0 (Offset 0x00B4) */ |
| |
| #define BIT_CTWEND BIT(12) |
| |
| /* 2 REG_HISR0 (Offset 0x00B4) */ |
| |
| #define BIT_HISR1_IND_INT BIT(11) |
| #define BIT_C2HCMD BIT(10) |
| #define BIT_CPWM2 BIT(9) |
| #define BIT_CPWM BIT(8) |
| #define BIT_HIGHDOK BIT(7) |
| #define BIT_MGTDOK BIT(6) |
| #define BIT_BKDOK BIT(5) |
| #define BIT_BEDOK BIT(4) |
| #define BIT_VIDOK BIT(3) |
| #define BIT_VODOK BIT(2) |
| #define BIT_RDU BIT(1) |
| #define BIT_RXOK BIT(0) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_BTON_STS_UPDATE_MASK BIT(29) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_MCU_ERR_MASK BIT(28) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_BCNDMAINT7__MSK BIT(27) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_BCNDMAINT6__MSK BIT(26) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_BCNDMAINT5__MSK BIT(25) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_BCNDMAINT4__MSK BIT(24) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_BCNDMAINT3_MSK BIT(23) |
| #define BIT_BCNDMAINT2_MSK BIT(22) |
| #define BIT_BCNDMAINT1_MSK BIT(21) |
| #define BIT_BCNDERR7_MSK BIT(20) |
| #define BIT_BCNDERR6_MSK BIT(19) |
| #define BIT_BCNDERR5_MSK BIT(18) |
| #define BIT_BCNDERR4_MSK BIT(17) |
| #define BIT_BCNDERR3_MSK BIT(16) |
| #define BIT_BCNDERR2_MSK BIT(15) |
| #define BIT_BCNDERR1_MSK BIT(14) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_ATIMEND_E_MSK BIT(13) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_ATIMEND__MSK BIT(12) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_TXERR_MSK BIT(11) |
| #define BIT_RXERR_MSK BIT(10) |
| #define BIT_TXFOVW_MSK BIT(9) |
| #define BIT_FOVW_MSK BIT(8) |
| |
| /* 2 REG_HIMR1 (Offset 0x00B8) */ |
| |
| #define BIT_CPU_MGQ_TXDONE_MSK BIT(5) |
| #define BIT_PS_TIMER_C_MSK BIT(4) |
| #define BIT_PS_TIMER_B_MSK BIT(3) |
| #define BIT_PS_TIMER_A_MSK BIT(2) |
| #define BIT_CPUMGQ_TX_TIMER_MSK BIT(1) |
| |
| /* 2 REG_HISR1 (Offset 0x00BC) */ |
| |
| #define BIT_BTON_STS_UPDATE_INT BIT(29) |
| |
| /* 2 REG_HISR1 (Offset 0x00BC) */ |
| |
| #define BIT_MCU_ERR BIT(28) |
| |
| /* 2 REG_HISR1 (Offset 0x00BC) */ |
| |
| #define BIT_BCNDMAINT7 BIT(27) |
| #define BIT_BCNDMAINT6 BIT(26) |
| #define BIT_BCNDMAINT5 BIT(25) |
| #define BIT_BCNDMAINT4 BIT(24) |
| #define BIT_BCNDMAINT3 BIT(23) |
| #define BIT_BCNDMAINT2 BIT(22) |
| #define BIT_BCNDMAINT1 BIT(21) |
| #define BIT_BCNDERR7 BIT(20) |
| #define BIT_BCNDERR6 BIT(19) |
| #define BIT_BCNDERR5 BIT(18) |
| #define BIT_BCNDERR4 BIT(17) |
| #define BIT_BCNDERR3 BIT(16) |
| #define BIT_BCNDERR2 BIT(15) |
| #define BIT_BCNDERR1 BIT(14) |
| |
| /* 2 REG_HISR1 (Offset 0x00BC) */ |
| |
| #define BIT_ATIMEND_E BIT(13) |
| |
| /* 2 REG_HISR1 (Offset 0x00BC) */ |
| |
| #define BIT_ATIMEND BIT(12) |
| #define BIT_TXERR_INT BIT(11) |
| #define BIT_RXERR_INT BIT(10) |
| #define BIT_TXFOVW BIT(9) |
| #define BIT_FOVW BIT(8) |
| |
| /* 2 REG_HISR1 (Offset 0x00BC) */ |
| |
| #define BIT_CPU_MGQ_TXDONE BIT(5) |
| #define BIT_PS_TIMER_C BIT(4) |
| #define BIT_PS_TIMER_B BIT(3) |
| #define BIT_PS_TIMER_A BIT(2) |
| #define BIT_CPUMGQ_TX_TIMER BIT(1) |
| |
| /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ |
| |
| #define BIT_HR_FF_OVF BIT(6) |
| #define BIT_HR_FF_UDN BIT(5) |
| #define BIT_TXDMA_BUSY_ERR BIT(4) |
| #define BIT_TXDMA_VLD_ERR BIT(3) |
| #define BIT_QSEL_UNKNOWN_ERR BIT(2) |
| #define BIT_QSEL_MIS_ERR BIT(1) |
| |
| /* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */ |
| |
| #define BIT_SHIFT_DEBUG_ST 0 |
| #define BIT_MASK_DEBUG_ST 0xffffffffL |
| #define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST) |
| #define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST) |
| |
| /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ |
| |
| #define BIT_SDIO_OVERRD_ERR BIT(0) |
| |
| /* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C1) */ |
| |
| #define BIT_SHIFT_CMD_CRC_ERR_CNT 0 |
| #define BIT_MASK_CMD_CRC_ERR_CNT 0xff |
| #define BIT_CMD_CRC_ERR_CNT(x) \ |
| (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT) |
| #define BIT_GET_CMD_CRC_ERR_CNT(x) \ |
| (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT) |
| |
| /* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C2) */ |
| |
| #define BIT_SHIFT_DATA_CRC_ERR_CNT 0 |
| #define BIT_MASK_DATA_CRC_ERR_CNT 0xff |
| #define BIT_DATA_CRC_ERR_CNT(x) \ |
| (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT) |
| #define BIT_GET_DATA_CRC_ERR_CNT(x) \ |
| (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_USB3_USB2_TRANSITION BIT(20) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_SHIFT_USB23_SW_MODE_V1 18 |
| #define BIT_MASK_USB23_SW_MODE_V1 0x3 |
| #define BIT_USB23_SW_MODE_V1(x) \ |
| (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) |
| #define BIT_GET_USB23_SW_MODE_V1(x) \ |
| (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_NO_PDN_CHIPOFF_V1 BIT(17) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_RSM_EN_V1 BIT(16) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_LD_B12V_EN BIT(7) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_EECS_IOSEL_V1 BIT(6) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_EECS_DATA_O_V1 BIT(5) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_EECS_DATA_I_V1 BIT(4) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_EESK_IOSEL_V1 BIT(2) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_EESK_DATA_O_V1 BIT(1) |
| |
| /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ |
| |
| #define BIT_EESK_DATA_I_V1 BIT(0) |
| |
| /* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */ |
| |
| #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0 |
| #define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL |
| #define BIT_SDIO_CMD_ERR_CONTENT(x) \ |
| (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) \ |
| << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) |
| #define BIT_GET_SDIO_CMD_ERR_CONTENT(x) \ |
| (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & \ |
| BIT_MASK_SDIO_CMD_ERR_CONTENT) |
| |
| /* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ |
| |
| #define BIT_D3_CRC_ERR BIT(4) |
| #define BIT_D2_CRC_ERR BIT(3) |
| #define BIT_D1_CRC_ERR BIT(2) |
| #define BIT_D0_CRC_ERR BIT(1) |
| #define BIT_CMD_CRC_ERR BIT(0) |
| |
| /* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */ |
| |
| #define BIT_SHIFT_SDIO_DATA_CRC 0 |
| #define BIT_MASK_SDIO_DATA_CRC 0xff |
| #define BIT_SDIO_DATA_CRC(x) \ |
| (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC) |
| #define BIT_GET_SDIO_DATA_CRC(x) \ |
| (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC) |
| |
| /* 2 REG_SDIO_DATA_REPLY_TIME (Offset 0x102500CB) */ |
| |
| #define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0 |
| #define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7 |
| #define BIT_SDIO_DATA_REPLY_TIME(x) \ |
| (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) \ |
| << BIT_SHIFT_SDIO_DATA_REPLY_TIME) |
| #define BIT_GET_SDIO_DATA_REPLY_TIME(x) \ |
| (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & \ |
| BIT_MASK_SDIO_DATA_REPLY_TIME) |
| |
| /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ |
| |
| #define BIT_SHIFT_EFUSE_BURN_GNT 24 |
| #define BIT_MASK_EFUSE_BURN_GNT 0xff |
| #define BIT_EFUSE_BURN_GNT(x) \ |
| (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT) |
| #define BIT_GET_EFUSE_BURN_GNT(x) \ |
| (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT) |
| |
| /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ |
| |
| #define BIT_STOP_WL_PMC BIT(9) |
| #define BIT_STOP_SYM_PMC BIT(8) |
| |
| /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ |
| |
| #define BIT_REG_RST_WLPMC BIT(5) |
| #define BIT_REG_RST_PD12N BIT(4) |
| #define BIT_SYSON_DIS_WLREG_WRMSK BIT(3) |
| #define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2) |
| |
| #define BIT_SHIFT_SYSON_REG_ARB 0 |
| #define BIT_MASK_SYSON_REG_ARB 0x3 |
| #define BIT_SYSON_REG_ARB(x) \ |
| (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB) |
| #define BIT_GET_SYSON_REG_ARB(x) \ |
| (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB) |
| |
| /* 2 REG_BIST_CTRL (Offset 0x00D0) */ |
| |
| #define BIT_BIST_USB_DIS BIT(27) |
| |
| /* 2 REG_BIST_CTRL (Offset 0x00D0) */ |
| |
| #define BIT_BIST_PCI_DIS BIT(26) |
| |
| /* 2 REG_BIST_CTRL (Offset 0x00D0) */ |
| |
| #define BIT_BIST_BT_DIS BIT(25) |
| |
| /* 2 REG_BIST_CTRL (Offset 0x00D0) */ |
| |
| #define BIT_BIST_WL_DIS BIT(24) |
| |
| /* 2 REG_BIST_CTRL (Offset 0x00D0) */ |
| |
| #define BIT_SHIFT_BIST_RPT_SEL 16 |
| #define BIT_MASK_BIST_RPT_SEL 0xf |
| #define BIT_BIST_RPT_SEL(x) \ |
| (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL) |
| #define BIT_GET_BIST_RPT_SEL(x) \ |
| (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL) |
| |
| /* 2 REG_BIST_CTRL (Offset 0x00D0) */ |
| |
| #define BIT_BIST_RESUME_PS BIT(4) |
| |
| /* 2 REG_BIST_CTRL (Offset 0x00D0) */ |
| |
| #define BIT_BIST_RESUME BIT(3) |
| #define BIT_BIST_NORMAL BIT(2) |
| |
| /* 2 REG_BIST_CTRL (Offset 0x00D0) */ |
| |
| #define BIT_BIST_RSTN BIT(1) |
| #define BIT_BIST_CLK_EN BIT(0) |
| |
| /* 2 REG_BIST_RPT (Offset 0x00D4) */ |
| |
| #define BIT_SHIFT_MBIST_REPORT 0 |
| #define BIT_MASK_MBIST_REPORT 0xffffffffL |
| #define BIT_MBIST_REPORT(x) \ |
| (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT) |
| #define BIT_GET_MBIST_REPORT(x) \ |
| (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT) |
| |
| /* 2 REG_MEM_CTRL (Offset 0x00D8) */ |
| |
| #define BIT_UMEM_RME BIT(31) |
| |
| /* 2 REG_MEM_CTRL (Offset 0x00D8) */ |
| |
| #define BIT_SHIFT_BT_SPRAM 28 |
| #define BIT_MASK_BT_SPRAM 0x3 |
| #define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM) |
| #define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM) |
| |
| /* 2 REG_MEM_CTRL (Offset 0x00D8) */ |
| |
| #define BIT_SHIFT_BT_ROM 24 |
| #define BIT_MASK_BT_ROM 0xf |
| #define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM) |
| #define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM) |
| |
| #define BIT_SHIFT_PCI_DPRAM 10 |
| #define BIT_MASK_PCI_DPRAM 0x3 |
| #define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM) |
| #define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM) |
| |
| /* 2 REG_MEM_CTRL (Offset 0x00D8) */ |
| |
| #define BIT_SHIFT_PCI_SPRAM 8 |
| #define BIT_MASK_PCI_SPRAM 0x3 |
| #define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM) |
| #define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM) |
| |
| #define BIT_SHIFT_USB_SPRAM 6 |
| #define BIT_MASK_USB_SPRAM 0x3 |
| #define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM) |
| #define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM) |
| |
| /* 2 REG_MEM_CTRL (Offset 0x00D8) */ |
| |
| #define BIT_SHIFT_USB_SPRF 4 |
| #define BIT_MASK_USB_SPRF 0x3 |
| #define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF) |
| #define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF) |
| |
| /* 2 REG_MEM_CTRL (Offset 0x00D8) */ |
| |
| #define BIT_SHIFT_MCU_ROM 0 |
| #define BIT_MASK_MCU_ROM 0xf |
| #define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM) |
| #define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM) |
| |
| /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ |
| |
| #define BIT_SYN_AGPIO BIT(20) |
| |
| /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ |
| |
| #define BIT_XTAL_LP BIT(4) |
| #define BIT_XTAL_GM_SEP BIT(3) |
| |
| /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ |
| |
| #define BIT_SHIFT_XTAL_SEL_TOK 0 |
| #define BIT_MASK_XTAL_SEL_TOK 0x7 |
| #define BIT_XTAL_SEL_TOK(x) \ |
| (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK) |
| #define BIT_GET_XTAL_SEL_TOK(x) \ |
| (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK) |
| |
| /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ |
| |
| #define BIT_RD_SEL BIT(31) |
| |
| /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ |
| |
| #define BIT_USB_SIE_INTF_WE_V1 BIT(30) |
| #define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29) |
| #define BIT_USB_SIE_SELECT BIT(28) |
| |
| /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ |
| |
| #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16 |
| #define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff |
| #define BIT_USB_SIE_INTF_ADDR_V1(x) \ |
| (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) \ |
| << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) |
| #define BIT_GET_USB_SIE_INTF_ADDR_V1(x) \ |
| (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & \ |
| BIT_MASK_USB_SIE_INTF_ADDR_V1) |
| |
| /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ |
| |
| #define BIT_SHIFT_USB_SIE_INTF_RD 8 |
| #define BIT_MASK_USB_SIE_INTF_RD 0xff |
| #define BIT_USB_SIE_INTF_RD(x) \ |
| (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD) |
| #define BIT_GET_USB_SIE_INTF_RD(x) \ |
| (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD) |
| |
| #define BIT_SHIFT_USB_SIE_INTF_WD 0 |
| #define BIT_MASK_USB_SIE_INTF_WD 0xff |
| #define BIT_USB_SIE_INTF_WD(x) \ |
| (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD) |
| #define BIT_GET_USB_SIE_INTF_WD(x) \ |
| (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD) |
| |
| /* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ |
| |
| #define BIT_PCIE_MIO_BYIOREG BIT(13) |
| #define BIT_PCIE_MIO_RE BIT(12) |
| |
| #define BIT_SHIFT_PCIE_MIO_WE 8 |
| #define BIT_MASK_PCIE_MIO_WE 0xf |
| #define BIT_PCIE_MIO_WE(x) \ |
| (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE) |
| #define BIT_GET_PCIE_MIO_WE(x) \ |
| (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE) |
| |
| #define BIT_SHIFT_PCIE_MIO_ADDR 0 |
| #define BIT_MASK_PCIE_MIO_ADDR 0xff |
| #define BIT_PCIE_MIO_ADDR(x) \ |
| (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR) |
| #define BIT_GET_PCIE_MIO_ADDR(x) \ |
| (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR) |
| |
| /* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */ |
| |
| #define BIT_SHIFT_PCIE_MIO_DATA 0 |
| #define BIT_MASK_PCIE_MIO_DATA 0xffffffffL |
| #define BIT_PCIE_MIO_DATA(x) \ |
| (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA) |
| #define BIT_GET_PCIE_MIO_DATA(x) \ |
| (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA) |
| |
| /* 2 REG_WLRF1 (Offset 0x00EC) */ |
| |
| #define BIT_SHIFT_WLRF1_CTRL 24 |
| #define BIT_MASK_WLRF1_CTRL 0xff |
| #define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL) |
| #define BIT_GET_WLRF1_CTRL(x) \ |
| (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_SHIFT_TRP_ICFG 28 |
| #define BIT_MASK_TRP_ICFG 0xf |
| #define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG) |
| #define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_RF_TYPE_ID BIT(27) |
| #define BIT_BD_HCI_SEL BIT(26) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_BD_PKG_SEL BIT(25) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_SPSLDO_SEL BIT(24) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_RTL_ID BIT(23) |
| #define BIT_PAD_HWPD_IDN BIT(22) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_TESTMODE BIT(20) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_SHIFT_VENDOR_ID 16 |
| #define BIT_MASK_VENDOR_ID 0xf |
| #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) |
| #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_SHIFT_CHIP_VER 12 |
| #define BIT_MASK_CHIP_VER 0xf |
| #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) |
| #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_BD_MAC3 BIT(11) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_BD_MAC1 BIT(10) |
| #define BIT_BD_MAC2 BIT(9) |
| #define BIT_SIC_IDLE BIT(8) |
| #define BIT_SW_OFFLOAD_EN BIT(7) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_OCP_SHUTDN BIT(6) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_V15_VLD BIT(5) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_PCIRSTB BIT(4) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_PCLK_VLD BIT(3) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_UCLK_VLD BIT(2) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_ACLK_VLD BIT(1) |
| |
| /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ |
| |
| #define BIT_XCLK_VLD BIT(0) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_SHIFT_RF_RL_ID 28 |
| #define BIT_MASK_RF_RL_ID 0xf |
| #define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) |
| #define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_HPHY_ICFG BIT(19) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_SHIFT_SEL_0XC0 16 |
| #define BIT_MASK_SEL_0XC0 0x3 |
| #define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0) |
| #define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_SHIFT_HCI_SEL_V3 12 |
| #define BIT_MASK_HCI_SEL_V3 0x7 |
| #define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3) |
| #define BIT_GET_HCI_SEL_V3(x) \ |
| (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_USB_OPERATION_MODE BIT(10) |
| #define BIT_BT_PDN BIT(9) |
| #define BIT_AUTO_WLPON BIT(8) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_WL_MODE BIT(7) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_PKG_SEL_HCI BIT(6) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_SHIFT_PAD_HCI_SEL_V1 3 |
| #define BIT_MASK_PAD_HCI_SEL_V1 0x7 |
| #define BIT_PAD_HCI_SEL_V1(x) \ |
| (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1) |
| #define BIT_GET_PAD_HCI_SEL_V1(x) \ |
| (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1) |
| |
| /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ |
| |
| #define BIT_SHIFT_EFS_HCI_SEL_V1 0 |
| #define BIT_MASK_EFS_HCI_SEL_V1 0x7 |
| #define BIT_EFS_HCI_SEL_V1(x) \ |
| (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1) |
| #define BIT_GET_EFS_HCI_SEL_V1(x) \ |
| (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1) |
| |
| /* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ |
| |
| #define BIT_SIO_ALDN BIT(19) |
| #define BIT_USB_ALDN BIT(18) |
| #define BIT_PCI_ALDN BIT(17) |
| #define BIT_SYS_ALDN BIT(16) |
| |
| #define BIT_SHIFT_EPVID1 8 |
| #define BIT_MASK_EPVID1 0xff |
| #define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1) |
| #define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1) |
| |
| #define BIT_SHIFT_EPVID0 0 |
| #define BIT_MASK_EPVID0 0xff |
| #define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0) |
| #define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0) |
| |
| /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ |
| |
| #define BIT_HCI_SEL_EMBEDDED BIT(8) |
| |
| /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ |
| |
| #define BIT_SHIFT_HW_ID 0 |
| #define BIT_MASK_HW_ID 0xff |
| #define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID) |
| #define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID) |
| |
| /* 2 REG_CR (Offset 0x0100) */ |
| |
| #define BIT_SHIFT_LBMODE 24 |
| #define BIT_MASK_LBMODE 0x1f |
| #define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE) |
| #define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE) |
| |
| #define BIT_SHIFT_NETYPE1 18 |
| #define BIT_MASK_NETYPE1 0x3 |
| #define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1) |
| #define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1) |
| |
| #define BIT_SHIFT_NETYPE0 16 |
| #define BIT_MASK_NETYPE0 0x3 |
| #define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0) |
| #define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0) |
| |
| /* 2 REG_CR (Offset 0x0100) */ |
| |
| #define BIT_I2C_MAILBOX_EN BIT(12) |
| #define BIT_SHCUT_EN BIT(11) |
| |
| /* 2 REG_CR (Offset 0x0100) */ |
| |
| #define BIT_32K_CAL_TMR_EN BIT(10) |
| #define BIT_MAC_SEC_EN BIT(9) |
| #define BIT_ENSWBCN BIT(8) |
| #define BIT_MACRXEN BIT(7) |
| #define BIT_MACTXEN BIT(6) |
| #define BIT_SCHEDULE_EN BIT(5) |
| #define BIT_PROTOCOL_EN BIT(4) |
| #define BIT_RXDMA_EN BIT(3) |
| #define BIT_TXDMA_EN BIT(2) |
| #define BIT_HCI_RXDMA_EN BIT(1) |
| #define BIT_HCI_TXDMA_EN BIT(0) |
| |
| /* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ |
| |
| #define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0 |
| #define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff |
| #define BIT_PKT_BUFF_ACCESS_CTRL(x) \ |
| (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) \ |
| << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) |
| #define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) \ |
| (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & \ |
| BIT_MASK_PKT_BUFF_ACCESS_CTRL) |
| |
| /* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ |
| |
| #define BIT_TSF_CLK_STABLE BIT(15) |
| |
| #define BIT_SHIFT_I2C_M_BUS_GNT_FW 4 |
| #define BIT_MASK_I2C_M_BUS_GNT_FW 0x7 |
| #define BIT_I2C_M_BUS_GNT_FW(x) \ |
| (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW) |
| #define BIT_GET_I2C_M_BUS_GNT_FW(x) \ |
| (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW) |
| |
| #define BIT_I2C_M_GNT_FW BIT(3) |
| |
| #define BIT_SHIFT_I2C_M_SPEED 1 |
| #define BIT_MASK_I2C_M_SPEED 0x3 |
| #define BIT_I2C_M_SPEED(x) \ |
| (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED) |
| #define BIT_GET_I2C_M_SPEED(x) \ |
| (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED) |
| |
| #define BIT_I2C_M_UNLOCK BIT(0) |
| |
| /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ |
| |
| #define BIT_SHIFT_TXDMA_HIQ_MAP 14 |
| #define BIT_MASK_TXDMA_HIQ_MAP 0x3 |
| #define BIT_TXDMA_HIQ_MAP(x) \ |
| (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) |
| #define BIT_GET_TXDMA_HIQ_MAP(x) \ |
| (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP) |
| |
| #define BIT_SHIFT_TXDMA_MGQ_MAP 12 |
| #define BIT_MASK_TXDMA_MGQ_MAP 0x3 |
| #define BIT_TXDMA_MGQ_MAP(x) \ |
| (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) |
| #define BIT_GET_TXDMA_MGQ_MAP(x) \ |
| (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP) |
| |
| #define BIT_SHIFT_TXDMA_BKQ_MAP 10 |
| #define BIT_MASK_TXDMA_BKQ_MAP 0x3 |
| #define BIT_TXDMA_BKQ_MAP(x) \ |
| (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) |
| #define BIT_GET_TXDMA_BKQ_MAP(x) \ |
| (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP) |
| |
| #define BIT_SHIFT_TXDMA_BEQ_MAP 8 |
| #define BIT_MASK_TXDMA_BEQ_MAP 0x3 |
| #define BIT_TXDMA_BEQ_MAP(x) \ |
| (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) |
| #define BIT_GET_TXDMA_BEQ_MAP(x) \ |
| (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP) |
| |
| #define BIT_SHIFT_TXDMA_VIQ_MAP 6 |
| #define BIT_MASK_TXDMA_VIQ_MAP 0x3 |
| #define BIT_TXDMA_VIQ_MAP(x) \ |
| (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) |
| #define BIT_GET_TXDMA_VIQ_MAP(x) \ |
| (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP) |
| |
| #define BIT_SHIFT_TXDMA_VOQ_MAP 4 |
| #define BIT_MASK_TXDMA_VOQ_MAP 0x3 |
| #define BIT_TXDMA_VOQ_MAP(x) \ |
| (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) |
| #define BIT_GET_TXDMA_VOQ_MAP(x) \ |
| (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP) |
| |
| #define BIT_RXDMA_AGG_EN BIT(2) |
| #define BIT_RXSHFT_EN BIT(1) |
| #define BIT_RXDMA_ARBBW_EN BIT(0) |
| |
| /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ |
| |
| #define BIT_SHIFT_RXFFOVFL_RSV_V2 8 |
| #define BIT_MASK_RXFFOVFL_RSV_V2 0xf |
| #define BIT_RXFFOVFL_RSV_V2(x) \ |
| (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2) |
|
