drivers/usb/host/xhci-hub.c - arm/linux - Git at Google

 /*
  * xHCI host controller driver
  *
  * Copyright (C) 2008 Intel Corp.
  *
  * Author: Sarah Sharp
  * Some code borrowed from the Linux EHCI driver.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  * for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software Foundation,
  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */


 #include <linux/slab.h>
 #include <asm/unaligned.h>

 #include "xhci.h"
 #include "xhci-trace.h"

 #define	PORT_WAKE_BITS	(PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
 #define	PORT_RWC_BITS	(PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
 			 PORT_RC | PORT_PLC | PORT_PE)

 /* USB 3 BOS descriptor and a capability descriptors, combined.
  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  */
 static u8 usb_bos_descriptor [] = {
 	USB_DT_BOS_SIZE,		/*  __u8 bLength, 5 bytes */
 	USB_DT_BOS,			/*  __u8 bDescriptorType */
 	0x0F, 0x00,			/*  __le16 wTotalLength, 15 bytes */
 	0x1,				/*  __u8 bNumDeviceCaps */
 	/* First device capability, SuperSpeed */
 	USB_DT_USB_SS_CAP_SIZE,		/*  __u8 bLength, 10 bytes */
 	USB_DT_DEVICE_CAPABILITY,	/* Device Capability */
 	USB_SS_CAP_TYPE,		/* bDevCapabilityType, SUPERSPEED_USB */
 	0x00,				/* bmAttributes, LTM off by default */
 	USB_5GBPS_OPERATION, 0x00,	/* wSpeedsSupported, 5Gbps only */
 	0x03,				/* bFunctionalitySupport,
 					   USB 3.0 speed only */
 	0x00,				/* bU1DevExitLat, set later. */
 	0x00, 0x00,			/* __le16 bU2DevExitLat, set later. */
 	/* Second device capability, SuperSpeedPlus */
 	0x1c,				/* bLength 28, will be adjusted later */
 	USB_DT_DEVICE_CAPABILITY,	/* Device Capability */
 	USB_SSP_CAP_TYPE,		/* bDevCapabilityType SUPERSPEED_PLUS */
 	0x00,				/* bReserved 0 */
 	0x23, 0x00, 0x00, 0x00,		/* bmAttributes, SSAC=3 SSIC=1 */
 	0x01, 0x00,			/* wFunctionalitySupport */
 	0x00, 0x00,			/* wReserved 0 */
 	/* Default Sublink Speed Attributes, overwrite if custom PSI exists */
 	0x34, 0x00, 0x05, 0x00,		/* 5Gbps, symmetric, rx, ID = 4 */
 	0xb4, 0x00, 0x05, 0x00,		/* 5Gbps, symmetric, tx, ID = 4 */
 	0x35, 0x40, 0x0a, 0x00,		/* 10Gbps, SSP, symmetric, rx, ID = 5 */
 	0xb5, 0x40, 0x0a, 0x00,		/* 10Gbps, SSP, symmetric, tx, ID = 5 */
 };

 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
 				     u16 wLength)
 {
 	int i, ssa_count;
 	u32 temp;
 	u16 desc_size, ssp_cap_size, ssa_size = 0;
 	bool usb3_1 = false;

 	desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 	ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;

 	/* does xhci support USB 3.1 Enhanced SuperSpeed */
 	if (xhci->usb3_rhub.min_rev >= 0x01) {
 		/* does xhci provide a PSI table for SSA speed attributes? */
 		if (xhci->usb3_rhub.psi_count) {
 			/* two SSA entries for each unique PSI ID, RX and TX */
 			ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
 			ssa_size = ssa_count * sizeof(u32);
 			ssp_cap_size -= 16; /* skip copying the default SSA */
 		}
 		desc_size += ssp_cap_size;
 		usb3_1 = true;
 	}
 	memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));

 	if (usb3_1) {
 		/* modify bos descriptor bNumDeviceCaps and wTotalLength */
 		buf[4] += 1;
 		put_unaligned_le16(desc_size + ssa_size, &buf[2]);
 	}

 	if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
 		return wLength;

 	/* Indicate whether the host has LTM support. */
 	temp = readl(&xhci->cap_regs->hcc_params);
 	if (HCC_LTC(temp))
 		buf[8] |= USB_LTM_SUPPORT;

 	/* Set the U1 and U2 exit latencies. */
 	if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 		temp = readl(&xhci->cap_regs->hcs_params3);
 		buf[12] = HCS_U1_LATENCY(temp);
 		put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 	}

 	/* If PSI table exists, add the custom speed attributes from it */
 	if (usb3_1 && xhci->usb3_rhub.psi_count) {
 		u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 		int offset;

 		ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;

 		if (wLength < desc_size)
 			return wLength;
 		buf[ssp_cap_base] = ssp_cap_size + ssa_size;

 		/* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 		bm_attrib = (ssa_count - 1) & 0x1f;
 		bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 		put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);

 		if (wLength < desc_size + ssa_size)
 			return wLength;
 		/*
 		 * Create the Sublink Speed Attributes (SSA) array.
 		 * The xhci PSI field and USB 3.1 SSA fields are very similar,
 		 * but link type bits 7:6 differ for values 01b and 10b.
 		 * xhci has also only one PSI entry for a symmetric link when
 		 * USB 3.1 requires two SSA entries (RX and TX) for every link
 		 */
 		offset = desc_size;
 		for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 			psi = xhci->usb3_rhub.psi[i];
 			psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 			psi_exp = XHCI_EXT_PORT_PSIE(psi);
 			psi_mant = XHCI_EXT_PORT_PSIM(psi);

 			/* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 			for (; psi_exp < 3; psi_exp++)
 				psi_mant /= 1000;
 			if (psi_mant >= 10)
 				psi |= BIT(14);

 			if ((psi & PLT_MASK) == PLT_SYM) {
 			/* Symmetric, create SSA RX and TX from one PSI entry */
 				put_unaligned_le32(psi, &buf[offset]);
 				psi |= 1 << 7;  /* turn entry to TX */
 				offset += 4;
 				if (offset >= desc_size + ssa_size)
 					return desc_size + ssa_size;
 			} else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 				/* Asymetric RX, flip bits 7:6 for SSA */
 				psi ^= PLT_MASK;
 			}
 			put_unaligned_le32(psi, &buf[offset]);
 			offset += 4;
 			if (offset >= desc_size + ssa_size)
 				return desc_size + ssa_size;
 		}
 	}
 	/* ssa_size is 0 for other than usb 3.1 hosts */
 	return desc_size + ssa_size;
 }

 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 		struct usb_hub_descriptor *desc, int ports)
 {
 	u16 temp;

 	desc->bPwrOn2PwrGood = 10;	/* xhci section 5.4.9 says 20ms max */
 	desc->bHubContrCurrent = 0;

 	desc->bNbrPorts = ports;
 	temp = 0;
 	/* Bits 1:0 - support per-port power switching, or power always on */
 	if (HCC_PPC(xhci->hcc_params))
 		temp |= HUB_CHAR_INDV_PORT_LPSM;
 	else
 		temp |= HUB_CHAR_NO_LPSM;
 	/* Bit  2 - root hubs are not part of a compound device */
 	/* Bits 4:3 - individual port over current protection */
 	temp |= HUB_CHAR_INDV_PORT_OCPM;
 	/* Bits 6:5 - no TTs in root ports */
 	/* Bit  7 - no port indicators */
 	desc->wHubCharacteristics = cpu_to_le16(temp);
 }

 /* Fill in the USB 2.0 roothub descriptor */
 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 		struct usb_hub_descriptor *desc)
 {
 	int ports;
 	u16 temp;
 	__u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 	u32 portsc;
 	unsigned int i;

 	ports = xhci->num_usb2_ports;

 	xhci_common_hub_descriptor(xhci, desc, ports);
 	desc->bDescriptorType = USB_DT_HUB;
 	temp = 1 + (ports / 8);
 	desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;

 	/* The Device Removable bits are reported on a byte granularity.
 	 * If the port doesn't exist within that byte, the bit is set to 0.
 	 */
 	memset(port_removable, 0, sizeof(port_removable));
 	for (i = 0; i < ports; i++) {
 		portsc = readl(xhci->usb2_ports[i]);
 		/* If a device is removable, PORTSC reports a 0, same as in the
 		 * hub descriptor DeviceRemovable bits.
 		 */
 		if (portsc & PORT_DEV_REMOVE)
 			/* This math is hairy because bit 0 of DeviceRemovable
 			 * is reserved, and bit 1 is for port 1, etc.
 			 */
 			port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 	}

 	/* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 	 * ports on it.  The USB 2.0 specification says that there are two
 	 * variable length fields at the end of the hub descriptor:
 	 * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 	 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 	 * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 	 * 0xFF, so we initialize the both arrays (DeviceRemovable and
 	 * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 	 * set of ports that actually exist.
 	 */
 	memset(desc->u.hs.DeviceRemovable, 0xff,
 			sizeof(desc->u.hs.DeviceRemovable));
 	memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 			sizeof(desc->u.hs.PortPwrCtrlMask));

 	for (i = 0; i < (ports + 1 + 7) / 8; i++)
 		memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 				sizeof(__u8));
 }

 /* Fill in the USB 3.0 roothub descriptor */
 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 		struct usb_hub_descriptor *desc)
 {
 	int ports;
 	u16 port_removable;
 	u32 portsc;
 	unsigned int i;

 	ports = xhci->num_usb3_ports;
 	xhci_common_hub_descriptor(xhci, desc, ports);
 	desc->bDescriptorType = USB_DT_SS_HUB;
 	desc->bDescLength = USB_DT_SS_HUB_SIZE;

 	/* header decode latency should be zero for roothubs,
 	 * see section 4.23.5.2.
 	 */
 	desc->u.ss.bHubHdrDecLat = 0;
 	desc->u.ss.wHubDelay = 0;

 	port_removable = 0;
 	/* bit 0 is reserved, bit 1 is for port 1, etc. */
 	for (i = 0; i < ports; i++) {
 		portsc = readl(xhci->usb3_ports[i]);
 		if (portsc & PORT_DEV_REMOVE)
 			port_removable |= 1 << (i + 1);
 	}

 	desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 }

 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 		struct usb_hub_descriptor *desc)
 {

 	if (hcd->speed >= HCD_USB3)
 		xhci_usb3_hub_descriptor(hcd, xhci, desc);
 	else
 		xhci_usb2_hub_descriptor(hcd, xhci, desc);

 }

 static unsigned int xhci_port_speed(unsigned int port_status)
 {
 	if (DEV_LOWSPEED(port_status))
 		return USB_PORT_STAT_LOW_SPEED;
 	if (DEV_HIGHSPEED(port_status))
 		return USB_PORT_STAT_HIGH_SPEED;
 	/*
 	 * FIXME: Yes, we should check for full speed, but the core uses that as
 	 * a default in portspeed() in usb/core/hub.c (which is the only place
 	 * USB_PORT_STAT_*_SPEED is used).
 	 */
 	return 0;
 }

 /*
  * These bits are Read Only (RO) and should be saved and written to the
  * registers: 0, 3, 10:13, 30
  * connect status, over-current status, port speed, and device removable.
  * connect status and port speed are also sticky - meaning they're in
  * the AUX well and they aren't changed by a hot, warm, or cold reset.
  */
 #define	XHCI_PORT_RO	((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 /*
  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  * bits 5:8, 9, 14:15, 25:27
  * link state, port power, port indicator state, "wake on" enable state
  */
 #define XHCI_PORT_RWS	((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 /*
  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  * bit 4 (port reset)
  */
 #define	XHCI_PORT_RW1S	((1<<4))
 /*
  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  * bits 1, 17, 18, 19, 20, 21, 22, 23
  * port enable/disable, and
  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
  * over-current, reset, link state, and L1 change
  */
 #define XHCI_PORT_RW1CS	((1<<1) | (0x7f<<17))
 /*
  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  * latched in
  */
 #define	XHCI_PORT_RW	((1<<16))
 /*
  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  * bits 2, 24, 28:31
  */
 #define	XHCI_PORT_RZ	((1<<2) | (1<<24) | (0xf<<28))

 /*
  * Given a port state, this function returns a value that would result in the
  * port being in the same state, if the value was written to the port status
  * control register.
  * Save Read Only (RO) bits and save read/write bits where
  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  */
 u32 xhci_port_state_to_neutral(u32 state)
 {
 	/* Save read-only status and port state */
 	return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 }

 /*
  * find slot id based on port number.
  * @port: The one-based port number from one of the two split roothubs.
  */
 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 		u16 port)
 {
 	int slot_id;
 	int i;
 	enum usb_device_speed speed;

 	slot_id = 0;
 	for (i = 0; i < MAX_HC_SLOTS; i++) {
 		if (!xhci->devs[i])
 			continue;
 		speed = xhci->devs[i]->udev->speed;
 		if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 				&& xhci->devs[i]->fake_port == port) {
 			slot_id = i;
 			break;
 		}
 	}

 	return slot_id;
 }

 /*
  * Stop device
  * It issues stop endpoint command for EP 0 to 30. And wait the last command
  * to complete.
  * suspend will set to 1, if suspend bit need to set in command.
  */
 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 {
 	struct xhci_virt_device *virt_dev;
 	struct xhci_command *cmd;
 	unsigned long flags;
 	int ret;
 	int i;

 	ret = 0;
 	virt_dev = xhci->devs[slot_id];
 	if (!virt_dev)
 		return -ENODEV;

 	trace_xhci_stop_device(virt_dev);

 	cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 	if (!cmd)
 		return -ENOMEM;

 	spin_lock_irqsave(&xhci->lock, flags);
 	for (i = LAST_EP_INDEX; i > 0; i--) {
 		if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 			struct xhci_ep_ctx *ep_ctx;
 			struct xhci_command *command;

 			ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);

 			/* Check ep is running, required by AMD SNPS 3.1 xHC */
 			if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 				continue;

 			command = xhci_alloc_command(xhci, false, false,
 						     GFP_NOWAIT);
 			if (!command) {
 				spin_unlock_irqrestore(&xhci->lock, flags);
 				ret = -ENOMEM;
 				goto cmd_cleanup;
 			}

 			ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 						       i, suspend);
 			if (ret) {
 				spin_unlock_irqrestore(&xhci->lock, flags);
 				xhci_free_command(xhci, command);
 				goto cmd_cleanup;
 			}
 		}
 	}
 	ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 	if (ret) {
 		spin_unlock_irqrestore(&xhci->lock, flags);
 		goto cmd_cleanup;
 	}

 	xhci_ring_cmd_db(xhci);
 	spin_unlock_irqrestore(&xhci->lock, flags);

 	/* Wait for last stop endpoint command to finish */
 	wait_for_completion(cmd->completion);

 	if (cmd->status == COMP_COMMAND_ABORTED ||
 	    cmd->status == COMP_COMMAND_RING_STOPPED) {
 		xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 		ret = -ETIME;
 	}

 cmd_cleanup:
 	xhci_free_command(xhci, cmd);
 	return ret;
 }

 /*
  * Ring device, it rings the all doorbells unconditionally.
  */
 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 {
 	int i, s;
 	struct xhci_virt_ep *ep;

 	for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 		ep = &xhci->devs[slot_id]->eps[i];

 		if (ep->ep_state & EP_HAS_STREAMS) {
 			for (s = 1; s < ep->stream_info->num_streams; s++)
 				xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 		} else if (ep->ring && ep->ring->dequeue) {
 			xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 		}
 	}

 	return;
 }

 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 		u16 wIndex, __le32 __iomem *addr, u32 port_status)
 {
 	/* Don't allow the USB core to disable SuperSpeed ports. */
 	if (hcd->speed >= HCD_USB3) {
 		xhci_dbg(xhci, "Ignoring request to disable "
 				"SuperSpeed port.\n");
 		return;
 	}

 	if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 		xhci_dbg(xhci,
 			 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 		return;
 	}

 	/* Write 1 to disable the port */
 	writel(port_status | PORT_PE, addr);
 	port_status = readl(addr);
 	xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 			wIndex, port_status);
 }

 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 		u16 wIndex, __le32 __iomem *addr, u32 port_status)
 {
 	char *port_change_bit;
 	u32 status;

 	switch (wValue) {
 	case USB_PORT_FEAT_C_RESET:
 		status = PORT_RC;
 		port_change_bit = "reset";
 		break;
 	case USB_PORT_FEAT_C_BH_PORT_RESET:
 		status = PORT_WRC;
 		port_change_bit = "warm(BH) reset";
 		break;
 	case USB_PORT_FEAT_C_CONNECTION:
 		status = PORT_CSC;
 		port_change_bit = "connect";
 		break;
 	case USB_PORT_FEAT_C_OVER_CURRENT:
 		status = PORT_OCC;
 		port_change_bit = "over-current";
 		break;
 	case USB_PORT_FEAT_C_ENABLE:
 		status = PORT_PEC;
 		port_change_bit = "enable/disable";
 		break;
 	case USB_PORT_FEAT_C_SUSPEND:
 		status = PORT_PLC;
 		port_change_bit = "suspend/resume";
 		break;
 	case USB_PORT_FEAT_C_PORT_LINK_STATE:
 		status = PORT_PLC;
 		port_change_bit = "link state";
 		break;
 	case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 		status = PORT_CEC;
 		port_change_bit = "config error";
 		break;
 	default:
 		/* Should never happen */
 		return;
 	}
 	/* Change bits are all write 1 to clear */
 	writel(port_status | status, addr);
 	port_status = readl(addr);
 	xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 			port_change_bit, wIndex, port_status);
 }

 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 {
 	int max_ports;
 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);

 	if (hcd->speed >= HCD_USB3) {
 		max_ports = xhci->num_usb3_ports;
 		*port_array = xhci->usb3_ports;
 	} else {
 		max_ports = xhci->num_usb2_ports;
 		*port_array = xhci->usb2_ports;
 	}

 	return max_ports;
 }

 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
 {
 	__le32 __iomem **port_array;

 	xhci_get_ports(hcd, &port_array);
 	return port_array[index];
 }

 /*
  * xhci_set_port_power() must be called with xhci->lock held.
  * It will release and re-aquire the lock while calling ACPI
  * method.
  */
 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 				u16 index, bool on, unsigned long *flags)
 {
 	__le32 __iomem *addr;
 	u32 temp;

 	addr = xhci_get_port_io_addr(hcd, index);
 	temp = readl(addr);
 	temp = xhci_port_state_to_neutral(temp);
 	if (on) {
 		/* Power on */
 		writel(temp | PORT_POWER, addr);
 		temp = readl(addr);
 		xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 						index, temp);
 	} else {
 		/* Power off */
 		writel(temp & ~PORT_POWER, addr);
 	}

 	spin_unlock_irqrestore(&xhci->lock, *flags);
 	temp = usb_acpi_power_manageable(hcd->self.root_hub,
 					index);
 	if (temp)
 		usb_acpi_set_power_state(hcd->self.root_hub,
 			index, on);
 	spin_lock_irqsave(&xhci->lock, *flags);
 }

 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 	u16 test_mode, u16 wIndex)
 {
 	u32 temp;
 	__le32 __iomem *addr;

 	/* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
 	addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
 	temp = readl(addr + PORTPMSC);
 	temp |= test_mode << PORT_TEST_MODE_SHIFT;
 	writel(temp, addr + PORTPMSC);
 	xhci->test_mode = test_mode;
 	if (test_mode == TEST_FORCE_EN)
 		xhci_start(xhci);
 }

 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 				u16 test_mode, u16 wIndex, unsigned long *flags)
 {
 	int i, retval;

 	/* Disable all Device Slots */
 	xhci_dbg(xhci, "Disable all slots\n");
 	spin_unlock_irqrestore(&xhci->lock, *flags);
 	for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 		retval = xhci_disable_slot(xhci, NULL, i);
 		if (retval)
 			xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 				 i, retval);
 	}
 	spin_lock_irqsave(&xhci->lock, *flags);
 	/* Put all ports to the Disable state by clear PP */
 	xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 	/* Power off USB3 ports*/
 	for (i = 0; i < xhci->num_usb3_ports; i++)
 		xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 	/* Power off USB2 ports*/
 	for (i = 0; i < xhci->num_usb2_ports; i++)
 		xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 	/* Stop the controller */
 	xhci_dbg(xhci, "Stop controller\n");
 	retval = xhci_halt(xhci);
 	if (retval)
 		return retval;
 	/* Disable runtime PM for test mode */
 	pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 	/* Set PORTPMSC.PTC field to enter selected test mode */
 	/* Port is selected by wIndex. port_id = wIndex + 1 */
 	xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 					test_mode, wIndex + 1);
 	xhci_port_set_test_mode(xhci, test_mode, wIndex);
 	return retval;
 }

 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 {
 	int retval;

 	if (!xhci->test_mode) {
 		xhci_err(xhci, "Not in test mode, do nothing.\n");
 		return 0;
 	}
 	if (xhci->test_mode == TEST_FORCE_EN &&
 		!(xhci->xhc_state & XHCI_STATE_HALTED)) {
 		retval = xhci_halt(xhci);
 		if (retval)
 			return retval;
 	}
 	pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 	xhci->test_mode = 0;
 	return xhci_reset(xhci);
 }

 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 				int port_id, u32 link_state)
 {
 	u32 temp;

 	temp = readl(port_array[port_id]);
 	temp = xhci_port_state_to_neutral(temp);
 	temp &= ~PORT_PLS_MASK;
 	temp |= PORT_LINK_STROBE | link_state;
 	writel(temp, port_array[port_id]);
 }

 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 		__le32 __iomem **port_array, int port_id, u16 wake_mask)
	/*
	* xHCI host controller driver
	*
	* Copyright (C) 2008 Intel Corp.
	*
	* Author: Sarah Sharp
	* Some code borrowed from the Linux EHCI driver.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful, but
	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	* for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software Foundation,
	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	*/


	#include <linux/slab.h>
	#include <asm/unaligned.h>

	#include "xhci.h"
	#include "xhci-trace.h"

	#define PORT_WAKE_BITS (PORT_WKOC_E \| PORT_WKDISC_E \| PORT_WKCONN_E)
	#define PORT_RWC_BITS (PORT_CSC \| PORT_PEC \| PORT_WRC \| PORT_OCC \| \
	PORT_RC \| PORT_PLC \| PORT_PE)

	/* USB 3 BOS descriptor and a capability descriptors, combined.
	* Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
	*/
	static u8 usb_bos_descriptor [] = {
	USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
	USB_DT_BOS, /* __u8 bDescriptorType */
	0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
	0x1, /* __u8 bNumDeviceCaps */
	/* First device capability, SuperSpeed */
	USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
	USB_DT_DEVICE_CAPABILITY, /* Device Capability */
	USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
	0x00, /* bmAttributes, LTM off by default */
	USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
	0x03, /* bFunctionalitySupport,
	USB 3.0 speed only */
	0x00, /* bU1DevExitLat, set later. */
	0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
	/* Second device capability, SuperSpeedPlus */
	0x1c, /* bLength 28, will be adjusted later */
	USB_DT_DEVICE_CAPABILITY, /* Device Capability */
	USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
	0x00, /* bReserved 0 */
	0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
	0x01, 0x00, /* wFunctionalitySupport */
	0x00, 0x00, /* wReserved 0 */
	/* Default Sublink Speed Attributes, overwrite if custom PSI exists */
	0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
	0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
	0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
	0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
	};

	static int xhci_create_usb3_bos_desc(struct xhci_hcd xhci, char buf,
	u16 wLength)
	{
	int i, ssa_count;
	u32 temp;
	u16 desc_size, ssp_cap_size, ssa_size = 0;
	bool usb3_1 = false;

	desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
	ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;

	/* does xhci support USB 3.1 Enhanced SuperSpeed */
	if (xhci->usb3_rhub.min_rev >= 0x01) {
	/* does xhci provide a PSI table for SSA speed attributes? */
	if (xhci->usb3_rhub.psi_count) {
	/* two SSA entries for each unique PSI ID, RX and TX */
	ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
	ssa_size = ssa_count * sizeof(u32);
	ssp_cap_size -= 16; /* skip copying the default SSA */
	}
	desc_size += ssp_cap_size;
	usb3_1 = true;
	}
	memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));

	if (usb3_1) {
	/* modify bos descriptor bNumDeviceCaps and wTotalLength */
	buf[4] += 1;
	put_unaligned_le16(desc_size + ssa_size, &buf[2]);
	}

	if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
	return wLength;

	/* Indicate whether the host has LTM support. */
	temp = readl(&xhci->cap_regs->hcc_params);
	if (HCC_LTC(temp))
	buf[8] \|= USB_LTM_SUPPORT;

	/* Set the U1 and U2 exit latencies. */
	if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
	temp = readl(&xhci->cap_regs->hcs_params3);
	buf[12] = HCS_U1_LATENCY(temp);
	put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
	}

	/* If PSI table exists, add the custom speed attributes from it */
	if (usb3_1 && xhci->usb3_rhub.psi_count) {
	u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
	int offset;

	ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;

	if (wLength < desc_size)
	return wLength;
	buf[ssp_cap_base] = ssp_cap_size + ssa_size;

	/* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
	bm_attrib = (ssa_count - 1) & 0x1f;
	bm_attrib \|= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
	put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);

	if (wLength < desc_size + ssa_size)
	return wLength;
	/*
	* Create the Sublink Speed Attributes (SSA) array.
	* The xhci PSI field and USB 3.1 SSA fields are very similar,
	* but link type bits 7:6 differ for values 01b and 10b.
	* xhci has also only one PSI entry for a symmetric link when
	* USB 3.1 requires two SSA entries (RX and TX) for every link
	*/
	offset = desc_size;
	for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
	psi = xhci->usb3_rhub.psi[i];
	psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
	psi_exp = XHCI_EXT_PORT_PSIE(psi);
	psi_mant = XHCI_EXT_PORT_PSIM(psi);

	/* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
	for (; psi_exp < 3; psi_exp++)
	psi_mant /= 1000;
	if (psi_mant >= 10)
	psi \|= BIT(14);

	if ((psi & PLT_MASK) == PLT_SYM) {
	/* Symmetric, create SSA RX and TX from one PSI entry */
	put_unaligned_le32(psi, &buf[offset]);
	psi \|= 1 << 7; /* turn entry to TX */
	offset += 4;
	if (offset >= desc_size + ssa_size)
	return desc_size + ssa_size;
	} else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
	/* Asymetric RX, flip bits 7:6 for SSA */
	psi ^= PLT_MASK;
	}
	put_unaligned_le32(psi, &buf[offset]);
	offset += 4;
	if (offset >= desc_size + ssa_size)
	return desc_size + ssa_size;
	}
	}
	/* ssa_size is 0 for other than usb 3.1 hosts */
	return desc_size + ssa_size;
	}

	static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
	struct usb_hub_descriptor *desc, int ports)
	{
	u16 temp;

	desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
	desc->bHubContrCurrent = 0;

	desc->bNbrPorts = ports;
	temp = 0;
	/* Bits 1:0 - support per-port power switching, or power always on */
	if (HCC_PPC(xhci->hcc_params))
	temp \|= HUB_CHAR_INDV_PORT_LPSM;
	else
	temp \|= HUB_CHAR_NO_LPSM;
	/* Bit 2 - root hubs are not part of a compound device */
	/* Bits 4:3 - individual port over current protection */
	temp \|= HUB_CHAR_INDV_PORT_OCPM;
	/* Bits 6:5 - no TTs in root ports */
	/* Bit 7 - no port indicators */
	desc->wHubCharacteristics = cpu_to_le16(temp);
	}

	/* Fill in the USB 2.0 roothub descriptor */
	static void xhci_usb2_hub_descriptor(struct usb_hcd hcd, struct xhci_hcd xhci,
	struct usb_hub_descriptor *desc)
	{
	int ports;
	u16 temp;
	__u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
	u32 portsc;
	unsigned int i;

	ports = xhci->num_usb2_ports;

	xhci_common_hub_descriptor(xhci, desc, ports);
	desc->bDescriptorType = USB_DT_HUB;
	temp = 1 + (ports / 8);
	desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;

	/* The Device Removable bits are reported on a byte granularity.
	* If the port doesn't exist within that byte, the bit is set to 0.
	*/
	memset(port_removable, 0, sizeof(port_removable));
	for (i = 0; i < ports; i++) {
	portsc = readl(xhci->usb2_ports[i]);
	/* If a device is removable, PORTSC reports a 0, same as in the
	* hub descriptor DeviceRemovable bits.
	*/
	if (portsc & PORT_DEV_REMOVE)
	/* This math is hairy because bit 0 of DeviceRemovable
	* is reserved, and bit 1 is for port 1, etc.
	*/
	port_removable[(i + 1) / 8] \|= 1 << ((i + 1) % 8);
	}

	/* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
	* ports on it. The USB 2.0 specification says that there are two
	* variable length fields at the end of the hub descriptor:
	* DeviceRemovable and PortPwrCtrlMask. But since we can have less than
	* USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
	* to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
	* 0xFF, so we initialize the both arrays (DeviceRemovable and
	* PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
	* set of ports that actually exist.
	*/
	memset(desc->u.hs.DeviceRemovable, 0xff,
	sizeof(desc->u.hs.DeviceRemovable));
	memset(desc->u.hs.PortPwrCtrlMask, 0xff,
	sizeof(desc->u.hs.PortPwrCtrlMask));

	for (i = 0; i < (ports + 1 + 7) / 8; i++)
	memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
	sizeof(__u8));
	}

	/* Fill in the USB 3.0 roothub descriptor */
	static void xhci_usb3_hub_descriptor(struct usb_hcd hcd, struct xhci_hcd xhci,
	struct usb_hub_descriptor *desc)
	{
	int ports;
	u16 port_removable;
	u32 portsc;
	unsigned int i;

	ports = xhci->num_usb3_ports;
	xhci_common_hub_descriptor(xhci, desc, ports);
	desc->bDescriptorType = USB_DT_SS_HUB;
	desc->bDescLength = USB_DT_SS_HUB_SIZE;

	/* header decode latency should be zero for roothubs,
	* see section 4.23.5.2.
	*/
	desc->u.ss.bHubHdrDecLat = 0;
	desc->u.ss.wHubDelay = 0;

	port_removable = 0;
	/* bit 0 is reserved, bit 1 is for port 1, etc. */
	for (i = 0; i < ports; i++) {
	portsc = readl(xhci->usb3_ports[i]);
	if (portsc & PORT_DEV_REMOVE)
	port_removable \|= 1 << (i + 1);
	}

	desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
	}

	static void xhci_hub_descriptor(struct usb_hcd hcd, struct xhci_hcd xhci,
	struct usb_hub_descriptor *desc)
	{

	if (hcd->speed >= HCD_USB3)
	xhci_usb3_hub_descriptor(hcd, xhci, desc);
	else
	xhci_usb2_hub_descriptor(hcd, xhci, desc);

	}

	static unsigned int xhci_port_speed(unsigned int port_status)
	{
	if (DEV_LOWSPEED(port_status))
	return USB_PORT_STAT_LOW_SPEED;
	if (DEV_HIGHSPEED(port_status))
	return USB_PORT_STAT_HIGH_SPEED;
	/*
	* FIXME: Yes, we should check for full speed, but the core uses that as
	* a default in portspeed() in usb/core/hub.c (which is the only place
	* USB_PORT_STAT_*_SPEED is used).
	*/
	return 0;
	}

	/*
	* These bits are Read Only (RO) and should be saved and written to the
	* registers: 0, 3, 10:13, 30
	* connect status, over-current status, port speed, and device removable.
	* connect status and port speed are also sticky - meaning they're in
	* the AUX well and they aren't changed by a hot, warm, or cold reset.
	*/
	#define XHCI_PORT_RO ((1<<0) \| (1<<3) \| (0xf<<10) \| (1<<30))
	/*
	* These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
	* bits 5:8, 9, 14:15, 25:27
	* link state, port power, port indicator state, "wake on" enable state
	*/
	#define XHCI_PORT_RWS ((0xf<<5) \| (1<<9) \| (0x3<<14) \| (0x7<<25))
	/*
	* These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
	* bit 4 (port reset)
	*/
	#define XHCI_PORT_RW1S ((1<<4))
	/*
	* These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
	* bits 1, 17, 18, 19, 20, 21, 22, 23
	* port enable/disable, and
	* change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
	* over-current, reset, link state, and L1 change
	*/
	#define XHCI_PORT_RW1CS ((1<<1) \| (0x7f<<17))
	/*
	* Bit 16 is RW, and writing a '1' to it causes the link state control to be
	* latched in
	*/
	#define XHCI_PORT_RW ((1<<16))
	/*
	* These bits are Reserved Zero (RsvdZ) and zero should be written to them:
	* bits 2, 24, 28:31
	*/
	#define XHCI_PORT_RZ ((1<<2) \| (1<<24) \| (0xf<<28))

	/*
	* Given a port state, this function returns a value that would result in the
	* port being in the same state, if the value was written to the port status
	* control register.
	* Save Read Only (RO) bits and save read/write bits where
	* writing a 0 clears the bit and writing a 1 sets the bit (RWS).
	* For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
	*/
	u32 xhci_port_state_to_neutral(u32 state)
	{
	/* Save read-only status and port state */
	return (state & XHCI_PORT_RO) \| (state & XHCI_PORT_RWS);
	}

	/*
	* find slot id based on port number.
	* @port: The one-based port number from one of the two split roothubs.
	*/
	int xhci_find_slot_id_by_port(struct usb_hcd hcd, struct xhci_hcd xhci,
	u16 port)
	{
	int slot_id;
	int i;
	enum usb_device_speed speed;

	slot_id = 0;
	for (i = 0; i < MAX_HC_SLOTS; i++) {
	if (!xhci->devs[i])
	continue;
	speed = xhci->devs[i]->udev->speed;
	if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
	&& xhci->devs[i]->fake_port == port) {
	slot_id = i;
	break;
	}
	}

	return slot_id;
	}

	/*
	* Stop device
	* It issues stop endpoint command for EP 0 to 30. And wait the last command
	* to complete.
	* suspend will set to 1, if suspend bit need to set in command.
	*/
	static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
	{
	struct xhci_virt_device *virt_dev;
	struct xhci_command *cmd;
	unsigned long flags;
	int ret;
	int i;

	ret = 0;
	virt_dev = xhci->devs[slot_id];
	if (!virt_dev)
	return -ENODEV;

	trace_xhci_stop_device(virt_dev);

	cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
	if (!cmd)
	return -ENOMEM;

	spin_lock_irqsave(&xhci->lock, flags);
	for (i = LAST_EP_INDEX; i > 0; i--) {
	if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
	struct xhci_ep_ctx *ep_ctx;
	struct xhci_command *command;

	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);

	/* Check ep is running, required by AMD SNPS 3.1 xHC */
	if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
	continue;

	command = xhci_alloc_command(xhci, false, false,
	GFP_NOWAIT);
	if (!command) {
	spin_unlock_irqrestore(&xhci->lock, flags);
	ret = -ENOMEM;
	goto cmd_cleanup;
	}

	ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
	i, suspend);
	if (ret) {
	spin_unlock_irqrestore(&xhci->lock, flags);
	xhci_free_command(xhci, command);
	goto cmd_cleanup;
	}
	}
	}
	ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
	if (ret) {
	spin_unlock_irqrestore(&xhci->lock, flags);
	goto cmd_cleanup;
	}

	xhci_ring_cmd_db(xhci);
	spin_unlock_irqrestore(&xhci->lock, flags);

	/* Wait for last stop endpoint command to finish */
	wait_for_completion(cmd->completion);

	if (cmd->status == COMP_COMMAND_ABORTED \|\|
	cmd->status == COMP_COMMAND_RING_STOPPED) {
	xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
	ret = -ETIME;
	}

	cmd_cleanup:
	xhci_free_command(xhci, cmd);
	return ret;
	}

	/*
	* Ring device, it rings the all doorbells unconditionally.
	*/
	void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
	{
	int i, s;
	struct xhci_virt_ep *ep;

	for (i = 0; i < LAST_EP_INDEX + 1; i++) {
	ep = &xhci->devs[slot_id]->eps[i];

	if (ep->ep_state & EP_HAS_STREAMS) {
	for (s = 1; s < ep->stream_info->num_streams; s++)
	xhci_ring_ep_doorbell(xhci, slot_id, i, s);
	} else if (ep->ring && ep->ring->dequeue) {
	xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
	}
	}

	return;
	}

	static void xhci_disable_port(struct usb_hcd hcd, struct xhci_hcd xhci,
	u16 wIndex, __le32 __iomem *addr, u32 port_status)
	{
	/* Don't allow the USB core to disable SuperSpeed ports. */
	if (hcd->speed >= HCD_USB3) {
	xhci_dbg(xhci, "Ignoring request to disable "
	"SuperSpeed port.\n");
	return;
	}

	if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
	xhci_dbg(xhci,
	"Broken Port Enabled/Disabled, ignoring port disable request.\n");
	return;
	}

	/* Write 1 to disable the port */
	writel(port_status \| PORT_PE, addr);
	port_status = readl(addr);
	xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
	wIndex, port_status);
	}

	static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
	u16 wIndex, __le32 __iomem *addr, u32 port_status)
	{
	char *port_change_bit;
	u32 status;

	switch (wValue) {
	case USB_PORT_FEAT_C_RESET:
	status = PORT_RC;
	port_change_bit = "reset";
	break;
	case USB_PORT_FEAT_C_BH_PORT_RESET:
	status = PORT_WRC;
	port_change_bit = "warm(BH) reset";
	break;
	case USB_PORT_FEAT_C_CONNECTION:
	status = PORT_CSC;
	port_change_bit = "connect";
	break;
	case USB_PORT_FEAT_C_OVER_CURRENT:
	status = PORT_OCC;
	port_change_bit = "over-current";
	break;
	case USB_PORT_FEAT_C_ENABLE:
	status = PORT_PEC;
	port_change_bit = "enable/disable";
	break;
	case USB_PORT_FEAT_C_SUSPEND:
	status = PORT_PLC;
	port_change_bit = "suspend/resume";
	break;
	case USB_PORT_FEAT_C_PORT_LINK_STATE:
	status = PORT_PLC;
	port_change_bit = "link state";
	break;
	case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
	status = PORT_CEC;
	port_change_bit = "config error";
	break;
	default:
	/* Should never happen */
	return;
	}
	/* Change bits are all write 1 to clear */
	writel(port_status \| status, addr);
	port_status = readl(addr);
	xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
	port_change_bit, wIndex, port_status);
	}

	static int xhci_get_ports(struct usb_hcd hcd, __le32 __iomem **port_array)
	{
	int max_ports;
	struct xhci_hcd *xhci = hcd_to_xhci(hcd);

	if (hcd->speed >= HCD_USB3) {
	max_ports = xhci->num_usb3_ports;
	*port_array = xhci->usb3_ports;
	} else {
	max_ports = xhci->num_usb2_ports;
	*port_array = xhci->usb2_ports;
	}

	return max_ports;
	}

	static __le32 __iomem xhci_get_port_io_addr(struct usb_hcd hcd, int index)
	{
	__le32 __iomem **port_array;

	xhci_get_ports(hcd, &port_array);
	return port_array[index];
	}

	/*
	* xhci_set_port_power() must be called with xhci->lock held.
	* It will release and re-aquire the lock while calling ACPI
	* method.
	*/
	static void xhci_set_port_power(struct xhci_hcd xhci, struct usb_hcd hcd,
	u16 index, bool on, unsigned long *flags)
	{
	__le32 __iomem *addr;
	u32 temp;

	addr = xhci_get_port_io_addr(hcd, index);
	temp = readl(addr);
	temp = xhci_port_state_to_neutral(temp);
	if (on) {
	/* Power on */
	writel(temp \| PORT_POWER, addr);
	temp = readl(addr);
	xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n",
	index, temp);
	} else {
	/* Power off */
	writel(temp & ~PORT_POWER, addr);
	}

	spin_unlock_irqrestore(&xhci->lock, *flags);
	temp = usb_acpi_power_manageable(hcd->self.root_hub,
	index);
	if (temp)
	usb_acpi_set_power_state(hcd->self.root_hub,
	index, on);
	spin_lock_irqsave(&xhci->lock, *flags);
	}

	static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
	u16 test_mode, u16 wIndex)
	{
	u32 temp;
	__le32 __iomem *addr;

	/* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
	addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
	temp = readl(addr + PORTPMSC);
	temp \|= test_mode << PORT_TEST_MODE_SHIFT;
	writel(temp, addr + PORTPMSC);
	xhci->test_mode = test_mode;
	if (test_mode == TEST_FORCE_EN)
	xhci_start(xhci);
	}

	static int xhci_enter_test_mode(struct xhci_hcd *xhci,
	u16 test_mode, u16 wIndex, unsigned long *flags)
	{
	int i, retval;

	/* Disable all Device Slots */
	xhci_dbg(xhci, "Disable all slots\n");
	spin_unlock_irqrestore(&xhci->lock, *flags);
	for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
	retval = xhci_disable_slot(xhci, NULL, i);
	if (retval)
	xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
	i, retval);
	}
	spin_lock_irqsave(&xhci->lock, *flags);
	/* Put all ports to the Disable state by clear PP */
	xhci_dbg(xhci, "Disable all port (PP = 0)\n");
	/* Power off USB3 ports*/
	for (i = 0; i < xhci->num_usb3_ports; i++)
	xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
	/* Power off USB2 ports*/
	for (i = 0; i < xhci->num_usb2_ports; i++)
	xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
	/* Stop the controller */
	xhci_dbg(xhci, "Stop controller\n");
	retval = xhci_halt(xhci);
	if (retval)
	return retval;
	/* Disable runtime PM for test mode */
	pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
	/* Set PORTPMSC.PTC field to enter selected test mode */
	/* Port is selected by wIndex. port_id = wIndex + 1 */
	xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
	test_mode, wIndex + 1);
	xhci_port_set_test_mode(xhci, test_mode, wIndex);
	return retval;
	}

	static int xhci_exit_test_mode(struct xhci_hcd *xhci)
	{
	int retval;

	if (!xhci->test_mode) {
	xhci_err(xhci, "Not in test mode, do nothing.\n");
	return 0;
	}
	if (xhci->test_mode == TEST_FORCE_EN &&
	!(xhci->xhc_state & XHCI_STATE_HALTED)) {
	retval = xhci_halt(xhci);
	if (retval)
	return retval;
	}
	pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
	xhci->test_mode = 0;
	return xhci_reset(xhci);
	}

	void xhci_set_link_state(struct xhci_hcd xhci, __le32 __iomem *port_array,
	int port_id, u32 link_state)
	{
	u32 temp;

	temp = readl(port_array[port_id]);
	temp = xhci_port_state_to_neutral(temp);
	temp &= ~PORT_PLS_MASK;
	temp \|= PORT_LINK_STROBE \| link_state;
	writel(temp, port_array[port_id]);
	}

	static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
	__le32 __iomem **port_array, int port_id, u16 wake_mask)