)]}'
{
  "commit": "ae6dc7deac2a8639595437af3df5fade878a1601",
  "tree": "db45ffb492b43e4598bbe417b6e1023ae1131cae",
  "parents": [
    "a1d5f18cafe6b81696e60ca4901709d2f807362c"
  ],
  "author": {
    "name": "Gabriele Paoloni",
    "email": "gabriele.paoloni@huawei.com",
    "time": "Tue May 23 15:23:59 2017 +0100"
  },
  "committer": {
    "name": "Bjorn Helgaas",
    "email": "bhelgaas@google.com",
    "time": "Fri Jun 16 19:19:28 2017 -0500"
  },
  "message": "PCI/portdrv: Allocate MSI/MSI-X vector for Downstream Port Containment\n\nCurrently pcie_port_enable_irq_vec() only allocates MSI/MSI-X vectors for\nPME, hotplug, and AER.\n\nThe Downstream Port Containment feature also supports MSI/MSI-X interrupts,\nso allocate a vector for it, too.\n\nSigned-off-by: Liudongdong \u003cliudongdong3@huawei.com\u003e\nSigned-off-by: Gabriele Paoloni \u003cgabriele.paoloni@huawei.com\u003e\n[bhelgaas: changelog, comment]\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nReviewed-by: Christoph Hellwig \u003chch@lst.de\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e00b5da07fef171bb61a7aa937ce0d23f613459d",
      "old_mode": 33188,
      "old_path": "drivers/pci/pcie/portdrv_core.c",
      "new_id": "313a21df1692fa62f2330e55121aa0788e48ce29",
      "new_mode": 33188,
      "new_path": "drivers/pci/pcie/portdrv_core.c"
    }
  ]
}