| commit | b0f0daa8fe9e74b85f6360288d38224ad1c2f2f4 | [log] [tgz] |
|---|---|---|
| author | Priit Laes <plaes@plaes.org> | Thu Mar 02 22:55:27 2017 +0200 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Mon Mar 06 10:25:56 2017 +0100 |
| tree | 1f0b619bb03802fdfd07dd854b3c11f6973e5b81 | |
| parent | 05c04bef445d695917fe74422e05352b1b46f3c8 [diff] |
clk: sunxi-ng: sun5i: Fix mux width for csi clock Mux for CSI clock is 3 bits, not 2. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>