)]}'
{
  "commit": "b12d44db4b0187f536c487713ef39a22da990635",
  "tree": "8cc3c51f4d367633fe1a3fc80d8630e5f961d73f",
  "parents": [
    "edc609fd19e1cd1b6d0125915195a28c107a293b"
  ],
  "author": {
    "name": "Ritesh Harjani",
    "email": "riteshh@codeaurora.org",
    "time": "Mon Nov 21 12:07:21 2016 +0530"
  },
  "committer": {
    "name": "Ulf Hansson",
    "email": "ulf.hansson@linaro.org",
    "time": "Tue Nov 29 09:05:17 2016 +0100"
  },
  "message": "mmc: sdhci-msm: Add clock changes for DDR mode.\n\nSDHC MSM controller need 2x clock for MCLK at GCC.\nHence make required changes to have 2x clock for\nDDR timing modes.\n\nSigned-off-by: Ritesh Harjani \u003criteshh@codeaurora.org\u003e\nAcked-by: Adrian Hunter \u003cadrian.hunter@intel.com\u003e\nSigned-off-by: Ulf Hansson \u003culf.hansson@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "00759efed312d2140e5d067a15d62822456557b0",
      "old_mode": 33188,
      "old_path": "drivers/mmc/host/sdhci-msm.c",
      "new_id": "c50cee87e6c0120301a8d15f54a5fd15a0e17549",
      "new_mode": 33188,
      "new_path": "drivers/mmc/host/sdhci-msm.c"
    }
  ]
}