| commit | 659db6f6beacae6fe49b5566debc4e82f678ff63 | [log] [tgz] |
|---|---|---|
| author | Andreas Herrmann <andreas.herrmann@calxeda.com> | Tue Oct 01 13:39:09 2013 +0100 |
| committer | Will Deacon <will.deacon@arm.com> | Wed Oct 09 14:14:41 2013 +0100 |
| tree | 76f38b1f4dc8da72d9f289fa28f46404f13e52e1 | |
| parent | 2ef0f03120ea2ad64d0e70f032a58e6c13603cdc [diff] |
iommu/arm-smmu: Clear global and context bank fault status registers After reset these registers have unknown values. This might cause problems when evaluating SMMU_GFSR and/or SMMU_CB_FSR in handlers for combined interrupts. Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com> Signed-off-by: Will Deacon <will.deacon@arm.com>