tree 15f22dc1162f04a8a6d48360d7b70d3755639e4a
parent 2bbbd96357ce76cc45ec722c00f654aa7b189112
author Yan Markman <ymarkman@marvell.com> 1476566552 +0300
committer Gregory CLEMENT <gregory.clement@free-electrons.com> 1509032486 +0200

ARM: dts: mvebu: pl310-cache disable double-linefill

Under heavy system stress mvebu SoC using Cortex A9 sporadically
encountered instability issues.

The "double linefill" feature of L2 cache was identified as causing
dependency between read and write which lead to the deadlock.

Especially, it was the cause of deadlock seen under heavy PCIe traffic,
as this dependency violates PCIE overtaking rule.

Fixes: c8f5a878e554 ("ARM: mvebu: use DT properties to fine-tune the L2 configuration")
Cc: stable@vger.kernel.org
Signed-off-by: Yan Markman <ymarkman@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
[gregory.clement@free-electrons.com: reformulate commit log, add Armada
375 and add Fixes tag]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>