commit d9493234e20e8153495fa118b60bdff22fdfc6c8
author Axel Lin <axel.lin@ingics.com> Tue Jul 30 10:46:28 2013 +0800
committer Mark Brown <broonie@linaro.org> Tue Jul 30 11:20:00 2013 +0100
tree c4e93d3ee4d3eb110b7ef0b81046cf2026acc301
parent 2e04cc41a6d7a561568f3802b61d0987f1ec7e9a

regulator: pfuze100: Fix n_voltages setting for SW2~SW4 with high bit set

Current code adjust min_uV and uV_step but missed adjusting the n_voltages
setting.

When BIT6 is clear:
        n_voltages = (1975000 - 400000) / 25000 + 1 = 64
When BIT6 is set:
        n_voltages = (3300000 - 800000) / 50000 + 1 = 51

The n_voltages needs update because when BIT6 is set 0x73 ~ 0x7f are reserved.
When using regulator_list_voltage_linear, the n_voltages does matter here
because wrong n_voltages setting make the equation return wrong result.
e.g. if selector is 63, regulator_list_voltage_linear returns
     800000 + (50000 * 63) = 4000000
     It should return -EINVAL if the selector is in the range of 51 ~ 63.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@linaro.org>