/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __reg_map_asm_h
#define __reg_map_asm_h

/*
 * This file is autogenerated from
 *   file:            reg.rmap
 * 
 *   by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
#define regi_ccd                                  0xb0000000
#define regi_ccd_top                              0xb0000000
#define regi_ccd_dp                               0xb0000400
#define regi_ccd_stat                             0xb0000800
#define regi_ccd_tg                               0xb0001000
#define regi_cfg                                  0xb0002000
#define regi_clkgen                               0xb0004000
#define regi_ddr2_ctrl                            0xb0006000
#define regi_dma0                                 0xb0008000
#define regi_dma1                                 0xb000a000
#define regi_dma11                                0xb000c000
#define regi_dma2                                 0xb000e000
#define regi_dma3                                 0xb0010000
#define regi_dma4                                 0xb0012000
#define regi_dma5                                 0xb0014000
#define regi_dma6                                 0xb0016000
#define regi_dma7                                 0xb0018000
#define regi_dma9                                 0xb001a000
#define regi_eth                                  0xb001c000
#define regi_gio                                  0xb0020000
#define regi_h264                                 0xb0022000
#define regi_hist                                 0xb0026000
#define regi_iop                                  0xb0028000
#define regi_iop_version                          0xb0028000
#define regi_iop_fifo_in_extra                    0xb0028040
#define regi_iop_fifo_out_extra                   0xb0028080
#define regi_iop_trigger_grp0                     0xb00280c0
#define regi_iop_trigger_grp1                     0xb0028100
#define regi_iop_trigger_grp2                     0xb0028140
#define regi_iop_trigger_grp3                     0xb0028180
#define regi_iop_trigger_grp4                     0xb00281c0
#define regi_iop_trigger_grp5                     0xb0028200
#define regi_iop_trigger_grp6                     0xb0028240
#define regi_iop_trigger_grp7                     0xb0028280
#define regi_iop_crc_par                          0xb0028300
#define regi_iop_dmc_in                           0xb0028380
#define regi_iop_dmc_out                          0xb0028400
#define regi_iop_fifo_in                          0xb0028480
#define regi_iop_fifo_out                         0xb0028500
#define regi_iop_scrc_in                          0xb0028580
#define regi_iop_scrc_out                         0xb0028600
#define regi_iop_timer_grp0                       0xb0028680
#define regi_iop_timer_grp1                       0xb0028700
#define regi_iop_sap_in                           0xb0028800
#define regi_iop_sap_out                          0xb0028900
#define regi_iop_spu                              0xb0028a00
#define regi_iop_sw_cfg                           0xb0028b00
#define regi_iop_sw_cpu                           0xb0028c00
#define regi_iop_sw_mpu                           0xb0028d00
#define regi_iop_sw_spu                           0xb0028e00
#define regi_iop_mpu                              0xb0029000
#define regi_irq                                  0xb002a000
#define regi_jpeg                                 0xb002c000
#define regi_l2cache                              0xb0030000
#define regi_marb_bar                             0xb0032000
#define regi_marb_bar_bp0                         0xb0032140
#define regi_marb_bar_bp1                         0xb0032180
#define regi_marb_bar_bp2                         0xb00321c0
#define regi_marb_bar_bp3                         0xb0032200
#define regi_marb_foo                             0xb0034000
#define regi_marb_foo_bp0                         0xb0034280
#define regi_marb_foo_bp1                         0xb00342c0
#define regi_marb_foo_bp2                         0xb0034300
#define regi_marb_foo_bp3                         0xb0034340
#define regi_pinmux                               0xb0038000
#define regi_pio                                  0xb0036000
#define regi_sclr                                 0xb003a000
#define regi_sclr_fifo                            0xb003c000
#define regi_ser0                                 0xb003e000
#define regi_ser1                                 0xb0040000
#define regi_ser2                                 0xb0042000
#define regi_ser3                                 0xb0044000
#define regi_ser4                                 0xb0046000
#define regi_sser                                 0xb0048000
#define regi_strcop                               0xb004a000
#define regi_strdma0                              0xb004e000
#define regi_strdma1                              0xb0050000
#define regi_strdma2                              0xb0052000
#define regi_strdma3                              0xb0054000
#define regi_strdma5                              0xb0056000
#define regi_strmux                               0xb004c000
#define regi_timer0                               0xb0058000
#define regi_timer1                               0xb005a000
#define regi_trace                                0xb005c000
#define regi_vin                                  0xb005e000
#define regi_vout                                 0xb0060000
#endif /* __reg_map_asm_h */