[
    {
        "EventCode": "0x24",
        "UMask": "0x21",
        "BriefDescription": "Demand Data Read miss L2, no rejects",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
        "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x41",
        "BriefDescription": "Demand Data Read requests that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
        "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x30",
        "BriefDescription": "L2 prefetch requests that miss L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.L2_PF_MISS",
        "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x50",
        "BriefDescription": "L2 prefetch requests that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.L2_PF_HIT",
        "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0xe1",
        "BriefDescription": "Demand Data Read requests",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
        "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0xe2",
        "BriefDescription": "RFO requests to L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.ALL_RFO",
        "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0xe4",
        "BriefDescription": "L2 code requests",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.ALL_CODE_RD",
        "PublicDescription": "This event counts the total number of L2 code requests.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0xf8",
        "BriefDescription": "Requests from L2 hardware prefetchers",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.ALL_PF",
        "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x27",
        "UMask": "0x50",
        "BriefDescription": "Not rejected writebacks that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_DEMAND_RQSTS.WB_HIT",
        "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x2E",
        "UMask": "0x41",
        "BriefDescription": "Core-originated cacheable demand requests missed L3",
        "Counter": "0,1,2,3",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x2E",
        "UMask": "0x4f",
        "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
        "Counter": "0,1,2,3",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x48",
        "UMask": "0x1",
        "BriefDescription": "L1D miss oustandings duration in cycles",
        "Counter": "2",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "2"
    },
    {
        "EventCode": "0x48",
        "UMask": "0x1",
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "2",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "CounterMask": "1",
        "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "2"
    },
    {
        "EventCode": "0x51",
        "UMask": "0x1",
        "BriefDescription": "L1D data line replacements",
        "Counter": "0,1,2,3",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x1",
        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
        "Errata": "BDM76",
        "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x2",
        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
        "Errata": "BDM76",
        "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x4",
        "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
        "Errata": "BDM76",
        "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x8",
        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
        "Errata": "BDM76",
        "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x1",
        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
        "CounterMask": "1",
        "Errata": "BDM76",
        "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x8",
        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "CounterMask": "1",
        "Errata": "BDM76",
        "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x4",
        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
        "CounterMask": "1",
        "Errata": "BDM76",
        "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x63",
        "UMask": "0x2",
        "BriefDescription": "Cycles when L1D is locked",
        "Counter": "0,1,2,3",
        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
        "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB0",
        "UMask": "0x1",
        "BriefDescription": "Demand Data Read requests sent to uncore",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
        "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB0",
        "UMask": "0x2",
        "BriefDescription": "Cacheable and noncachaeble code read requests",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
        "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB0",
        "UMask": "0x4",
        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
        "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB0",
        "UMask": "0x8",
        "BriefDescription": "Demand and prefetch data reads",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
        "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable \"Demands\" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xb2",
        "UMask": "0x1",
        "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
        "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xD0",
        "UMask": "0x11",
        "BriefDescription": "Retired load uops that miss the STLB.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD0",
        "UMask": "0x12",
        "BriefDescription": "Retired store uops that miss the STLB.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
        "SampleAfterValue": "100003",
        "L1_Hit_Indication": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD0",
        "UMask": "0x21",
        "BriefDescription": "Retired load uops with locked access.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
        "Errata": "BDM35",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with locked access retired to the architected path.",
        "SampleAfterValue": "100007",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD0",
        "UMask": "0x41",
        "BriefDescription": "Retired load uops that split across a cacheline boundary.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD0",
        "UMask": "0x42",
        "BriefDescription": "Retired store uops that split across a cacheline boundary.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
        "SampleAfterValue": "100003",
        "L1_Hit_Indication": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD0",
        "UMask": "0x81",
        "BriefDescription": "All retired load uops.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
        "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD0",
        "UMask": "0x82",
        "BriefDescription": "All retired store uops.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
        "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
        "SampleAfterValue": "2000003",
        "L1_Hit_Indication": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD1",
        "UMask": "0x1",
        "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD1",
        "UMask": "0x2",
        "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
        "Errata": "BDM35",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD1",
        "UMask": "0x4",
        "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
        "Errata": "BDM100",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.",
        "SampleAfterValue": "50021",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD1",
        "UMask": "0x8",
        "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD1",
        "UMask": "0x10",
        "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.",
        "SampleAfterValue": "50021",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD1",
        "UMask": "0x20",
        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
        "Errata": "BDM100, BDE70",
        "SampleAfterValue": "100007",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD1",
        "UMask": "0x40",
        "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD2",
        "UMask": "0x1",
        "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
        "Errata": "BDM100",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.",
        "SampleAfterValue": "20011",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD2",
        "UMask": "0x2",
        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
        "Errata": "BDM100",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.",
        "SampleAfterValue": "20011",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD2",
        "UMask": "0x4",
        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
        "Errata": "BDM100",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).",
        "SampleAfterValue": "20011",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD2",
        "UMask": "0x8",
        "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
        "Errata": "BDM100",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xD3",
        "UMask": "0x1",
        "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
        "Data_LA": "1",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
        "Errata": "BDE70, BDM100",
        "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).",
        "SampleAfterValue": "100007",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xF0",
        "UMask": "0x1",
        "BriefDescription": "Demand Data Read requests that access L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_TRANS.DEMAND_DATA_RD",
        "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF0",
        "UMask": "0x2",
        "BriefDescription": "RFO requests that access L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_TRANS.RFO",
        "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF0",
        "UMask": "0x4",
        "BriefDescription": "L2 cache accesses when fetching instructions",
        "Counter": "0,1,2,3",
        "EventName": "L2_TRANS.CODE_RD",
        "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF0",
        "UMask": "0x8",
        "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_TRANS.ALL_PF",
        "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF0",
        "UMask": "0x10",
        "BriefDescription": "L1D writebacks that access L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_TRANS.L1D_WB",
        "PublicDescription": "This event counts L1D writebacks that access L2 cache.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF0",
        "UMask": "0x20",
        "BriefDescription": "L2 fill requests that access L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_TRANS.L2_FILL",
        "PublicDescription": "This event counts L2 fill requests that access L2 cache.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF0",
        "UMask": "0x40",
        "BriefDescription": "L2 writebacks that access L2 cache",
        "Counter": "0,1,2,3",
        "EventName": "L2_TRANS.L2_WB",
        "PublicDescription": "This event counts L2 writebacks that access L2 cache.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF0",
        "UMask": "0x80",
        "BriefDescription": "Transactions accessing L2 pipe",
        "Counter": "0,1,2,3",
        "EventName": "L2_TRANS.ALL_REQUESTS",
        "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF1",
        "UMask": "0x1",
        "BriefDescription": "L2 cache lines in I state filling L2",
        "Counter": "0,1,2,3",
        "EventName": "L2_LINES_IN.I",
        "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF1",
        "UMask": "0x2",
        "BriefDescription": "L2 cache lines in S state filling L2",
        "Counter": "0,1,2,3",
        "EventName": "L2_LINES_IN.S",
        "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF1",
        "UMask": "0x4",
        "BriefDescription": "L2 cache lines in E state filling L2",
        "Counter": "0,1,2,3",
        "EventName": "L2_LINES_IN.E",
        "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF1",
        "UMask": "0x7",
        "BriefDescription": "L2 cache lines filling L2",
        "Counter": "0,1,2,3",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF2",
        "UMask": "0x5",
        "BriefDescription": "Clean L2 cache lines evicted by demand.",
        "Counter": "0,1,2,3",
        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xf4",
        "UMask": "0x10",
        "BriefDescription": "Split locks in SQ",
        "Counter": "0,1,2,3",
        "EventName": "SQ_MISC.SPLIT_LOCK",
        "PublicDescription": "This event counts the number of split locks in the super queue.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x42",
        "BriefDescription": "RFO requests that hit L2 cache.",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.RFO_HIT",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x22",
        "BriefDescription": "RFO requests that miss L2 cache.",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.RFO_MISS",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x44",
        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.CODE_RD_HIT",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x24",
        "BriefDescription": "L2 cache misses when fetching instructions.",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.CODE_RD_MISS",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x27",
        "BriefDescription": "Demand requests that miss L2 cache.",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0xe7",
        "BriefDescription": "Demand requests to L2 cache.",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0x3f",
        "BriefDescription": "All requests that miss L2 cache.",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.MISS",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x24",
        "UMask": "0xff",
        "BriefDescription": "All L2 requests.",
        "Counter": "0,1,2,3",
        "EventName": "L2_RQSTS.REFERENCES",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x1",
        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
        "CounterMask": "6",
        "Errata": "BDM76",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x48",
        "UMask": "0x1",
        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
        "Counter": "2",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
        "AnyThread": "1",
        "CounterMask": "1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "2"
    },
    {
        "EventCode": "0x48",
        "UMask": "0x2",
        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
        "Counter": "0,1,2,3",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "CounterMask": "1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    }
]