)]}'
{
  "commit": "fc57ac2c9ca8109ea97fcc594f4be436944230cc",
  "tree": "a5147edd2bd218899d250860b5a3df199e3967a4",
  "parents": [
    "1f854112553a1d65363ab27d4ee3dfb4b27075fb"
  ],
  "author": {
    "name": "Paolo Bonzini",
    "email": "pbonzini@redhat.com",
    "time": "Wed May 14 17:40:58 2014 +0200"
  },
  "committer": {
    "name": "Paolo Bonzini",
    "email": "pbonzini@redhat.com",
    "time": "Tue May 27 10:21:09 2014 +0200"
  },
  "message": "KVM: lapic: sync highest ISR to hardware apic on EOI\n\nWhen Hyper-V enlightenments are in effect, Windows prefers to issue an\nHyper-V MSR write to issue an EOI rather than an x2apic MSR write.\nThe Hyper-V MSR write is not handled by the processor, and besides\nbeing slower, this also causes bugs with APIC virtualization.  The\nreason is that on EOI the processor will modify the highest in-service\ninterrupt (SVI) field of the VMCS, as explained in section 29.1.4 of\nthe SDM; every other step in EOI virtualization is already done by\napic_send_eoi or on VM entry, but this one is missing.\n\nWe need to do the same, and be careful not to muck with the isr_count\nand highest_isr_cache fields that are unused when virtual interrupt\ndelivery is enabled.\n\nCc: stable@vger.kernel.org\nReviewed-by: Yang Zhang \u003cyang.z.zhang@intel.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9736529ade08d727cbaa7db12a330ce86e5ea9c6",
      "old_mode": 33188,
      "old_path": "arch/x86/kvm/lapic.c",
      "new_id": "0069118581742d39da8d8aaada6f9f1cb2a14173",
      "new_mode": 33188,
      "new_path": "arch/x86/kvm/lapic.c"
    }
  ]
}