resources: Update boot-tests gem5 configs for gem5-20.1
Change-Id: Ib106bc08ccb081cd21e648e1716ffbd13f014d44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/34535
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
diff --git a/src/boot-exit/configs/system/MESI_Two_Level.py b/src/boot-exit/configs/system/MESI_Two_Level.py
index ef9ec64..4feef12 100755
--- a/src/boot-exit/configs/system/MESI_Two_Level.py
+++ b/src/boot-exit/configs/system/MESI_Two_Level.py
@@ -86,9 +86,9 @@
icache = self.controllers[i].L1Icache,
dcache = self.controllers[i].L1Dcache,
clk_domain = self.controllers[i].clk_domain,
- pio_master_port = iobus.slave,
- mem_master_port = iobus.slave,
- pio_slave_port = iobus.master
+ pio_request_port = iobus.cpu_side_ports,
+ mem_request_port = iobus.cpu_side_ports,
+ pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
slave = port)
@@ -113,22 +113,21 @@
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.slave
- self.sys_port_proxy.pio_master_port = iobus.slave
+ system.system_port = self.sys_port_proxy.in_ports
+ self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
+ cpu.icache_port = self.sequencers[i].in_ports
+ cpu.dcache_port = self.sequencers[i].in_ports
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+ cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
+ cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].slave
- cpu.dtb.walker.port = self.sequencers[i].slave
-
+ cpu.itb.walker.port = self.sequencers[i].in_ports
+ cpu.dtb.walker.port = self.sequencers[i].in_ports
class L1Cache(L1Cache_Controller):
@@ -193,18 +192,18 @@
"""
self.mandatoryQueue = MessageBuffer()
self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.master = ruby_system.network.slave
+ self.requestFromL1Cache.out_port = ruby_system.network.in_port
self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.master = ruby_system.network.slave
+ self.responseFromL1Cache.out_port = ruby_system.network.in_port
self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.master = ruby_system.network.slave
+ self.unblockFromL1Cache.out_port = ruby_system.network.in_port
self.optionalQueue = MessageBuffer()
self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.slave = ruby_system.network.master
+ self.requestToL1Cache.in_port = ruby_system.network.out_port
self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.slave = ruby_system.network.master
+ self.responseToL1Cache.in_port = ruby_system.network.out_port
class L2Cache(L2Cache_Controller):
@@ -239,17 +238,17 @@
"""Connect all of the queues for this controller.
"""
self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.master = ruby_system.network.slave
+ self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.master = ruby_system.network.slave
+ self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.master = ruby_system.network.slave
+ self.responseFromL2Cache.out_port = ruby_system.network.in_port
self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.slave = ruby_system.network.master
+ self.unblockToL2Cache.in_port = ruby_system.network.out_port
self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.slave = ruby_system.network.master
+ self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.slave = ruby_system.network.master
+ self.responseToL2Cache.in_port = ruby_system.network.out_port
class DirController(Directory_Controller):
@@ -271,16 +270,16 @@
self.ruby_system = ruby_system
self.directory = RubyDirectoryMemory()
# Connect this directory to the memory side.
- self.memory = mem_ctrls[0].port
+ self.memory_out_port = mem_ctrls[0].port
self.connectQueues(ruby_system)
def connectQueues(self, ruby_system):
self.requestToDir = MessageBuffer()
- self.requestToDir.slave = ruby_system.network.master
+ self.requestToDir.in_port = ruby_system.network.out_port
self.responseToDir = MessageBuffer()
- self.responseToDir.slave = ruby_system.network.master
+ self.responseToDir.in_port = ruby_system.network.out_port
self.responseFromDir = MessageBuffer()
- self.responseFromDir.master = ruby_system.network.slave
+ self.responseFromDir.out_port = ruby_system.network.in_port
self.requestToMemory = MessageBuffer()
self.responseFromMemory = MessageBuffer()
@@ -301,9 +300,9 @@
def connectQueues(self, ruby_system):
self.mandatoryQueue = MessageBuffer()
self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.slave = ruby_system.network.master
+ self.responseFromDir.in_port = ruby_system.network.out_port
self.requestToDir = MessageBuffer()
- self.requestToDir.master = ruby_system.network.slave
+ self.requestToDir.out_port = ruby_system.network.in_port
class MyNetwork(SimpleNetwork):
diff --git a/src/boot-exit/configs/system/MI_example_caches.py b/src/boot-exit/configs/system/MI_example_caches.py
index 2a7e975..8aa08ea 100755
--- a/src/boot-exit/configs/system/MI_example_caches.py
+++ b/src/boot-exit/configs/system/MI_example_caches.py
@@ -87,9 +87,9 @@
icache = self.controllers[i].cacheMemory,
dcache = self.controllers[i].cacheMemory,
clk_domain = self.controllers[i].clk_domain,
- pio_master_port = iobus.slave,
- mem_master_port = iobus.slave,
- pio_slave_port = iobus.master
+ pio_request_port = iobus.cpu_side_ports,
+ mem_request_port = iobus.cpu_side_ports,
+ pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
slave = port)
@@ -113,21 +113,21 @@
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.slave
- self.sys_port_proxy.pio_master_port = iobus.slave
+ system.system_port = self.sys_port_proxy.in_ports
+ self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
+ cpu.icache_port = self.sequencers[i].in_ports
+ cpu.dcache_port = self.sequencers[i].in_ports
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+ cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
+ cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].slave
- cpu.dtb.walker.port = self.sequencers[i].slave
+ cpu.itb.walker.port = self.sequencers[i].in_ports
+ cpu.dtb.walker.port = self.sequencers[i].in_ports
class L1Cache(L1Cache_Controller):
@@ -177,13 +177,13 @@
"""
self.mandatoryQueue = MessageBuffer()
self.requestFromCache = MessageBuffer(ordered = True)
- self.requestFromCache.master = ruby_system.network.slave
+ self.requestFromCache.out_port = ruby_system.network.in_port
self.responseFromCache = MessageBuffer(ordered = True)
- self.responseFromCache.master = ruby_system.network.slave
+ self.responseFromCache.out_port = ruby_system.network.in_port
self.forwardToCache = MessageBuffer(ordered = True)
- self.forwardToCache.slave = ruby_system.network.master
+ self.forwardToCache.in_port = ruby_system.network.out_port
self.responseToCache = MessageBuffer(ordered = True)
- self.responseToCache.slave = ruby_system.network.master
+ self.responseToCache.in_port = ruby_system.network.out_port
class DirController(Directory_Controller):
@@ -204,21 +204,21 @@
self.ruby_system = ruby_system
self.directory = RubyDirectoryMemory()
# Connect this directory to the memory side.
- self.memory = mem_ctrls[0].port
+ self.memory_out_port = mem_ctrls[0].port
self.connectQueues(ruby_system)
def connectQueues(self, ruby_system):
self.requestToDir = MessageBuffer(ordered = True)
- self.requestToDir.slave = ruby_system.network.master
+ self.requestToDir.in_port = ruby_system.network.out_port
self.dmaRequestToDir = MessageBuffer(ordered = True)
- self.dmaRequestToDir.slave = ruby_system.network.master
+ self.dmaRequestToDir.in_port = ruby_system.network.out_port
self.responseFromDir = MessageBuffer()
- self.responseFromDir.master = ruby_system.network.slave
+ self.responseFromDir.out_port = ruby_system.network.in_port
self.dmaResponseFromDir = MessageBuffer(ordered = True)
- self.dmaResponseFromDir.master = ruby_system.network.slave
+ self.dmaResponseFromDir.out_port = ruby_system.network.in_port
self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.master = ruby_system.network.slave
+ self.forwardFromDir.out_port = ruby_system.network.in_port
self.requestToMemory = MessageBuffer()
self.responseFromMemory = MessageBuffer()
@@ -239,9 +239,9 @@
def connectQueues(self, ruby_system):
self.mandatoryQueue = MessageBuffer()
self.requestToDir = MessageBuffer()
- self.requestToDir.master = ruby_system.network.slave
+ self.requestToDir.out_port = ruby_system.network.in_port
self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.slave = ruby_system.network.master
+ self.responseFromDir.in_port = ruby_system.network.out_port
class MyNetwork(SimpleNetwork):
diff --git a/src/boot-exit/configs/system/MOESI_CMP_directory.py b/src/boot-exit/configs/system/MOESI_CMP_directory.py
index 1af5cca..5aa49ba 100755
--- a/src/boot-exit/configs/system/MOESI_CMP_directory.py
+++ b/src/boot-exit/configs/system/MOESI_CMP_directory.py
@@ -87,9 +87,9 @@
icache = self.controllers[i].L1Icache,
dcache = self.controllers[i].L1Dcache,
clk_domain = self.controllers[i].clk_domain,
- pio_master_port = iobus.slave,
- mem_master_port = iobus.slave,
- pio_slave_port = iobus.master
+ pio_request_port = iobus.cpu_side_ports,
+ mem_request_port = iobus.cpu_side_ports,
+ pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
slave = port)
@@ -114,21 +114,21 @@
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.slave
- self.sys_port_proxy.pio_master_port = iobus.slave
+ system.system_port = self.sys_port_proxy.in_ports
+ self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
+ cpu.icache_port = self.sequencers[i].in_ports
+ cpu.dcache_port = self.sequencers[i].in_ports
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+ cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
+ cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].slave
- cpu.dtb.walker.port = self.sequencers[i].slave
+ cpu.itb.walker.port = self.sequencers[i].in_ports
+ cpu.dtb.walker.port = self.sequencers[i].in_ports
class L1Cache(L1Cache_Controller):
@@ -196,13 +196,13 @@
"""
self.mandatoryQueue = MessageBuffer()
self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.master = ruby_system.network.slave
+ self.requestFromL1Cache.out_port = ruby_system.network.in_port
self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.master = ruby_system.network.slave
+ self.responseFromL1Cache.out_port = ruby_system.network.in_port
self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.slave = ruby_system.network.master
+ self.requestToL1Cache.in_port = ruby_system.network.out_port
self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.slave = ruby_system.network.master
+ self.responseToL1Cache.in_port = ruby_system.network.out_port
self.triggerQueue = MessageBuffer(ordered = True)
class L2Cache(L2Cache_Controller):
@@ -240,18 +240,18 @@
"""Connect all of the queues for this controller.
"""
self.GlobalRequestFromL2Cache = MessageBuffer()
- self.GlobalRequestFromL2Cache.master = ruby_system.network.slave
+ self.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.master = ruby_system.network.slave
+ self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.master = ruby_system.network.slave
+ self.responseFromL2Cache.out_port = ruby_system.network.in_port
self.GlobalRequestToL2Cache = MessageBuffer()
- self.GlobalRequestToL2Cache.slave = ruby_system.network.master
+ self.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.slave = ruby_system.network.master
+ self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.slave = ruby_system.network.master
+ self.responseToL2Cache.in_port = ruby_system.network.out_port
self.triggerQueue = MessageBuffer(ordered = True)
@@ -275,18 +275,18 @@
self.ruby_system = ruby_system
self.directory = RubyDirectoryMemory()
# Connect this directory to the memory side.
- self.memory = mem_ctrls[0].port
+ self.memory_out_port = mem_ctrls[0].port
self.connectQueues(ruby_system)
def connectQueues(self, ruby_system):
self.requestToDir = MessageBuffer()
- self.requestToDir.slave = ruby_system.network.master
+ self.requestToDir.in_port = ruby_system.network.out_port
self.responseToDir = MessageBuffer()
- self.responseToDir.slave = ruby_system.network.master
+ self.responseToDir.in_port = ruby_system.network.out_port
self.responseFromDir = MessageBuffer()
- self.responseFromDir.master = ruby_system.network.slave
+ self.responseFromDir.out_port = ruby_system.network.in_port
self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.master = ruby_system.network.slave
+ self.forwardFromDir.out_port = ruby_system.network.in_port
self.requestToMemory = MessageBuffer()
self.responseFromMemory = MessageBuffer()
@@ -307,11 +307,11 @@
def connectQueues(self, ruby_system):
self.mandatoryQueue = MessageBuffer()
self.responseFromDir = MessageBuffer()
- self.responseFromDir.slave = ruby_system.network.master
+ self.responseFromDir.in_port = ruby_system.network.out_port
self.reqToDir = MessageBuffer()
- self.reqToDir.master = ruby_system.network.slave
+ self.reqToDir.out_port = ruby_system.network.in_port
self.respToDir = MessageBuffer()
- self.respToDir.master = ruby_system.network.slave
+ self.respToDir.out_port = ruby_system.network.in_port
self.triggerQueue = MessageBuffer(ordered = True)
diff --git a/src/boot-exit/configs/system/caches.py b/src/boot-exit/configs/system/caches.py
index abc0b31..813c6b5 100755
--- a/src/boot-exit/configs/system/caches.py
+++ b/src/boot-exit/configs/system/caches.py
@@ -64,7 +64,7 @@
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
@@ -116,13 +116,13 @@
Note: This creates a new crossbar
"""
self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.master
+ self.cpu_side = self.mmubus.mem_side_ports
for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.slave = tlb.walker.port
+ self.mmubus.cpu_side_ports = tlb.walker.port
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
class L2Cache(PrefetchCache):
"""Simple L2 Cache with default values"""
@@ -141,7 +141,7 @@
super(L2Cache, self).__init__()
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
diff --git a/src/boot-exit/configs/system/fs_tools.py b/src/boot-exit/configs/system/fs_tools.py
index 22a43d2..5e5e2df 100755
--- a/src/boot-exit/configs/system/fs_tools.py
+++ b/src/boot-exit/configs/system/fs_tools.py
@@ -33,7 +33,7 @@
def __init__(self, filename):
super(CowDisk, self).__init__()
- self.driveID = 'master'
+ self.driveID = 'device0'
self.image = CowDiskImage(child=RawDiskImage(read_only=True),
read_only=False)
self.image.child.image_file = filename
diff --git a/src/boot-exit/configs/system/ruby_system.py b/src/boot-exit/configs/system/ruby_system.py
index 778743a..e7c1135 100755
--- a/src/boot-exit/configs/system/ruby_system.py
+++ b/src/boot-exit/configs/system/ruby_system.py
@@ -80,7 +80,7 @@
from .MOESI_CMP_directory import MOESICMPDirCache
self.caches = MOESICMPDirCache()
self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma, self.iobus.master],
+ [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports],
self.iobus)
if self._host_parallel:
@@ -133,7 +133,7 @@
def _createMemoryControllers(self, num, cls):
self.mem_cntrls = [
- cls(range = self.mem_ranges[0])
+ MemCtrl(dram = cls(range = self.mem_ranges[0]))
for i in range(num)
]
diff --git a/src/boot-exit/configs/system/system.py b/src/boot-exit/configs/system/system.py
index 58e37b8..95d0147 100755
--- a/src/boot-exit/configs/system/system.py
+++ b/src/boot-exit/configs/system/system.py
@@ -56,7 +56,7 @@
self.membus.default = Self.badaddr_responder.pio
# Set up the system port for functional access from the simulator
- self.system_port = self.membus.slave
+ self.system_port = self.membus.cpu_side_ports
self.initFS(self.membus, num_cpus)
@@ -163,9 +163,9 @@
# For x86 only, connect interrupts to the memory
# Note: these are directly connected to the memory bus and
# not cached
- cpu.interrupts[0].pio = self.membus.master
- cpu.interrupts[0].int_master = self.membus.slave
- cpu.interrupts[0].int_slave = self.membus.master
+ cpu.interrupts[0].pio = self.membus.mem_side_ports
+ cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
+ cpu.interrupts[0].int_responder = self.membus.mem_side_ports
def createMemoryControllersDDR3(self):
@@ -173,8 +173,8 @@
def _createMemoryControllers(self, num, cls):
self.mem_cntrls = [
- cls(range = self.mem_ranges[0],
- port = self.membus.master)
+ MemCtrl(dram = cls(range = self.mem_ranges[0]),
+ port = self.membus.mem_side_ports)
for i in range(num)
]
@@ -192,8 +192,8 @@
# North Bridge
self.iobus = IOXBar()
self.bridge = Bridge(delay='50ns')
- self.bridge.master = self.iobus.slave
- self.bridge.slave = membus.master
+ self.bridge.mem_side_port = self.iobus.cpu_side_ports
+ self.bridge.cpu_side_port = membus.mem_side_ports
# Allow the bridge to pass through:
# 1) kernel configured PCI device memory map address: address range
# [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
@@ -213,8 +213,8 @@
# Create a bridge from the IO bus to the memory bus to allow access
# to the local APIC (two pages)
self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.slave = self.iobus.master
- self.apicbridge.master = membus.slave
+ self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
+ self.apicbridge.mem_side_port = membus.cpu_side_ports
self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
interrupts_address_space_base +
cpus * APIC_range_size
@@ -233,8 +233,8 @@
size = '1kB',
tgts_per_mshr = 12,
addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.master
- self.iocache.mem_side = self.membus.slave
+ self.iocache.cpu_side = self.iobus.mem_side_ports
+ self.iocache.mem_side = self.membus.cpu_side_ports
self.intrctrl = IntrControl()
