diff --git a/README.md b/README.md
index cace966..6179118 100644
--- a/README.md
+++ b/README.md
@@ -74,8 +74,8 @@
 ### RISCV Tests Origins
 
 The RISCV Tests in this repository were obtained from
-<https://github.com/riscv/riscv-tests.git>, revision
-19bfdab48c2a6da4a2c67d5779757da7b073811d.
+<https://github.com/riscv-software-src/riscv-tests.git>, revision
+e65ecdf941a5484af27f9be223fb655ebcb0398b.
 
 ### RISCV Tests Compilation
 
diff --git a/src/riscv-tests/README.md b/src/riscv-tests/README.md
index 570e4e4..d3ce2d1 100644
--- a/src/riscv-tests/README.md
+++ b/src/riscv-tests/README.md
@@ -55,7 +55,7 @@
 A test program for RISC-V is written within a single assembly language file,
 which is passed through the C preprocessor, and all regular assembly
 directives can be used. An example test program is shown below. Each test
-program should first include the `riscv test.h` header file, which defines the
+program should first include the `riscv_test.h` header file, which defines the
 macros used by the TVM. The header file will have different contents depending
 on the target environment for which the test will be built.  One of the goals
 of the various TVMs is to allow the same test program to be compiled and run
diff --git a/src/riscv-tests/benchmarks/Makefile b/src/riscv-tests/benchmarks/Makefile
index cc32714..c9469e2 100644
--- a/src/riscv-tests/benchmarks/Makefile
+++ b/src/riscv-tests/benchmarks/Makefile
@@ -37,7 +37,7 @@
 
 RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf-
 RISCV_GCC ?= $(RISCV_PREFIX)gcc
-RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf
+RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns
 RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
 RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld
 RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
diff --git a/src/riscv-tests/benchmarks/common/test.ld b/src/riscv-tests/benchmarks/common/test.ld
index 679c4ba..a50b017 100644
--- a/src/riscv-tests/benchmarks/common/test.ld
+++ b/src/riscv-tests/benchmarks/common/test.ld
@@ -28,6 +28,7 @@
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }
 
+  . = ALIGN(0x1000);
   .text : { *(.text) }
 
   /* data segment */
diff --git a/src/riscv-tests/benchmarks/pmp/pmp.c b/src/riscv-tests/benchmarks/pmp/pmp.c
index 2ccd769..ec07e4a 100644
--- a/src/riscv-tests/benchmarks/pmp/pmp.c
+++ b/src/riscv-tests/benchmarks/pmp/pmp.c
@@ -8,6 +8,7 @@
 #include "util.h"
 
 volatile int trap_expected;
+volatile int granule;
 
 #define INLINE inline __attribute__((always_inline))
 
@@ -55,8 +56,6 @@
   return va - SCRATCH + (uintptr_t)scratch;
 }
 
-#define GRANULE (1UL << PMP_SHIFT)
-
 typedef struct {
   uintptr_t cfg;
   uintptr_t a0;
@@ -85,14 +84,14 @@
     p.a1 = p.a0 + range;
   }
 
-  p.a0 *= GRANULE;
-  p.a1 *= GRANULE;
+  p.a0 *= granule;
+  p.a1 *= granule;
   addr = va2pa(addr);
 
   uintptr_t hits = 0;
-  for (uintptr_t i = 0; i < size; i += GRANULE) {
+  for (uintptr_t i = 0; i < size; i += granule) {
     if (p.a0 <= addr + i && addr + i < p.a1)
-      hits += GRANULE;
+      hits += granule;
   }
 
   return hits == 0 || hits >= size;
@@ -126,7 +125,7 @@
 
 INLINE void test_range_once(pmpcfg_t p, uintptr_t base, uintptr_t range)
 {
-  for (uintptr_t addr = base; addr < base + range; addr += GRANULE)
+  for (uintptr_t addr = base; addr < base + range; addr += granule)
     test_all_sizes(p, addr);
 }
 
@@ -153,7 +152,7 @@
 INLINE pmpcfg_t set_pmp_napot(uintptr_t base, uintptr_t range)
 {
   pmpcfg_t p;
-  p.cfg = PMP_R | (range > GRANULE ? PMP_NAPOT : PMP_NA4);
+  p.cfg = PMP_R | (range > granule ? PMP_NAPOT : PMP_NA4);
   p.a0 = 0;
   p.a1 = (base + (range/2 - 1)) >> PMP_SHIFT;
   return set_pmp(p);
@@ -172,18 +171,33 @@
 
 static void test_ranges(uintptr_t addr, uintptr_t size)
 {
-  for (uintptr_t range = GRANULE; range <= size; range += GRANULE)
+  for (uintptr_t range = granule; range <= size; range += granule)
     test_range(addr, range);
 }
 
 static void exhaustive_test(uintptr_t addr, uintptr_t size)
 {
-  for (uintptr_t base = addr; base < addr + size; base += GRANULE)
+  for (uintptr_t base = addr; base < addr + size; base += granule)
     test_ranges(base, size - (base - addr));
 }
 
+static void detect_granule()
+{
+  write_csr(pmpcfg0, NULL);
+  write_csr(pmpaddr0, 0xffffffffffffffffULL);
+  uintptr_t ret = read_csr(pmpaddr0);
+  int g = 2;
+  for(uintptr_t i = 1; i; i<<=1) {
+    if((ret & i) != 0) 
+      break;
+    g++;
+  }
+  granule = 1UL << g;
+}
+
 int main()
 {
+  detect_granule();
   init_pt();
 
   const int max_exhaustive = 32;
diff --git a/src/riscv-tests/debug/Makefile b/src/riscv-tests/debug/Makefile
index 3efdea8..06f7d9d 100644
--- a/src/riscv-tests/debug/Makefile
+++ b/src/riscv-tests/debug/Makefile
@@ -4,16 +4,19 @@
 src_dir ?= .
 GDBSERVER_PY = $(src_dir)/gdbserver.py
 TESTS = $(shell $(GDBSERVER_PY) --list-tests $(src_dir)/targets/RISC-V/spike32.py)
+MULTI_TESTS = $(shell $(GDBSERVER_PY) --list-tests $(src_dir)/targets/RISC-V/spike32.py | \
+	      grep -i multi)
 
 default: spike$(XLEN) spike$(XLEN)-2
 
-all-tests: spike32 spike32-2 spike32-2-rtos spike32-2-hwthread \
-	spike64 spike64-2 spike64-2-rtos spike64-2-hwthread
+all-tests: spike32 spike-multi-limited spike32-2 spike32-2-hwthread \
+	spike64 spike64-2 spike64-2-hwthread
+
+slow-tests:	spike-multi all-tests
 
 all:	pylint all-tests
 
 run.%:
-	echo $@
 	$(GDBSERVER_PY) \
 		$(src_dir)/targets/RISC-V/$(word 2, $(subst ., ,$@)).py \
 		$(word 3, $(subst ., ,$@)) \
@@ -23,11 +26,14 @@
 		--server_cmd $(RISCV)/bin/openocd
 
 # Target to check all the multicore options.
-multi-tests: spike32-2 spike64-2-rtos spike32-2-hwthread
+multi-tests: spike32-2 spike32-2-hwthread
 
 pylint:
 	pylint --rcfile=pylint.rc `git ls-files '*.py'`
 
+spike-multi-limited:	$(foreach test, $(MULTI_TESTS), run.spike-multi.$(test))
+	echo Finished $@
+
 spike%:	$(foreach test, $(TESTS), run.spike%.$(test))
 	echo Finished $@
 
diff --git a/src/riscv-tests/debug/README.md b/src/riscv-tests/debug/README.md
index 6133b6c..7dd6790 100644
--- a/src/riscv-tests/debug/README.md
+++ b/src/riscv-tests/debug/README.md
@@ -9,7 +9,8 @@
 Requirements
 ============
 The following should be in the user's path:
-* riscv64-unknown-elf-gcc
+* riscv64-unknown-elf-gcc (`rvv-0.9.x` branch for riscv-gnu-toolchain should
+  work if master does not have vector support yet)
 * riscv64-unknown-elf-gdb (can be overridden with `--gdb` when running
   gdbserver.py manually), which should be the latest from
   git://sourceware.org/git/binutils-gdb.git.
diff --git a/src/riscv-tests/debug/bin/README.md b/src/riscv-tests/debug/bin/README.md
new file mode 100644
index 0000000..7e81515
--- /dev/null
+++ b/src/riscv-tests/debug/bin/README.md
@@ -0,0 +1,7 @@
+This directory contains binaries that are not easy to compile.
+
+RTOSDemo32.axf and RTOSDemo64.axf are created by checking out
+https://github.com/FreeRTOS/FreeRTOS, following the instructions in
+`FreeRTOS/Demo/RISC-V-spike-htif_GCC/README.md`, and building:
+* `make XLEN=32 BASE_ADDRESS=0x10000000`
+* `make XLEN=64 BASE_ADDRESS=0x1212340000`
diff --git a/src/riscv-tests/debug/bin/RTOSDemo32.axf b/src/riscv-tests/debug/bin/RTOSDemo32.axf
new file mode 100644
index 0000000..5fa3fe7
--- /dev/null
+++ b/src/riscv-tests/debug/bin/RTOSDemo32.axf
Binary files differ
diff --git a/src/riscv-tests/debug/bin/RTOSDemo64.axf b/src/riscv-tests/debug/bin/RTOSDemo64.axf
new file mode 100644
index 0000000..bfa2a2a
--- /dev/null
+++ b/src/riscv-tests/debug/bin/RTOSDemo64.axf
Binary files differ
diff --git a/src/riscv-tests/debug/gdbserver.py b/src/riscv-tests/debug/gdbserver.py
index da671d3..3484906 100755
--- a/src/riscv-tests/debug/gdbserver.py
+++ b/src/riscv-tests/debug/gdbserver.py
@@ -8,13 +8,14 @@
 import tempfile
 import time
 import os
+import re
 
 import targets
 import testlib
 from testlib import assertEqual, assertNotEqual, assertIn, assertNotIn
 from testlib import assertGreater, assertRegex, assertLess
 from testlib import GdbTest, GdbSingleHartTest, TestFailed
-from testlib import assertTrue, TestNotApplicable
+from testlib import assertTrue, TestNotApplicable, CompileError
 
 MSTATUS_UIE = 0x00000001
 MSTATUS_SIE = 0x00000002
@@ -77,6 +78,23 @@
 def readable_binary_string(s):
     return "".join("%02x" % ord(c) for c in s)
 
+class InfoTest(GdbTest):
+    def test(self):
+        output = self.gdb.command("monitor riscv info")
+        info = {}
+        for line in output.splitlines():
+            if re.search(r"Found \d+ triggers", line):
+                continue
+            if re.search(r"Disabling abstract command writes to CSRs.", line):
+                continue
+            if re.search(
+                    r"keep_alive.. was not invoked in the \d+ ms timelimit.",
+                    line):
+                continue
+            k, v = line.strip().split()
+            info[k] = v
+        assertEqual(int(info.get("hart.xlen")), self.hart.xlen)
+
 class SimpleRegisterTest(GdbTest):
     def check_reg(self, name, alias):
         a = random.randrange(1<<self.hart.xlen)
@@ -170,7 +188,7 @@
         return self.target.implements_custom_test
 
     def check_custom(self, magic):
-        regs = {k: v for k, v in self.gdb.info_registers("all").items()
+        regs = {k: v for k, v in self.gdb.info_registers("all", ops=20).items()
                 if k.startswith("custom")}
         assertEqual(set(regs.keys()),
                 set(("custom1",
@@ -237,18 +255,25 @@
     def test(self):
         self.access_test(8, 'long long')
 
-# FIXME: I'm not passing back invalid addresses correctly in read/write memory.
-#class MemTestReadInvalid(SimpleMemoryTest):
-#    def test(self):
-#        # This test relies on 'gdb_report_data_abort enable' being executed in
-#        # the openocd.cfg file.
-#        try:
-#            self.gdb.p("*((int*)0xdeadbeef)")
-#            assert False, "Read should have failed."
-#        except testlib.CannotAccess as e:
-#            assertEqual(e.address, 0xdeadbeef)
-#        self.gdb.p("*((int*)0x%x)" % self.hart.ram)
-#
+class MemTestReadInvalid(SimpleMemoryTest):
+    def test(self):
+        bad_address = self.hart.bad_address
+        good_address = self.hart.ram + 0x80
+
+        self.write_nop_program(2)
+        self.gdb.p("$s0=0x12345678")
+        self.gdb.p("*((int*)0x%x)=0xabcdef" % good_address)
+        # This test relies on 'gdb_report_data_abort enable' being executed in
+        # the openocd.cfg file.
+        try:
+            self.gdb.p("*((int*)0x%x)" % bad_address)
+            assert False, "Read should have failed."
+        except testlib.CannotAccess as e:
+            assertEqual(e.address, bad_address)
+        self.gdb.stepi()    # Don't let gdb cache register read
+        assertEqual(self.gdb.p("*((int*)0x%x)" % good_address), 0xabcdef)
+        assertEqual(self.gdb.p("$s0"), 0x12345678)
+
 #class MemTestWriteInvalid(SimpleMemoryTest):
 #    def test(self):
 #        # This test relies on 'gdb_report_data_abort enable' being executed in
@@ -569,10 +594,10 @@
         self.exit()
 
 class Hwbp1(DebugTest):
-    def test(self):
-        if self.hart.instruction_hardware_breakpoint_count < 1:
-            raise TestNotApplicable
+    def early_applicable(self):
+        return self.hart.instruction_hardware_breakpoint_count > 0
 
+    def test(self):
         if not self.hart.honors_tdata1_hmode:
             # Run to main before setting the breakpoint, because startup code
             # will otherwise clear the trigger that we set.
@@ -590,11 +615,103 @@
         self.gdb.b("_exit")
         self.exit()
 
-class Hwbp2(DebugTest):
-    def test(self):
-        if self.hart.instruction_hardware_breakpoint_count < 2:
-            raise TestNotApplicable
+def MCONTROL_TYPE(xlen):
+    return 0xf<<((xlen)-4)
+def MCONTROL_DMODE(xlen):
+    return 1<<((xlen)-5)
+def MCONTROL_MASKMAX(xlen):
+    return 0x3<<((xlen)-11)
 
+MCONTROL_SELECT = (1<<19)
+MCONTROL_TIMING = (1<<18)
+MCONTROL_ACTION = (0x3f<<12)
+MCONTROL_CHAIN = (1<<11)
+MCONTROL_MATCH = (0xf<<7)
+MCONTROL_M = (1<<6)
+MCONTROL_H = (1<<5)
+MCONTROL_S = (1<<4)
+MCONTROL_U = (1<<3)
+MCONTROL_EXECUTE = (1<<2)
+MCONTROL_STORE = (1<<1)
+MCONTROL_LOAD = (1<<0)
+
+MCONTROL_TYPE_NONE = 0
+MCONTROL_TYPE_MATCH = 2
+
+MCONTROL_ACTION_DEBUG_EXCEPTION = 0
+MCONTROL_ACTION_DEBUG_MODE = 1
+MCONTROL_ACTION_TRACE_START = 2
+MCONTROL_ACTION_TRACE_STOP = 3
+MCONTROL_ACTION_TRACE_EMIT = 4
+
+MCONTROL_MATCH_EQUAL = 0
+MCONTROL_MATCH_NAPOT = 1
+MCONTROL_MATCH_GE = 2
+MCONTROL_MATCH_LT = 3
+MCONTROL_MATCH_MASK_LOW = 4
+MCONTROL_MATCH_MASK_HIGH = 5
+
+def set_field(reg, mask, val):
+    return ((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))
+
+class HwbpManual(DebugTest):
+    """Make sure OpenOCD behaves "normal" when the user sets a trigger by
+    writing the trigger registers themselves directly."""
+    def early_applicable(self):
+        return self.target.support_manual_hwbp and \
+            self.hart.instruction_hardware_breakpoint_count >= 1
+
+    def test(self):
+        if not self.hart.honors_tdata1_hmode:
+            # Run to main before setting the breakpoint, because startup code
+            # will otherwise clear the trigger that we set.
+            self.gdb.b("main")
+            self.gdb.c()
+
+        self.gdb.command("delete")
+        #self.gdb.hbreak("rot13")
+        tdata1 = MCONTROL_DMODE(self.hart.xlen)
+        tdata1 = set_field(tdata1, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE)
+        tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL)
+        tdata1 |= MCONTROL_M | MCONTROL_S | MCONTROL_U | MCONTROL_EXECUTE
+
+        tselect = 0
+        while True:
+            self.gdb.p("$tselect=%d" % tselect)
+            value = self.gdb.p("$tselect")
+            if value != tselect:
+                raise TestNotApplicable
+            self.gdb.p("$tdata1=0x%x" % tdata1)
+            value = self.gdb.p("$tselect")
+            if value == tdata1:
+                break
+            self.gdb.p("$tdata1=0")
+            tselect += 1
+
+        self.gdb.p("$tdata2=&rot13")
+        # The breakpoint should be hit exactly 2 times.
+        for _ in range(2):
+            output = self.gdb.c(ops=2)
+            self.gdb.p("$pc")
+            assertRegex(output, r"[bB]reakpoint")
+            assertIn("rot13 ", output)
+        self.gdb.p("$tdata2=&crc32a")
+        self.gdb.c()
+        before = self.gdb.p("$pc")
+        assertEqual(before, self.gdb.p("&crc32a"))
+        self.gdb.stepi()
+        after = self.gdb.p("$pc")
+        assertNotEqual(before, after)
+
+        self.gdb.b("_exit")
+        self.exit()
+
+
+class Hwbp2(DebugTest):
+    def early_applicable(self):
+        return self.hart.instruction_hardware_breakpoint_count >= 2
+
+    def test(self):
         self.gdb.command("delete")
         self.gdb.hbreak("main")
         self.gdb.hbreak("rot13")
@@ -615,9 +732,14 @@
 
         output = self.gdb.c(checkOutput=False)
         assertIn("Cannot insert hardware breakpoint", output)
+        # There used to be a bug where this would fail if done twice in a row.
+        output = self.gdb.c(checkOutput=False)
+        assertIn("Cannot insert hardware breakpoint", output)
         # Clean up, otherwise the hardware breakpoints stay set and future
         # tests may fail.
-        self.gdb.command("D")
+        self.gdb.command("delete")
+        self.gdb.b("_exit")
+        self.exit()
 
 class Registers(DebugTest):
     def test(self):
@@ -667,6 +789,163 @@
         self.gdb.p("i=0")
         self.exit()
 
+class MemorySampleTest(DebugTest):
+    def early_applicable(self):
+        return self.target.support_memory_sampling
+
+    def setup(self):
+        DebugTest.setup(self)
+        self.gdb.b("main:start")
+        self.gdb.c()
+        self.gdb.p("i=123")
+
+    @staticmethod
+    def check_incrementing_samples(raw_samples, check_addr,
+                                   tolerance=0x200000):
+        first_timestamp = None
+        end = None
+        total_samples = 0
+        previous_value = None
+        for line in raw_samples.splitlines():
+            m = re.match(r"^timestamp \w+: (\d+)", line)
+            if m:
+                timestamp = int(m.group(1))
+                if not first_timestamp:
+                    first_timestamp = timestamp
+                else:
+                    end = (timestamp, total_samples)
+            else:
+                address, value = line.split(': ')
+                address = int(address, 16)
+                if address == check_addr:
+                    value = int(value, 16)
+                    if not previous_value is None:
+                        # TODO: what if the counter wraps?
+                        assertGreater(value, previous_value)
+                        assertLess(value, previous_value + tolerance)
+                    previous_value = value
+                total_samples += 1
+        if end and total_samples > 0:
+            print("%d samples/second" % (1000 * end[1] / (end[0] -
+                first_timestamp)))
+        else:
+            raise Exception("No samples collected.")
+
+    @staticmethod
+    def check_samples_equal(raw_samples, check_addr, check_value):
+        total_samples = 0
+        for line in raw_samples.splitlines():
+            if not line.startswith("timestamp "):
+                address, value = line.split(': ')
+                address = int(address, 16)
+                if address == check_addr:
+                    value = int(value, 16)
+                    assertEqual(value, check_value)
+                    total_samples += 1
+        assertGreater(total_samples, 0)
+
+    def collect_samples(self):
+        self.gdb.c(wait=False)
+        time.sleep(5)
+        output = self.gdb.interrupt()
+        assert "main" in output
+        return self.gdb.command("monitor riscv dump_sample_buf", ops=5)
+
+class MemorySampleSingle(MemorySampleTest):
+    def test(self):
+        addr = self.gdb.p("&j")
+        sizeof_j = self.gdb.p("sizeof(j)")
+        self.gdb.command("monitor riscv memory_sample 0 0x%x %d" % (
+                addr, sizeof_j))
+
+        raw_samples = self.collect_samples()
+        self.check_incrementing_samples(raw_samples, addr)
+
+        # Buffer should have been emptied by dumping.
+        raw_samples = self.gdb.command("monitor riscv dump_sample_buf", ops=5)
+        assertEqual(len(raw_samples), 0)
+
+class MemorySampleMixed(MemorySampleTest):
+    def test(self):
+        addr = {}
+        for i, name in enumerate(("j", "i32", "i64")):
+            addr[name] = self.gdb.p("&%s" % name)
+            sizeof = self.gdb.p("sizeof(%s)" % name)
+            self.gdb.command("monitor riscv memory_sample %d 0x%x %d" % (
+                    i, addr[name], sizeof))
+
+        raw_samples = self.collect_samples()
+        self.check_incrementing_samples(raw_samples, addr["j"],
+                                        tolerance=0x400000)
+        self.check_samples_equal(raw_samples, addr["i32"], 0xdeadbeef)
+        self.check_samples_equal(raw_samples, addr["i64"], 0x1122334455667788)
+
+class RepeatReadTest(DebugTest):
+    def early_applicable(self):
+        return self.target.supports_clint_mtime
+
+    def test(self):
+        self.gdb.b("main:start")
+        self.gdb.c()
+        mtime_addr = 0x02000000 + 0xbff8
+        count = 1024
+        output = self.gdb.command("monitor riscv repeat_read %d 0x%x 4" %
+                (count, mtime_addr))
+        values = []
+        for line in output.splitlines():
+            # Ignore warnings
+            if line.startswith("Batch memory"):
+                continue
+            for v in line.split():
+                values.append(int(v, 16))
+
+        assertEqual(len(values), count)
+        # mtime should only ever increase, unless it wraps
+        slop = 0x100000
+        for i in range(1, len(values)):
+            if values[i] < values[i-1]:
+                # wrapped
+                assertLess(values[i], slop)
+            else:
+                assertGreater(values[i], values[i-1])
+                assertLess(values[i], values[i-1] + slop)
+
+        output = self.gdb.command("monitor riscv repeat_read 0 0x%x 4" %
+                mtime_addr)
+        assertEqual(output, "")
+
+class Semihosting(GdbSingleHartTest):
+    # Include malloc so that gdb can assign a string.
+    compile_args = ("programs/semihosting.c", "programs/tiny-malloc.c",
+                    "-DDEFINE_MALLOC", "-DDEFINE_FREE")
+
+    def early_applicable(self):
+        return self.target.test_semihosting
+
+    def setup(self):
+        self.gdb.load()
+        self.parkOtherHarts()
+        self.gdb.b("_exit")
+
+    def exit(self, expected_result=0):
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("_exit", output)
+        assertEqual(self.gdb.p("status"), expected_result)
+
+    def test(self):
+        """Sending gdb ^C while the program is running should cause it to
+        halt."""
+        temp = tempfile.NamedTemporaryFile(suffix=".data")
+
+        self.gdb.b("main:begin")
+        self.gdb.c()
+        self.gdb.p('filename="%s"' % temp.name, ops=3)
+        self.exit()
+
+        contents = open(temp.name, "r").readlines()
+        assertIn("Hello, world!\n", contents)
+
 class InterruptTest(GdbSingleHartTest):
     compile_args = ("programs/interrupt.c",)
 
@@ -738,18 +1017,18 @@
             self.gdb.c()
             assertIn("main_end", self.gdb.where())
 
-        hart_ids = []
+        hart_ids = set()
         for hart in self.target.harts:
             self.gdb.select_hart(hart)
             # Check register values.
             x1 = self.gdb.p("$x1")
             hart_id = self.gdb.p("$mhartid")
             assertEqual(x1, hart_id << 8)
-            assertNotIn(hart_id, hart_ids)
-            hart_ids.append(hart_id)
+            assertNotIn((hart.system, hart_id), hart_ids)
+            hart_ids.add((hart.system, hart_id))
             for n in range(2, 32):
                 value = self.gdb.p("$x%d" % n)
-                assertEqual(value, (hart_ids[-1] << 8) + n - 1)
+                assertEqual(value, (hart_id << 8) + n - 1)
 
         # Confirmed that we read different register values for different harts.
         # Write a new value to x1, and run through the add sequence again.
@@ -1053,7 +1332,8 @@
 
 class TriggerDmode(TriggerTest):
     def early_applicable(self):
-        return self.hart.honors_tdata1_hmode
+        return self.hart.honors_tdata1_hmode and \
+                self.hart.instruction_hardware_breakpoint_count > 0
 
     def check_triggers(self, tdata1_lsbs, tdata2):
         dmode = 1 << (self.hart.xlen-5)
@@ -1156,6 +1436,8 @@
         assertEqual(123, self.gdb.p("$csr832"))
 
 class DownloadTest(GdbTest):
+    compile_args = ("programs/infinite_loop.S", )
+
     def setup(self):
         # pylint: disable=attribute-defined-outside-init
         length = min(2**18, max(2**10, self.hart.ram_size - 2048))
@@ -1188,15 +1470,23 @@
         if self.crc < 0:
             self.crc += 2**32
 
-        self.binary = self.target.compile(self.hart, self.download_c.name,
-                "programs/checksum.c")
-        self.gdb.global_command("file %s" % self.binary)
+        compiled = {}
+        for hart in self.target.harts:
+            key = hart.system
+            if key not in compiled:
+                compiled[key] = self.target.compile(hart, self.download_c.name,
+                        "programs/checksum.c")
+            self.gdb.select_hart(hart)
+            self.gdb.command("file %s" % compiled.get(key))
+
+        self.gdb.select_hart(self.hart)
 
     def test(self):
         self.gdb.load()
         self.parkOtherHarts()
         self.gdb.command("b _exit")
-        self.gdb.c(ops=100)
+        #self.gdb.c(ops=100)
+        self.gdb.c()
         assertEqual(self.gdb.p("status"), self.crc)
         os.unlink(self.download_c.name)
 
@@ -1289,6 +1579,7 @@
         self.disable_pmp()
 
         self.gdb.load()
+        self.parkOtherHarts()
         self.gdb.b("main")
         output = self.gdb.c()
         assertRegex(output, r"\bmain\b")
@@ -1352,6 +1643,132 @@
         self.gdb.p("vms=&sv48")
         self.test_translation()
 
+class VectorTest(GdbSingleHartTest):
+    compile_args = ("programs/vectors.S", )
+
+    def early_applicable(self):
+        if not self.hart.extensionSupported('V'):
+            return False
+        # If the compiler can't build this test, say it's not applicable. At
+        # some time all compilers will support the V extension, but we're not
+        # there yet.
+        try:
+            self.compile()
+        except CompileError as e:
+            if b"Error: unknown CSR `vlenb'" in e.stderr:
+                return False
+        return True
+
+    def setup(self):
+        self.gdb.load()
+        self.gdb.b("main")
+        self.gdb.c()
+
+    def test(self):
+        vlenb = self.gdb.p("$vlenb")
+        self.gdb.command("delete")
+        self.gdb.b("_exit")
+        self.gdb.b("trap_entry")
+
+        self.gdb.b("test0")
+
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("test0", output)
+
+        # I'm not convinced that writing 0 is supported on every vector
+        # implementation. If this test fails, that might be why.
+        for regname in ('$vl', '$vtype'):
+            value = self.gdb.p(regname)
+            assertNotEqual(value, 0)
+            self.gdb.p("%s=0" % regname)
+            self.gdb.command("flushregs")
+            assertEqual(self.gdb.p(regname), 0)
+            self.gdb.p("%s=0x%x" % (regname, value))
+            self.gdb.command("flushregs")
+            assertEqual(self.gdb.p(regname), value)
+
+        assertEqual(self.gdb.p("$a0"), 0)
+        a = self.gdb.x("&a", 'b', vlenb)
+        b = self.gdb.x("&b", 'b', vlenb)
+        v4 = self.gdb.p("$v4")
+        assertEqual(a, b)
+        assertEqual(b, v4["b"])
+        assertEqual(0, self.gdb.p("$a0"))
+
+        self.gdb.b("test1")
+
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("test1", output)
+
+        assertEqual(self.gdb.p("$a0"), 0)
+        b = self.gdb.x("&b", 'b', vlenb)
+        c = self.gdb.x("&c", 'b', vlenb)
+        v4 = self.gdb.p("$v4")
+        assertEqual(b, c)
+        assertEqual(c, v4["b"])
+        assertEqual(0, self.gdb.p("$a0"))
+
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("_exit", output)
+        assertEqual(self.gdb.p("status"), 0)
+
+class FreeRtosTest(GdbTest):
+    def early_applicable(self):
+        return self.target.freertos_binary
+
+    def freertos(self):
+        return True
+
+    def test(self):
+        self.gdb.command("file %s" % self.target.freertos_binary)
+        self.gdb.load()
+
+        output = self.gdb.command("monitor riscv_freertos_stacking mainline")
+
+        # Turn off htif, which doesn't work when the file is loaded into spike
+        # through gdb. It only works when spike loads the ELF file itself.
+        bp = self.gdb.b("main")
+        self.gdb.c()
+        self.gdb.command("delete %d" % bp)
+        self.gdb.p("*((int*) &use_htif) = 0")
+        # Need this, otherwise gdb complains that there is no current active
+        # thread.
+        self.gdb.threads()
+
+        bp = self.gdb.b("prvQueueReceiveTask")
+
+        self.gdb.c()
+        self.gdb.command("delete %d" % bp)
+
+        bp = self.gdb.b("prvQueueSendTask")
+        self.gdb.c()
+        self.gdb.command("delete %d" % bp)
+
+        # Now we know for sure at least 2 threads have executed.
+
+        threads = self.gdb.threads()
+        assertGreater(len(threads), 1)
+
+        values = {}
+        for thread in threads:
+            assertNotIn("No Name", thread[1])
+            self.gdb.thread(thread)
+            assertEqual(self.gdb.p("$zero"), 0)
+            output = self.gdb.command("info reg sp")
+            assertIn("ucHeap", output)
+            self.gdb.command("info reg mstatus")
+            values[thread.id] = self.gdb.p("$s11")
+            self.gdb.p("$s11=0x%x" % (values[thread.id] ^ int(thread.id)))
+
+        # Test that writing worked
+        self.gdb.stepi()
+        for thread in self.gdb.threads():
+            self.gdb.thread(thread)
+            assertEqual(self.gdb.p("$s11"), values[thread.id] ^ int(thread.id))
+
 parsed = None
 def main():
     parser = argparse.ArgumentParser(
diff --git a/src/riscv-tests/debug/programs/debug.c b/src/riscv-tests/debug/programs/debug.c
index 8a4aa73..641aa4e 100644
--- a/src/riscv-tests/debug/programs/debug.c
+++ b/src/riscv-tests/debug/programs/debug.c
@@ -55,6 +55,8 @@
     int j = 0;
     char fox[] = "The quick brown fox jumps of the lazy dog.";
     unsigned int checksum = 0;
+    volatile uint32_t i32 = 0xdeadbeef;
+    volatile uint64_t i64 = 0x1122334455667788;
 
 start:
     while (i)
diff --git a/src/riscv-tests/debug/programs/entry.S b/src/riscv-tests/debug/programs/entry.S
index 3796b3b..091efa4 100755
--- a/src/riscv-tests/debug/programs/entry.S
+++ b/src/riscv-tests/debug/programs/entry.S
@@ -71,6 +71,9 @@
   addi  t0, t0, -1
   bnez  t0, 1b
 
+  # Catch trap in case trigger module is not implemented
+  la t2, 2f
+  csrrw t2, mtvec, t2
   # Clear all hardware triggers
   li    t0, ~0
 1:
@@ -79,6 +82,10 @@
   csrw  CSR_TDATA1, zero
   csrr  t1, CSR_TSELECT
   beq   t0, t1, 1b
+.p2align 2
+2:
+  # Restore mtvec
+  csrw mtvec, t2
 
 #ifdef MULTICORE
   csrr  t0, CSR_MHARTID
diff --git a/src/riscv-tests/debug/programs/semihosting.c b/src/riscv-tests/debug/programs/semihosting.c
new file mode 100644
index 0000000..2ceea8c
--- /dev/null
+++ b/src/riscv-tests/debug/programs/semihosting.c
@@ -0,0 +1,73 @@
+#include <stdint.h>
+
+#include "semihosting.h"
+
+size_t strlen(const char *buf)
+{
+    int len = 0;
+    while (buf[len])
+        len++;
+    return len;
+}
+
+#define O_RDONLY         0
+#define O_WRONLY         1
+#define O_RDWR           2
+#define O_RDWR           2
+#define O_TRUNC		0x0800
+
+int errno;
+
+/* These semihosting functions came from the Freedom Metal source. */
+static int open(const char *name, int flags, int mode) {
+    int semiflags = 0;
+
+    switch (flags & (O_RDONLY | O_WRONLY | O_RDWR)) {
+    case O_RDONLY:
+        semiflags = 0; /* 'r' */
+        break;
+    case O_WRONLY:
+        if (flags & O_TRUNC)
+            semiflags = 4; /* 'w' */
+        else
+            semiflags = 8; /* 'a' */
+        break;
+    default:
+        if (flags & O_TRUNC)
+            semiflags = 6; /* 'w+' */
+        else
+            semiflags = 10; /* 'a+' */
+        break;
+    }
+
+    volatile semihostparam_t arg = {.param1 = (uintptr_t)name,
+                                    .param2 = (uintptr_t)semiflags,
+                                    .param3 = (uintptr_t)strlen(name)};
+
+    int ret = (int)semihost_call_host(SEMIHOST_SYS_OPEN, (uintptr_t)&arg);
+    if (ret == -1)
+        errno = semihost_call_host(SEMIHOST_SYS_ERRNO, 0);
+    return ret;
+}
+
+static ssize_t write(int file, const void *ptr, size_t len)
+{
+    volatile semihostparam_t arg = {.param1 = (uintptr_t)file,
+                                    .param2 = (uintptr_t)ptr,
+                                    .param3 = (uintptr_t)len};
+    ssize_t ret =
+        (ssize_t)semihost_call_host(SEMIHOST_SYS_WRITE, (uintptr_t)&arg);
+
+    return (len - ret);
+}
+
+int main()
+{
+    char *filename = NULL;
+    const char *message = "Hello, world!\n";
+    int fd;
+
+begin:
+    fd = open(filename, O_WRONLY, 0644);
+    write(fd, message, strlen(message));
+}
\ No newline at end of file
diff --git a/src/riscv-tests/debug/programs/semihosting.h b/src/riscv-tests/debug/programs/semihosting.h
new file mode 100644
index 0000000..201e414
--- /dev/null
+++ b/src/riscv-tests/debug/programs/semihosting.h
@@ -0,0 +1,82 @@
+#include <sys/types.h>
+
+#ifndef _SEMIHOSTING_H_
+#define _SEMIHOSTING_H_
+
+// ----------------------------------------------------------------------------
+
+// Semihosting operations.
+enum Semihost_Sys_Op {
+    // Regular operations
+    SEMIHOST_SYS_CLOCK = 0x10,
+    SEMIHOST_SYS_CLOSE = 0x02,
+    SEMIHOST_SYS_ELAPSED = 0x30,
+    SEMIHOST_SYS_ERRNO = 0x13,
+    SEMIHOST_SYS_EXIT = 0x18,
+    SEMIHOST_SYS_EXIT_EXTENDED = 0x20,
+    SEMIHOST_SYS_FLEN = 0x0C,
+    SEMIHOST_SYS_GET_CMDLINE = 0x15,
+    SEMIHOST_SYS_HEAPINFO = 0x16,
+    SEMIHOST_SYS_ISERROR = 0x08,
+    SEMIHOST_SYS_ISTTY = 0x09,
+    SEMIHOST_SYS_OPEN = 0x01,
+    SEMIHOST_SYS_READ = 0x06,
+    SEMIHOST_SYS_READC = 0x07,
+    SEMIHOST_SYS_REMOVE = 0x0E,
+    SEMIHOST_SYS_RENAME = 0x0F,
+    SEMIHOST_SYS_SEEK = 0x0A,
+    SEMIHOST_SYS_SYSTEM = 0x12,
+    SEMIHOST_SYS_TICKFREQ = 0x31,
+    SEMIHOST_SYS_TIME = 0x11,
+    SEMIHOST_SYS_TMPNAM = 0x0D,
+    SEMIHOST_SYS_WRITE = 0x05,
+    SEMIHOST_SYS_WRITEC = 0x03,
+    SEMIHOST_SYS_WRITE0 = 0x04,
+};
+
+enum ADP_Code {
+    ADP_Stopped_BranchThroughZero = 0x20000,
+    ADP_Stopped_UndefinedInstr = 0x20001,
+    ADP_Stopped_SoftwareInterrupt = 0x20002,
+    ADP_Stopped_PrefetchAbort = 0x20003,
+    ADP_Stopped_DataAbort = 0x20004,
+    ADP_Stopped_AddressException = 0x20005,
+    ADP_Stopped_IRQ = 0x20006,
+    ADP_Stopped_FIQ = 0x20007,
+    ADP_Stopped_BreakPoint = 0x20020,
+    ADP_Stopped_WatchPoint = 0x20021,
+    ADP_Stopped_StepComplete = 0x20022,
+    ADP_Stopped_RunTimeErrorUnknown = 0x20023,
+    ADP_Stopped_InternalError = 0x20024,
+    ADP_Stopped_UserInterruption = 0x20025,
+    ADP_Stopped_ApplicationExit = 0x20026,
+    ADP_Stopped_StackOverflow = 0x20027,
+    ADP_Stopped_DivisionByZero = 0x20028,
+    ADP_Stopped_OSSpecific = 0x20029,
+};
+
+typedef struct {
+    uintptr_t param1;
+    uintptr_t param2;
+    uintptr_t param3;
+} semihostparam_t;
+
+static inline uintptr_t __attribute__((always_inline))
+semihost_call_host(uintptr_t op, uintptr_t arg) {
+    register uintptr_t r0 asm("a0") = op;
+    register uintptr_t r1 asm("a1") = arg;
+
+    asm volatile(".option push               \n"
+                 ".option norvc              \n"
+                 " slli    zero,zero,0x1f    \n"
+                 " ebreak                    \n"
+                 " srai    zero,zero,0x7     \n"
+                 ".option pop                \n"
+
+                 : "=r"(r0)         /* Outputs */
+                 : "r"(r0), "r"(r1) /* Inputs */
+                 : "memory");
+    return r0;
+}
+
+#endif
\ No newline at end of file
diff --git a/src/riscv-tests/debug/programs/vectors.S b/src/riscv-tests/debug/programs/vectors.S
new file mode 100644
index 0000000..53e53be
--- /dev/null
+++ b/src/riscv-tests/debug/programs/vectors.S
@@ -0,0 +1,159 @@
+#include "encoding.h"
+
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+
+        .global main
+        .global main_end
+        .global main_post_csrr
+
+        // Load constants into all registers so we can test no register are
+        // clobbered after attaching.
+main:
+        SREG    ra, 0(sp)
+        addi    sp, sp, REGBYTES
+
+        // Set VS=1
+        csrr    t0, CSR_MSTATUS
+        li      t1, set_field(0, MSTATUS_VS, 1)
+        or      t0, t0, t1
+        csrw    CSR_MSTATUS, t0
+
+        // copy a to b
+        la      a0, a
+        jal     vector_load_v4
+        la      a0, b
+        jal     shift_store_v4
+
+        // assert a == b
+        la      a0, a
+        la      a1, b
+        jal     check_equal
+test0:
+        bne     a0, zero, return_from_main
+
+        // copy b to c
+        la      a0, b
+        jal     shift_load_v4
+        la      a0, c
+        jal     vector_store_v4
+
+        // assert b == c
+        la      a0, b
+        la      a1, c
+        jal     check_equal
+test1:
+        bne     a0, zero, return_from_main
+
+return_from_main:
+        addi    sp, sp, -REGBYTES
+        LREG    ra, 0(sp)
+        ret
+
+vector_load_v4:
+        // a0: point to memory to load from
+        csrr    s0, vlenb
+        vsetvli zero, s0, e8, m1  # Vectors of 8b
+        vle8.v v4, 0(a0)          # Load bytes
+        ret
+
+vector_store_v4:
+        // a0: point to memory to store to
+        csrr    s0, vlenb
+        vsetvli zero, s0, e8, m1  # Vectors of 8b
+        vse8.v v4, 0(a0)          # Load bytes
+        ret
+
+shift_load_v4:
+        // a0: pointer to memory to load from
+
+        // Configure all elements in the chain
+        csrr    s0, vlenb
+#if XLEN == 32
+        vsetvli zero, s0, e32
+#else
+        vsetvli zero, s0, e64
+#endif
+
+        // Figure out how long the chain is.
+        csrr    s0, vlenb
+        li      s1, XLEN/8
+        divu    s0, s0, s1
+
+1:
+        LREG    s2, 0(a0)
+        vslide1down.vx  v4, v4, s2
+        addi    a0, a0, REGBYTES
+        addi    s0, s0, -1
+        bne     s0, zero, 1b
+
+        ret
+
+shift_store_v4:
+        // a0: pointer to memory to store to
+
+        // Configure all elements in the chain
+        csrr    s0, vlenb
+#if XLEN == 32
+        vsetvli zero, s0, e32
+#else
+        vsetvli zero, s0, e64
+#endif
+
+        // Figure out how long the chain is.
+        csrr    s0, vlenb
+        li      s1, XLEN/8
+        divu    s0, s0, s1
+
+1:
+        vmv.x.s s2, v4
+        SREG    s2, 0(a0)
+        vslide1down.vx  v4, v4, s2
+        addi    a0, a0, REGBYTES
+        addi    s0, s0, -1
+        bne     s0, zero, 1b
+
+        ret
+
+check_equal:
+        csrr    s0, vlenb
+1:
+        lb      s1, 0(a0)
+        lb      s2, 0(a1)
+        bne     s1, s2, 2f
+        addi    a0, a0, 1
+        addi    a1, a1, 1
+        addi    s0, s0, -1
+        bne     s0, zero, 1b
+        li      a0, 0   // equal
+        ret
+2:      // unequal
+        li      a0, 1
+        ret
+
+        .data
+        .align  6
+a:      .word   0xaa00, 0xaa01, 0xaa02, 0xaa03, 0xaa04, 0xaa05, 0xaa06, 0xaa07
+        .word   0xaa08, 0xaa09, 0xaa0a, 0xaa0b, 0xaa0c, 0xaa0d, 0xaa0e, 0xaa0f
+        .word   0xaa10, 0xaa11, 0xaa12, 0xaa13, 0xaa14, 0xaa15, 0xaa16, 0xaa17
+        .word   0xaa18, 0xaa19, 0xaa1a, 0xaa1b, 0xaa1c, 0xaa1d, 0xaa1e, 0xaa1f
+
+b:      .word   0xbb00, 0xbb01, 0xbb02, 0xbb03, 0xbb04, 0xbb05, 0xbb06, 0xbb07
+        .word   0xbb08, 0xbb09, 0xbb0b, 0xbb0b, 0xbb0c, 0xbb0d, 0xbb0e, 0xbb0f
+        .word   0xbb10, 0xbb11, 0xbb13, 0xbb13, 0xbb14, 0xbb15, 0xbb16, 0xbb17
+        .word   0xbb18, 0xbb19, 0xbb1b, 0xbb1b, 0xbb1c, 0xbb1d, 0xbb1e, 0xbb1f
+
+c:      .word   0xcc00, 0xcc01, 0xcc02, 0xcc03, 0xcc04, 0xcc05, 0xcc06, 0xcc07
+        .word   0xcc08, 0xcc09, 0xcc0c, 0xcc0c, 0xcc0c, 0xcc0d, 0xcc0e, 0xcc0f
+        .word   0xcc10, 0xcc11, 0xcc13, 0xcc13, 0xcc14, 0xcc15, 0xcc16, 0xcc17
+        .word   0xcc18, 0xcc19, 0xcc1c, 0xcc1c, 0xcc1c, 0xcc1d, 0xcc1e, 0xcc1f
\ No newline at end of file
diff --git a/src/riscv-tests/debug/rbb_daisychain.py b/src/riscv-tests/debug/rbb_daisychain.py
new file mode 100755
index 0000000..b7c21e6
--- /dev/null
+++ b/src/riscv-tests/debug/rbb_daisychain.py
@@ -0,0 +1,111 @@
+#!/usr/bin/python3
+
+import argparse
+import sys
+import socket
+
+# https://github.com/ntfreak/openocd/blob/master/doc/manual/jtag/drivers/remote_bitbang.txt
+
+class Tap:
+    def __init__(self, port):
+        self.port = port
+        self.socket = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+        self.socket.connect(("localhost", port))
+
+    def execute(self, commands):
+        sent = self.socket.send(commands)
+        assert len(commands) == sent
+        read_count = 0
+        for command in commands:
+            if command == ord('R'):
+                read_count += 1
+        result = b""
+        while len(result) < read_count:
+            result += self.socket.recv(read_count - len(result))
+        assert len(result) == read_count
+        return result
+
+class Chain:
+    def __init__(self, debug=False):
+        self.debug = debug
+        self.taps = []
+
+    def append(self, tap):
+        self.taps.append(tap)
+
+    def execute(self, commands):
+        values = []
+        for i, tap in enumerate(self.taps):
+            tmp_commands = []
+            for command in commands:
+                if i > 0 and ord('0') <= command <= ord('7'):
+                    # Replace TDI with the value from the previous TAP.
+                    v = values.pop(0)
+                    command &= 0xfe
+                    if v == ord('1'):
+                        command |= 1
+
+                if i < len(self.taps) - 1:
+                    if command != ord('R'):
+                        tmp_commands.append(command)
+                    if ord('0') <= command <= ord('7'):
+                        # Read TDO before every scan.
+                        tmp_commands.append(ord('R'))
+                else:
+                    tmp_commands.append(command)
+            assert len(values) == 0
+            values = list(tap.execute(bytes(tmp_commands)))
+            if self.debug:
+                sys.stdout.write("    %d %r -> %r\n" % (i, bytes(tmp_commands),
+                                                        bytes(values)))
+        return bytes(values)
+
+def main():
+    parser = argparse.ArgumentParser(
+            description='Combine multiple remote_bitbang processes into a '
+            'single scan-chain.')
+    parser.add_argument("listen_port", type=int,
+            help="port to listen on")
+    parser.add_argument("tap_port", nargs="+", type=int,
+            help="port of a remote_bitbang TAP to connect to")
+    parser.add_argument("--debug", action='store_true',
+                        help="Print out debug messages.")
+    args = parser.parse_args()
+
+    server = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+    server.bind(("localhost", args.listen_port))
+    server.listen(1)
+
+    chain = Chain(args.debug)
+    for port in args.tap_port:
+        chain.append(Tap(port))
+
+    sys.stdout.write("Listening on port %d.\n" % server.getsockname()[1])
+    sys.stdout.flush()
+
+    while True:
+        (client, _) = server.accept()
+
+        while True:
+            try:
+                commands = client.recv(4096)
+            except (ConnectionResetError, OSError):
+                sys.stdout.write("Client disconnected due to exception.\n")
+                break
+
+            if len(commands) == 0:
+                sys.stdout.write("Client disconnected.\n")
+                break
+
+            if args.debug:
+                sys.stdout.write("%r\n" % commands)
+            result = chain.execute(commands)
+            if args.debug:
+                sys.stdout.write("   -> %r\n" % result)
+            client.send(result)
+
+        client.close()
+        sys.stdout.flush()
+
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/src/riscv-tests/debug/targets.py b/src/riscv-tests/debug/targets.py
index f4192b6..dd0175e 100644
--- a/src/riscv-tests/debug/targets.py
+++ b/src/riscv-tests/debug/targets.py
@@ -1,5 +1,6 @@
 import importlib
 import os.path
+import re
 import sys
 import tempfile
 
@@ -28,6 +29,10 @@
     ram = None
     ram_size = None
 
+    # Address where we expect memory accesses to fail, usually because there is
+    # no device mapped to that location.
+    bad_address = None
+
     # Number of instruction triggers the hart supports.
     instruction_hardware_breakpoint_count = 0
 
@@ -39,6 +44,20 @@
     # jumpers.
     reset_vectors = []
 
+    # system is set to an identifier of the system this hart belongs to.  Harts
+    # within the same system are assumed to share memory, and to have unique
+    # hartids within that system.  So for most cases the default value of None
+    # is fine.
+    system = None
+
+    def __init__(self, misa=None, system=None, link_script_path=None):
+        if misa:
+            self.misa = misa
+        if system:
+            self.system = system
+        if link_script_path:
+            self.link_script_path = link_script_path
+
     def extensionSupported(self, letter):
         # target.misa is set by testlib.ExamineTarget
         if self.misa:
@@ -91,6 +110,22 @@
     # whether they are applicable or not.
     skip_tests = []
 
+    # Set False if semihosting should not be tested in this configuration,
+    # because it doesn't work and isn't expected to work.
+    test_semihosting = True
+
+    # Set False if manual hwbps (breakpoints set by directly writing tdata*)
+    # isn't supposed to work.
+    support_manual_hwbp = True
+
+    # Set False if memory sampling is not supported due to OpenOCD
+    # limitation/hardware support.
+    support_memory_sampling = True
+
+    # Relative path to a FreeRTOS binary compiled from the spike demo project
+    # in https://github.com/FreeRTOS/FreeRTOS.
+    freertos_binary = None
+
     # Internal variables:
     directory = None
     temporary_files = []
@@ -102,6 +137,7 @@
         self.server_cmd = parsed.server_cmd
         self.sim_cmd = parsed.sim_cmd
         self.temporary_binary = None
+        self.compiler_supports_v = True
         Target.isolate = parsed.isolate
         if not self.name:
             self.name = type(self).__name__
@@ -125,17 +161,18 @@
     def create(self):
         """Create the target out of thin air, eg. start a simulator."""
 
-    def server(self):
+    def server(self, test):
         """Start the debug server that gdb connects to, eg. OpenOCD."""
         return testlib.Openocd(server_cmd=self.server_cmd,
                 config=self.openocd_config_path,
-                timeout=self.server_timeout_sec)
+                timeout=self.server_timeout_sec,
+                freertos=test.freertos())
 
-    def compile(self, hart, *sources):
-        binary_name = "%s_%s-%d" % (
+    def do_compile(self, hart, *sources):
+        binary_name = "%s_%s-%x" % (
                 self.name,
                 os.path.basename(os.path.splitext(sources[0])[0]),
-                hart.xlen)
+                hart.misa)
         if Target.isolate:
             self.temporary_binary = tempfile.NamedTemporaryFile(
                     prefix=binary_name + "_")
@@ -161,6 +198,8 @@
             for letter in "fdc":
                 if hart.extensionSupported(letter):
                     march += letter
+            if hart.extensionSupported("v") and self.compiler_supports_v:
+                march += "v"
             args.append("-march=%s" % march)
             if hart.xlen == 32:
                 args.append("-mabi=ilp32")
@@ -170,6 +209,24 @@
         testlib.compile(args)
         return binary_name
 
+    def compile(self, hart, *sources):
+        for _ in range(2):
+            try:
+                return self.do_compile(hart, *sources)
+            except testlib.CompileError as e:
+                # If the compiler doesn't support V, disable it from the
+                # current configuration. Eventually all gcc branches will
+                # support V, but we're not there yet.
+                m = re.search(r"Error: cannot find default versions of the "
+                        r"ISA extension `(\w)'", e.stderr.decode())
+                if m and m.group(1) in "v":
+                    extension = m.group(1)
+                    print("Disabling extension %r because the "
+                            "compiler doesn't support it." % extension)
+                    self.compiler_supports_v = False
+                else:
+                    raise
+
 def add_target_options(parser):
     parser.add_argument("target", help=".py file that contains definition for "
             "the target to test with.")
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-1.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-1.cfg
index d1ed60e..5f11b08 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike-1.cfg
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-1.cfg
@@ -8,10 +8,13 @@
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+if {$::env(USE_FREERTOS)} {
+    target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos FreeRTOS
+} else {
+    target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+}
 $_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
 
-
 gdb_report_data_abort enable
 gdb_report_register_access_error enable
 
@@ -26,3 +29,5 @@
 riscv authdata_write [expr $challenge + 1]
 
 halt
+
+arm semihosting enable
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg
index 31a5f68..c378a45 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg
@@ -11,7 +11,6 @@
 set _TARGETNAME_0 $_CHIPNAME.cpu0
 set _TARGETNAME_1 $_CHIPNAME.cpu1
 target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread
-#target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
 target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 target smp $_TARGETNAME_0 $_TARGETNAME_1
 
@@ -20,8 +19,11 @@
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.
-riscv expose_csrs 2288
-riscv expose_custom 1,12345-12348
+foreach t [target names] {
+    targets $t
+    riscv expose_csrs 2288
+    riscv expose_custom 1,12345-12348
+}
 
 init
 
@@ -29,3 +31,8 @@
 riscv authdata_write [expr $challenge + 1]
 
 halt
+
+foreach t [target names] {
+    targets $t
+    arm semihosting enable
+}
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-2.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-2.cfg
index c9de7d2..640fba9 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike-2.cfg
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-2.cfg
@@ -18,15 +18,19 @@
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.
-riscv expose_csrs 2288
-riscv expose_custom 1,12345-12348
+foreach t [target names] {
+    targets $t
+    riscv expose_csrs 2288
+    riscv expose_custom 1,12345-12348
+}
 
 init
 
 set challenge [riscv authdata_read]
 riscv authdata_write [expr $challenge + 1]
 
-targets $_TARGETNAME_0
-halt
-targets $_TARGETNAME_1
-halt
+foreach t [target names] {
+    targets $t
+    halt
+    arm semihosting enable
+}
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-multi.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-multi.cfg
new file mode 100644
index 0000000..ef6dfc6
--- /dev/null
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-multi.cfg
@@ -0,0 +1,46 @@
+# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+jtag newtap riscv.0 cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap riscv.1 cpu -irlen 5 -expected-id 0x10e31913
+
+target create riscv.0.cpu0 riscv -chain-position riscv.0.cpu -coreid 0
+target create riscv.0.cpu1 riscv -chain-position riscv.0.cpu -coreid 1
+target create riscv.1.cpu0 riscv -chain-position riscv.1.cpu -coreid 0
+target create riscv.1.cpu1 riscv -chain-position riscv.1.cpu -coreid 1
+
+riscv.0.cpu0 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+riscv.0.cpu1 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+riscv.1.cpu0 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+riscv.1.cpu1 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+foreach t [target names] {
+    targets $t
+    riscv expose_csrs 2288
+    riscv expose_custom 1,12345-12348
+}
+
+init
+
+targets riscv.0.cpu0
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+targets riscv.1.cpu0
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+foreach t [target names] {
+    targets $t
+    halt
+    arm semihosting enable
+}
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-multi.py b/src/riscv-tests/debug/targets/RISC-V/spike-multi.py
new file mode 100644
index 0000000..82de76f
--- /dev/null
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-multi.py
@@ -0,0 +1,31 @@
+import targets
+import testlib
+
+import spike32  # pylint: disable=import-error
+import spike64  # pylint: disable=import-error
+
+class multispike(targets.Target):
+    harts = [
+        spike32.spike32_hart(misa=0x4034112d, system=0),
+        spike32.spike32_hart(misa=0x4034112d, system=0),
+        spike64.spike64_hart(misa=0x8000000000341129, system=1),
+        spike64.spike64_hart(misa=0x8000000000341129, system=1)]
+    openocd_config_path = "spike-multi.cfg"
+    # Increased timeout because we use abstract_rti to artificially slow things
+    # down.
+    timeout_sec = 30
+    implements_custom_test = True
+    support_hasel = False
+    support_memory_sampling = False # Needs SBA
+
+    def create(self):
+        return testlib.MultiSpike(
+            [
+                testlib.Spike(self, isa="RV64IMAFDV",
+                    support_hasel=False, support_abstract_csr=False,
+                    vlen=512, elen=64, harts=self.harts[2:]),
+                testlib.Spike(self, isa="RV32IMAFDCV",
+                    support_abstract_csr=True, support_haltgroups=False,
+                    # elen must be at least 64 because D is supported.
+                    elen=64, harts=self.harts[:2]),
+                ])
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg
deleted file mode 100644
index 7cd1c3f..0000000
--- a/src/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
-adapter_khz     10000
-
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-# Expose an unimplemented CSR so we can test non-existent register access
-# behavior.
-riscv expose_csrs 2288
-riscv expose_custom 1,12345-12348
-
-init
-
-set challenge [riscv authdata_read]
-riscv authdata_write [expr $challenge + 1]
-
-halt
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py b/src/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py
index 2ad2998..e84391a 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py
@@ -9,6 +9,7 @@
     openocd_config_path = "spike-2-hwthread.cfg"
     timeout_sec = 5
     implements_custom_test = True
+    support_memory_sampling = False # not supported without sba
 
     def create(self):
         return testlib.Spike(self, isa="RV32IMAV", support_hasel=True,
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py b/src/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py
deleted file mode 100644
index 8872739..0000000
--- a/src/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py
+++ /dev/null
@@ -1,17 +0,0 @@
-import targets
-import testlib
-
-import spike32  # pylint: disable=import-error
-
-class spike32_2(targets.Target):
-    harts = [spike32.spike32_hart(misa=0x40141129),
-            spike32.spike32_hart(misa=0x40141129)]
-    openocd_config_path = "spike-rtos.cfg"
-    timeout_sec = 30
-    implements_custom_test = True
-    support_hasel = False
-
-    def create(self):
-        return testlib.Spike(self, progbufsize=0, dmi_rti=4,
-                support_hasel=False, support_abstract_csr=True,
-                support_haltgroups=False)
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike32.py b/src/riscv-tests/debug/targets/RISC-V/spike32.py
index b261f6c..17d28fb 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike32.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike32.py
@@ -5,18 +5,18 @@
     xlen = 32
     ram = 0x10000000
     ram_size = 0x10000000
+    bad_address = ram - 8
     instruction_hardware_breakpoint_count = 4
     reset_vectors = [0x1000]
     link_script_path = "spike32.lds"
 
-    def __init__(self, misa):
-        self.misa = misa
-
 class spike32(targets.Target):
     harts = [spike32_hart(misa=0x4034112d)]
     openocd_config_path = "spike-1.cfg"
     timeout_sec = 30
     implements_custom_test = True
+    support_memory_sampling = False # Needs SBA
+    freertos_binary = "bin/RTOSDemo32.axf"
 
     def create(self):
         # 64-bit FPRs on 32-bit target
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py b/src/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py
index 5d8d6e6..db381d4 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py
@@ -4,11 +4,17 @@
 import spike64  # pylint: disable=import-error
 
 class spike64_2(targets.Target):
-    harts = [spike64.spike64_hart(misa=0x8000000000141129),
-            spike64.spike64_hart(misa=0x8000000000141129)]
+    harts = [spike64.spike64_hart(misa=0x8000000000341129),
+            spike64.spike64_hart(misa=0x8000000000341129)]
     openocd_config_path = "spike-2-hwthread.cfg"
-    timeout_sec = 5
+    # Increased timeout because we use abstract_rti to artificially slow things
+    # down.
+    timeout_sec = 20
     implements_custom_test = True
+    support_hasel = False
+    support_memory_sampling = False # Needs SBA
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30,
+                support_hasel=False, support_abstract_csr=False,
+                vlen=512, elen=64)
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py b/src/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py
index db6263a..acb217f 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py
@@ -10,6 +10,9 @@
     timeout_sec = 60
     implements_custom_test = True
     support_hasel = False
+    test_semihosting = False
+    support_manual_hwbp = False # not supported with `-rtos riscv`
+    support_memory_sampling = False # not supported with `-rtos riscv`
 
     def create(self):
         return testlib.Spike(self, abstract_rti=30, support_hasel=False,
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike64-2.py b/src/riscv-tests/debug/targets/RISC-V/spike64-2.py
index 5ace23b..e710fe1 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike64-2.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike64-2.py
@@ -4,16 +4,12 @@
 import spike64  # pylint: disable=import-error
 
 class spike64_2(targets.Target):
-    harts = [spike64.spike64_hart(misa=0x8000000000341129),
-            spike64.spike64_hart(misa=0x8000000000341129)]
+    harts = [spike64.spike64_hart(misa=0x8000000000141129),
+            spike64.spike64_hart(misa=0x8000000000141129)]
     openocd_config_path = "spike-2.cfg"
-    # Increased timeout because we use abstract_rti to artificially slow things
-    # down.
-    timeout_sec = 20
+    timeout_sec = 5
     implements_custom_test = True
-    support_hasel = False
+    support_memory_sampling = False # Needs SBA
 
     def create(self):
-        return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30,
-                support_hasel=False, support_abstract_csr=False,
-                vlen=512, elen=64)
+        return testlib.Spike(self)
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike64.py b/src/riscv-tests/debug/targets/RISC-V/spike64.py
index ec43a11..31088ff 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike64.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike64.py
@@ -5,18 +5,18 @@
     xlen = 64
     ram = 0x1212340000
     ram_size = 0x10000000
+    bad_address = ram - 8
     instruction_hardware_breakpoint_count = 4
     reset_vectors = [0x1000]
     link_script_path = "spike64.lds"
-
-    def __init__(self, misa=0x8000000000141125):
-        self.misa = misa
+    misa = 0x8000000000141125
 
 class spike64(targets.Target):
     harts = [spike64_hart()]
     openocd_config_path = "spike-1.cfg"
     timeout_sec = 30
     implements_custom_test = True
+    freertos_binary = "bin/RTOSDemo64.axf"
 
     def create(self):
         # 32-bit FPRs only
diff --git a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py
index cb2741e..947d061 100644
--- a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py
+++ b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py
@@ -4,6 +4,7 @@
     xlen = 64
     ram = 0x80000000
     ram_size = 1024 * 1024
+    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
     instruction_hardware_breakpoint_count = 2
     link_script_path = "HiFiveUnleashed-flash.lds"
     reset_vectors = [0x1004]
@@ -12,6 +13,7 @@
     xlen = 64
     ram = 0x80000000
     ram_size = 1024 * 1024
+    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
     instruction_hardware_breakpoint_count = 2
     link_script_path = "HiFiveUnleashed-flash.lds"
     reset_vectors = [0x1004]
@@ -19,4 +21,5 @@
 class HiFiveUnleashedFlash(targets.Target):
     support_hasel = False
     harts = [E51(), U54(), U54(), U54(), U54()]
+    support_memory_sampling = False # Needs SBA
     openocd_config_path = "HiFiveUnleashed.cfg"
diff --git a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg
index 3aa5538..3d20be0 100644
--- a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg
+++ b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg
@@ -55,6 +55,7 @@
 foreach t [target names] {
     targets $t
     reg pc 0x08000000
+    arm semihosting enable
 }
 resume
 wait_halt
diff --git a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py
index 9bf7cae..04f6cef 100644
--- a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py
+++ b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py
@@ -4,6 +4,7 @@
     xlen = 64
     ram = 0x80000000
     ram_size = 1024 * 1024
+    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
     instruction_hardware_breakpoint_count = 2
     reset_vectors = [0x1004]
     misa = 0x8000000000101105
@@ -12,10 +13,12 @@
     xlen = 64
     ram = 0x80000000
     ram_size = 1024 * 1024
+    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
     instruction_hardware_breakpoint_count = 2
     reset_vectors = [0x1004]
     misa = 0x800000000014112d
 
 class HiFiveUnleashed(targets.Target):
     support_hasel = False
+    support_memory_sampling = False # Needs SBA
     harts = [E51(), U54(), U54(), U54(), U54()]
diff --git a/src/riscv-tests/debug/testlib.py b/src/riscv-tests/debug/testlib.py
index 36f1f17..b97b607 100644
--- a/src/riscv-tests/debug/testlib.py
+++ b/src/riscv-tests/debug/testlib.py
@@ -29,8 +29,19 @@
             return relpath
     return None
 
+class CompileError(Exception):
+    def __init__(self, stdout, stderr):
+        super().__init__()
+        self.stdout = stdout
+        self.stderr = stderr
+
+gcc_cmd = None
 def compile(args): # pylint: disable=redefined-builtin
-    cmd = ["riscv64-unknown-elf-gcc", "-g"]
+    if gcc_cmd:
+        cmd = [gcc_cmd]
+    else:
+        cmd = ["riscv64-unknown-elf-gcc"]
+    cmd.append("-g")
     for arg in args:
         found = find_file(arg)
         if found:
@@ -43,10 +54,10 @@
                                stderr=subprocess.PIPE)
     stdout, stderr = process.communicate()
     if process.returncode:
-        print(stdout, end=" ")
-        print(stderr, end=" ")
+        print(stdout.decode('ascii'), end=" ")
+        print(stderr.decode('ascii'), end=" ")
         header("")
-        raise Exception("Compile failed!")
+        raise CompileError(stdout, stderr)
 
 class Spike:
     # pylint: disable=too-many-instance-attributes
@@ -54,7 +65,7 @@
     def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
             isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None,
             support_hasel=True, support_abstract_csr=True,
-            support_haltgroups=True, vlen=128, elen=64, slen=128):
+            support_haltgroups=True, vlen=128, elen=64, harts=None):
         """Launch spike. Return tuple of its process and the port it's running
         on."""
         self.process = None
@@ -67,23 +78,20 @@
         self.support_haltgroups = support_haltgroups
         self.vlen = vlen
         self.elen = elen
-        self.slen = slen
 
-        if target.harts:
-            harts = target.harts
-        else:
-            harts = [target]
+        self.harts = harts or target.harts or [target]
 
-        cmd = self.command(target, harts, halted, timeout, with_jtag_gdb)
-        self.infinite_loop = target.compile(harts[0],
+        cmd = self.command(target, halted, timeout, with_jtag_gdb)
+        self.infinite_loop = target.compile(self.harts[0],
                 "programs/checksum.c", "programs/tiny-malloc.c",
                 "programs/infinite_loop.S", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
         cmd.append(self.infinite_loop)
         self.logfile = tempfile.NamedTemporaryFile(prefix="spike-",
                 suffix=".log")
-        self.logname = self.logfile.name
+        logname = self.logfile.name
+        self.lognames = [logname]
         if print_log_names:
-            real_stdout.write("Temporary spike log: %s\n" % self.logname)
+            real_stdout.write("Temporary spike log: %s\n" % logname)
         self.logfile.write(("+ %s\n" % " ".join(cmd)).encode())
         self.logfile.flush()
         self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
@@ -93,41 +101,41 @@
             self.port = None
             for _ in range(30):
                 m = re.search(r"Listening for remote bitbang connection on "
-                        r"port (\d+).", open(self.logname).read())
+                        r"port (\d+).", open(logname).read())
                 if m:
                     self.port = int(m.group(1))
                     os.environ['REMOTE_BITBANG_PORT'] = m.group(1)
                     break
                 time.sleep(0.11)
             if not self.port:
-                print_log(self.logname)
+                print_log(logname)
                 raise Exception("Didn't get spike message about bitbang "
                         "connection")
 
     # pylint: disable=too-many-branches
-    def command(self, target, harts, halted, timeout, with_jtag_gdb):
+    def command(self, target, halted, timeout, with_jtag_gdb):
         # pylint: disable=no-self-use
         if target.sim_cmd:
             cmd = shlex.split(target.sim_cmd)
         else:
             cmd = ["spike"]
 
-        cmd += ["-p%d" % len(harts)]
+        cmd += ["-p%d" % len(self.harts)]
 
-        assert len(set(t.xlen for t in harts)) == 1, \
+        assert len(set(t.xlen for t in self.harts)) == 1, \
                 "All spike harts must have the same XLEN"
 
         if self.isa:
             isa = self.isa
         else:
-            isa = "RV%dG" % harts[0].xlen
+            isa = "RV%dG" % self.harts[0].xlen
 
         cmd += ["--isa", isa]
         cmd += ["--dm-auth"]
 
         if not self.progbufsize is None:
             cmd += ["--dm-progsize", str(self.progbufsize)]
-            cmd += ["--dm-sba", "32"]
+            cmd += ["--dm-sba", "64"]
 
         if not self.dmi_rti is None:
             cmd += ["--dmi-rti", str(self.dmi_rti)]
@@ -145,15 +153,14 @@
             cmd.append("--dm-no-halt-groups")
 
         if 'V' in isa[2:]:
-            cmd.append("--varch=vlen:%d,elen:%d,slen:%d" % (self.vlen,
-                self.elen, self.slen))
+            cmd.append("--varch=vlen:%d,elen:%d" % (self.vlen, self.elen))
 
-        assert len(set(t.ram for t in harts)) == 1, \
+        assert len(set(t.ram for t in self.harts)) == 1, \
                 "All spike harts must have the same RAM layout"
-        assert len(set(t.ram_size for t in harts)) == 1, \
+        assert len(set(t.ram_size for t in self.harts)) == 1, \
                 "All spike harts must have the same RAM layout"
-        os.environ['WORK_AREA'] = '0x%x' % harts[0].ram
-        cmd += ["-m0x%x:0x%x" % (harts[0].ram, harts[0].ram_size)]
+        os.environ['WORK_AREA'] = '0x%x' % self.harts[0].ram
+        cmd += ["-m0x%x:0x%x" % (self.harts[0].ram, self.harts[0].ram_size)]
 
         if timeout:
             cmd = ["timeout", str(timeout)] + cmd
@@ -177,6 +184,48 @@
     def wait(self, *args, **kwargs):
         return self.process.wait(*args, **kwargs)
 
+class MultiSpike:
+    def __init__(self, spikes):
+        self.process = None
+
+        self.spikes = spikes
+        self.lognames = sum((spike.lognames for spike in spikes), [])
+        self.logfile = tempfile.NamedTemporaryFile(prefix="daisychain-",
+                suffix=".log")
+        self.lognames.append(self.logfile.name)
+
+        # Now create the daisy-chain process.
+        cmd = ["./rbb_daisychain.py", "0"] + \
+            [str(spike.port) for spike in spikes]
+        self.logfile.write(("+ %s\n" % cmd).encode())
+        self.logfile.flush()
+        self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
+                stdout=self.logfile, stderr=self.logfile)
+
+        self.port = None
+        for _ in range(30):
+            m = re.search(r"Listening on port (\d+).",
+                          open(self.lognames[-1]).read())
+            if m:
+                self.port = int(m.group(1))
+                break
+            time.sleep(0.11)
+        if not self.port:
+            print_log(self.lognames[-1])
+            raise Exception("Didn't get daisy chain message about which port "
+                            "it's listening on.")
+
+        os.environ['REMOTE_BITBANG_HOST'] = 'localhost'
+        os.environ['REMOTE_BITBANG_PORT'] = str(self.port)
+
+    def __del__(self):
+        if self.process:
+            try:
+                self.process.kill()
+                self.process.wait()
+            except OSError:
+                pass
+
 class VcsSim:
     logfile = tempfile.NamedTemporaryFile(prefix='simv', suffix='.log')
     logname = logfile.name
@@ -234,7 +283,8 @@
     logfile = tempfile.NamedTemporaryFile(prefix='openocd', suffix='.log')
     logname = logfile.name
 
-    def __init__(self, server_cmd=None, config=None, debug=False, timeout=60):
+    def __init__(self, server_cmd=None, config=None, debug=False, timeout=60,
+                 freertos=False):
         self.timeout = timeout
 
         if server_cmd:
@@ -263,12 +313,18 @@
             self.config_file = find_file(config)
             if self.config_file is None:
                 print("Unable to read file", config)
-                exit(1)
+                sys.exit(1)
 
             cmd += ["-f", self.config_file]
         if debug:
             cmd.append("-d")
 
+        extra_env = {}
+        if freertos:
+            extra_env['USE_FREERTOS'] = "1"
+        else:
+            extra_env['USE_FREERTOS'] = "0"
+
         raw_logfile = open(Openocd.logname, "wb")
         try:
             spike_dasm = subprocess.Popen("spike-dasm", stdin=subprocess.PIPE,
@@ -281,17 +337,21 @@
         env_entries = ("REMOTE_BITBANG_HOST", "REMOTE_BITBANG_PORT",
                 "WORK_AREA")
         env_entries = [key for key in env_entries if key in os.environ]
-        logfile.write(("+ %s%s\n" % (
-            "".join("%s=%s " % (key, os.environ[key]) for key in env_entries),
-            " ".join(map(pipes.quote, cmd)))).encode())
+        parts = [
+            " ".join("%s=%s" % (key, os.environ[key]) for key in env_entries),
+            " ".join("%s=%s" % (k, v) for k, v in extra_env.items()),
+            " ".join(map(pipes.quote, cmd))
+        ]
+        logfile.write(("+ %s\n" % " ".join(parts)).encode())
         logfile.flush()
 
         self.gdb_ports = []
-        self.process = self.start(cmd, logfile)
+        self.process = self.start(cmd, logfile, extra_env)
 
-    def start(self, cmd, logfile):
+    def start(self, cmd, logfile, extra_env):
+        combined_env = {**os.environ, **extra_env}
         process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
-                stdout=logfile, stderr=logfile)
+                stdout=logfile, stderr=logfile, env=combined_env)
 
         try:
             # Wait for OpenOCD to have made it through riscv_examine(). When
@@ -379,6 +439,11 @@
         Exception.__init__(self)
         self.address = address
 
+class CannotInsertBreakpoint(Exception):
+    def __init__(self, number):
+        Exception.__init__(self)
+        self.number = number
+
 class CouldNotFetch(Exception):
     def __init__(self, regname, explanation):
         Exception.__init__(self)
@@ -390,6 +455,9 @@
         Exception.__init__(self)
         self.symbol = symbol
 
+    def __repr__(self):
+        return "NoSymbol(%r)" % self.symbol
+
 Thread = collections.namedtuple('Thread', ('id', 'description', 'target_id',
     'name', 'frame'))
 
@@ -412,6 +480,8 @@
                     lambda m: CouldNotFetch(m.group(1), m.group(2))),
                 (r"Cannot access memory at address (0x[0-9a-f]+)",
                     lambda m: CannotAccess(int(m.group(1), 0))),
+                (r"Cannot insert breakpoint (\d+).",
+                    lambda m: CannotInsertBreakpoint(int(m.group(1)))),
                 (r'No symbol "(\w+)" in current context.',
                     lambda m: NoSymbol(m.group(1))),
                 (r'"([^"]*)"', lambda m: m.group(1)),
@@ -490,15 +560,14 @@
             11, 149, 107, 163, 73, 47, 43, 173, 7, 109, 101, 103, 191, 2, 139,
             97, 193, 157, 3, 29, 79, 113, 5, 89, 19, 37, 71, 179, 59, 137, 53)
 
-    def __init__(self, ports,
-            cmd="riscv64-unknown-elf-gdb",
-            timeout=60, binary=None):
+    def __init__(self, target, ports, cmd=None, timeout=60, binaries=None):
         assert ports
 
+        self.target = target
         self.ports = ports
-        self.cmd = cmd
+        self.cmd = cmd or "riscv64-unknown-elf-gdb"
         self.timeout = timeout
-        self.binary = binary
+        self.binaries = binaries or [None] * len(ports)
 
         self.reset_delay_index = 0
         self.stack = []
@@ -512,26 +581,30 @@
             self.logfiles.append(logfile)
             if print_log_names:
                 real_stdout.write("Temporary gdb log: %s\n" % logfile.name)
-            child = pexpect.spawn(cmd)
+            child = pexpect.spawn(self.cmd)
             child.logfile = logfile
-            child.logfile.write(("+ %s\n" % cmd).encode())
+            child.logfile.write(("+ %s\n" % self.cmd).encode())
             self.children.append(child)
         self.active_child = self.children[0]
 
     def connect(self):
-        for port, child in zip(self.ports, self.children):
+        for port, child, binary in zip(self.ports, self.children,
+                                       self.binaries):
             self.select_child(child)
             self.wait()
-            self.command("set style enabled off")
-            self.command("set confirm off")
-            self.command("set width 0")
-            self.command("set height 0")
+            self.command("set style enabled off", reset_delays=None)
+            self.command("set confirm off", reset_delays=None)
+            self.command("set width 0", reset_delays=None)
+            self.command("set height 0", reset_delays=None)
             # Force consistency.
-            self.command("set print entry-values no")
-            self.command("set remotetimeout %d" % self.timeout)
-            self.command("target extended-remote localhost:%d" % port, ops=10)
-            if self.binary:
-                self.command("file %s" % self.binary)
+            self.command("set print entry-values no", reset_delays=None)
+            self.command("set remotetimeout %d" % self.timeout,
+                         reset_delays=None)
+            self.command("target extended-remote localhost:%d" % port, ops=10,
+                         reset_delays=None)
+            if binary:
+                output = self.command("file %s" % binary)
+                assertIn("Reading symbols", output)
             threads = self.threads()
             for t in threads:
                 hartid = None
@@ -593,11 +666,11 @@
                         len(self.reset_delays)
             self.command("monitor riscv reset_delays %d" % reset_delays,
                     reset_delays=None)
-        timeout = ops * self.timeout
+        timeout = max(1, ops) * self.timeout
         self.active_child.sendline(command)
         self.active_child.expect("\n", timeout=timeout)
         self.active_child.expect(r"\(gdb\)", timeout=timeout)
-        return self.active_child.before.strip().decode("utf-8")
+        return self.active_child.before.strip().decode("utf-8", errors="ignore")
 
     def global_command(self, command):
         """Execute this command on every gdb that we control."""
@@ -606,6 +679,20 @@
                 self.select_child(child)
                 self.command(command)
 
+    def system_command(self, command, ops=20):
+        """Execute this command on every unique system that we control."""
+        done = set()
+        output = ""
+        with PrivateState(self):
+            for i, child in enumerate(self.children):
+                self.select_child(child)
+                if self.target.harts[i].system in done:
+                    self.command("set $pc=_start")
+                else:
+                    output += self.command(command, ops=ops)
+                    done.add(self.target.harts[i].system)
+        return output
+
     def c(self, wait=True, sync=True, checkOutput=True, ops=20):
         """
         Dumb c command.
@@ -659,10 +746,16 @@
             self.select_child(child)
             self.interrupt()
 
-    def x(self, address, size='w'):
-        output = self.command("x/%s %s" % (size, address))
-        value = int(output.split(':')[1].strip(), 0)
-        return value
+    def x(self, address, size='w', count=1):
+        output = self.command("x/%d%s %s" % (count, size, address),
+                              ops=count / 16)
+        values = []
+        for line in output.splitlines():
+            for value in line.split(':')[1].strip().split():
+                values.append(int(value, 0))
+        if len(values) == 1:
+            return values[0]
+        return values
 
     def p_raw(self, obj):
         output = self.command("p %s" % obj)
@@ -687,8 +780,8 @@
         value = shlex.split(output.split('=')[-1].strip())[1]
         return value
 
-    def info_registers(self, group):
-        output = self.command("info registers %s" % group, ops=5)
+    def info_registers(self, group="", ops=5):
+        output = self.command("info registers %s" % group, ops=ops)
         result = {}
         for line in output.splitlines():
             m = re.match(r"(\w+)\s+({.*})(?:\s+(\(.*\)))?", line)
@@ -708,10 +801,10 @@
         return output
 
     def load(self):
-        output = self.command("load", ops=1000)
+        output = self.system_command("load", ops=1000)
         assert "failed" not in  output
         assert "Transfer rate" in output
-        output = self.command("compare-sections", ops=1000)
+        output = self.system_command("compare-sections", ops=1000)
         assert "matched" in output
         assert "MIS" not in output
 
@@ -755,8 +848,6 @@
             if m:
                 threads.append(Thread(*m.groups()))
         assert threads
-        #>>>if not threads:
-        #>>>    threads.append(Thread('1', '1', 'Default', '???'))
         return threads
 
     def thread(self, thread):
@@ -799,6 +890,8 @@
 
     global gdb_cmd  # pylint: disable=global-statement
     gdb_cmd = parsed.gdb
+    global gcc_cmd  # pylint: disable=global-statement
+    gcc_cmd = parsed.gcc
 
     examine_added = False
     for hart in target.harts:
@@ -882,6 +975,8 @@
             help="Print out a list of tests, and exit immediately.")
     parser.add_argument("test", nargs='*',
             help="Run only tests that are named here.")
+    parser.add_argument("--gcc",
+            help="The command to use to start gcc.")
     parser.add_argument("--gdb",
             help="The command to use to start gdb.")
     parser.add_argument("--misaval",
@@ -904,9 +999,10 @@
     print()
 
 def print_log(path):
-    print_log_handle(path, open(path, "r"))
+    print_log_handle(path, open(path, "r", errors='ignore'))
 
 class BaseTest:
+    # pylint: disable=too-many-instance-attributes
     compiled = {}
 
     def __init__(self, target, hart=None):
@@ -920,6 +1016,7 @@
         self.binary = None
         self.start = 0
         self.logs = []
+        self.binaries = []
 
     def early_applicable(self):
         """Return a false value if the test has determined it cannot run
@@ -927,24 +1024,33 @@
         # pylint: disable=no-self-use
         return True
 
+    def freertos(self):
+        """Return a true value if the test is running a FreeRTOS binary where
+        the debugger should expose FreeRTOS threads to gdb."""
+        # pylint: disable=no-self-use
+        return False
+
     def setup(self):
         pass
 
     def compile(self):
         compile_args = getattr(self, 'compile_args', None)
+        self.binaries = []
         if compile_args:
-            if compile_args not in BaseTest.compiled:
-                BaseTest.compiled[compile_args] = \
-                        self.target.compile(self.hart, *compile_args)
-        self.binary = BaseTest.compiled.get(compile_args)
+            for hart in self.target.harts:
+                key = (compile_args, hart.misa)
+                if key not in BaseTest.compiled:
+                    BaseTest.compiled[key] = \
+                            self.target.compile(hart, *compile_args)
+                self.binaries.append(BaseTest.compiled.get(key))
 
     def classSetup(self):
         self.compile()
         self.target_process = self.target.create()
         if self.target_process:
-            self.logs.append(self.target_process.logname)
+            self.logs += self.target_process.lognames
         try:
-            self.server = self.target.server()
+            self.server = self.target.server(self)
             self.logs.append(self.server.logname)
         except Exception:
             for log in self.logs:
@@ -960,7 +1066,7 @@
 
     def run(self):
         """
-        If compile_args is set, compile a program and set self.binary.
+        If compile_args is set, compile a program and set self.binaries.
 
         Call setup().
 
@@ -1005,7 +1111,7 @@
             # Get handles to logs before the files are deleted.
             logs = []
             for log in self.logs:
-                logs.append((log, open(log, "r")))
+                logs.append((log, open(log, "r", errors='ignore')))
 
             self.classTeardown()
             for name, handle in logs:
@@ -1031,12 +1137,8 @@
     def classSetup(self):
         BaseTest.classSetup(self)
 
-        if gdb_cmd:
-            self.gdb = Gdb(self.server.gdb_ports, gdb_cmd,
-                    timeout=self.target.timeout_sec, binary=self.binary)
-        else:
-            self.gdb = Gdb(self.server.gdb_ports,
-                    timeout=self.target.timeout_sec, binary=self.binary)
+        self.gdb = Gdb(self.target, self.server.gdb_ports, cmd=gdb_cmd,
+                       timeout=self.target.timeout_sec, binaries=self.binaries)
 
         self.logs += self.gdb.lognames()
         self.gdb.connect()
diff --git a/src/riscv-tests/env/encoding.h b/src/riscv-tests/env/encoding.h
index c109ce1..2aa895b 100644
--- a/src/riscv-tests/env/encoding.h
+++ b/src/riscv-tests/env/encoding.h
@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+/* See LICENSE for license details. */
 
 #ifndef RISCV_CSR_ENCODING_H
 #define RISCV_CSR_ENCODING_H
@@ -12,7 +12,7 @@
 #define MSTATUS_HPIE        0x00000040
 #define MSTATUS_MPIE        0x00000080
 #define MSTATUS_SPP         0x00000100
-#define MSTATUS_HPP         0x00000600
+#define MSTATUS_VS          0x00000600
 #define MSTATUS_MPP         0x00001800
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
@@ -32,6 +32,7 @@
 #define SSTATUS_UPIE        0x00000010
 #define SSTATUS_SPIE        0x00000020
 #define SSTATUS_SPP         0x00000100
+#define SSTATUS_VS          0x00000600
 #define SSTATUS_FS          0x00006000
 #define SSTATUS_XS          0x00018000
 #define SSTATUS_SUM         0x00040000
@@ -40,6 +41,9 @@
 #define SSTATUS_UXL         0x0000000300000000
 #define SSTATUS64_SD        0x8000000000000000
 
+#define USTATUS_UIE         0x00000001
+#define USTATUS_UPIE        0x00000010
+
 #define DCSR_XDEBUGVER      (3U<<30)
 #define DCSR_NDRESET        (1<<29)
 #define DCSR_FULLRESET      (1<<28)
@@ -95,12 +99,15 @@
 #define MCONTROL_MATCH_MASK_LOW  4
 #define MCONTROL_MATCH_MASK_HIGH 5
 
+#define MIP_USIP            (1 << IRQ_U_SOFT)
 #define MIP_SSIP            (1 << IRQ_S_SOFT)
 #define MIP_HSIP            (1 << IRQ_H_SOFT)
 #define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_UTIP            (1 << IRQ_U_TIMER)
 #define MIP_STIP            (1 << IRQ_S_TIMER)
 #define MIP_HTIP            (1 << IRQ_H_TIMER)
 #define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_UEIP            (1 << IRQ_U_EXT)
 #define MIP_SEIP            (1 << IRQ_S_EXT)
 #define MIP_HEIP            (1 << IRQ_H_EXT)
 #define MIP_MEIP            (1 << IRQ_M_EXT)
@@ -138,12 +145,15 @@
 #define PMP_NA4   0x10
 #define PMP_NAPOT 0x18
 
+#define IRQ_U_SOFT   0
 #define IRQ_S_SOFT   1
 #define IRQ_H_SOFT   2
 #define IRQ_M_SOFT   3
+#define IRQ_U_TIMER  4
 #define IRQ_S_TIMER  5
 #define IRQ_H_TIMER  6
 #define IRQ_M_TIMER  7
+#define IRQ_U_EXT    8
 #define IRQ_S_EXT    9
 #define IRQ_H_EXT    10
 #define IRQ_M_EXT    11
@@ -156,16 +166,20 @@
 #define EXT_IO_BASE        0x40000000
 #define DRAM_BASE          0x80000000
 
-// page table entry (PTE) fields
-#define PTE_V     0x001 // Valid
-#define PTE_R     0x002 // Read
-#define PTE_W     0x004 // Write
-#define PTE_X     0x008 // Execute
-#define PTE_U     0x010 // User
-#define PTE_G     0x020 // Global
-#define PTE_A     0x040 // Accessed
-#define PTE_D     0x080 // Dirty
-#define PTE_SOFT  0x300 // Reserved for Software
+/* page table entry (PTE) fields */
+#define PTE_V     0x001 /* Valid */
+#define PTE_R     0x002 /* Read */
+#define PTE_W     0x004 /* Write */
+#define PTE_X     0x008 /* Execute */
+#define PTE_U     0x010 /* User */
+#define PTE_G     0x020 /* Global */
+#define PTE_A     0x040 /* Accessed */
+#define PTE_D     0x080 /* Dirty */
+#define PTE_SOFT  0x300 /* Reserved for Software */
+#define PTE_RSVD  0x1FC0000000000000 /* Reserved for future standard use */
+#define PTE_PBMT  0x6000000000000000 /* Svpbmt: Page-based memory types */
+#define PTE_N     0x8000000000000000 /* Svnapot: NAPOT translation contiguity */
+#define PTE_ATTR  0xFFC0000000000000 /* All attributes and reserved bits */
 
 #define PTE_PPN_SHIFT 10
 
@@ -221,9 +235,55 @@
 #endif
 
 #endif
-/* Automatically generated by parse-opcodes.  */
+/* Automatically generated by parse_opcodes.  */
 #ifndef RISCV_ENCODING_H
 #define RISCV_ENCODING_H
+#define MATCH_SLLI_RV32 0x1013
+#define MASK_SLLI_RV32  0xfe00707f
+#define MATCH_SRLI_RV32 0x5013
+#define MASK_SRLI_RV32  0xfe00707f
+#define MATCH_SRAI_RV32 0x40005013
+#define MASK_SRAI_RV32  0xfe00707f
+#define MATCH_FRFLAGS 0x102073
+#define MASK_FRFLAGS  0xfffff07f
+#define MATCH_FSFLAGS 0x101073
+#define MASK_FSFLAGS  0xfff0707f
+#define MATCH_FSFLAGSI 0x105073
+#define MASK_FSFLAGSI  0xfff0707f
+#define MATCH_FRRM 0x202073
+#define MASK_FRRM  0xfffff07f
+#define MATCH_FSRM 0x201073
+#define MASK_FSRM  0xfff0707f
+#define MATCH_FSRMI 0x205073
+#define MASK_FSRMI  0xfff0707f
+#define MATCH_FSCSR 0x301073
+#define MASK_FSCSR  0xfff0707f
+#define MATCH_FRCSR 0x302073
+#define MASK_FRCSR  0xfffff07f
+#define MATCH_RDCYCLE 0xc0002073
+#define MASK_RDCYCLE  0xfffff07f
+#define MATCH_RDTIME 0xc0102073
+#define MASK_RDTIME  0xfffff07f
+#define MATCH_RDINSTRET 0xc0202073
+#define MASK_RDINSTRET  0xfffff07f
+#define MATCH_RDCYCLEH 0xc8002073
+#define MASK_RDCYCLEH  0xfffff07f
+#define MATCH_RDTIMEH 0xc8102073
+#define MASK_RDTIMEH  0xfffff07f
+#define MATCH_RDINSTRETH 0xc8202073
+#define MASK_RDINSTRETH  0xfffff07f
+#define MATCH_SCALL 0x73
+#define MASK_SCALL  0xffffffff
+#define MATCH_SBREAK 0x100073
+#define MASK_SBREAK  0xffffffff
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S  0xfff0707f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X  0xfff0707f
+#define MATCH_FENCE_TSO 0x8330000f
+#define MASK_FENCE_TSO  0xfff0707f
+#define MATCH_PAUSE 0x100000f
+#define MASK_PAUSE  0xffffffff
 #define MATCH_BEQ 0x63
 #define MASK_BEQ  0x707f
 #define MATCH_BNE 0x1063
@@ -282,6 +342,26 @@
 #define MASK_OR  0xfe00707f
 #define MATCH_AND 0x7033
 #define MASK_AND  0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB  0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH  0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW  0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU  0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU  0x707f
+#define MATCH_SB 0x23
+#define MASK_SB  0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH  0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW  0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE  0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I  0x707f
 #define MATCH_ADDIW 0x1b
 #define MASK_ADDIW  0x707f
 #define MATCH_SLLIW 0x101b
@@ -300,32 +380,12 @@
 #define MASK_SRLW  0xfe00707f
 #define MATCH_SRAW 0x4000503b
 #define MASK_SRAW  0xfe00707f
-#define MATCH_LB 0x3
-#define MASK_LB  0x707f
-#define MATCH_LH 0x1003
-#define MASK_LH  0x707f
-#define MATCH_LW 0x2003
-#define MASK_LW  0x707f
 #define MATCH_LD 0x3003
 #define MASK_LD  0x707f
-#define MATCH_LBU 0x4003
-#define MASK_LBU  0x707f
-#define MATCH_LHU 0x5003
-#define MASK_LHU  0x707f
 #define MATCH_LWU 0x6003
 #define MASK_LWU  0x707f
-#define MATCH_SB 0x23
-#define MASK_SB  0x707f
-#define MATCH_SH 0x1023
-#define MASK_SH  0x707f
-#define MATCH_SW 0x2023
-#define MASK_SW  0x707f
 #define MATCH_SD 0x3023
 #define MASK_SD  0x707f
-#define MATCH_FENCE 0xf
-#define MASK_FENCE  0x707f
-#define MATCH_FENCE_I 0x100f
-#define MASK_FENCE_I  0x707f
 #define MATCH_MUL 0x2000033
 #define MASK_MUL  0xfe00707f
 #define MATCH_MULH 0x2001033
@@ -396,34 +456,6 @@
 #define MASK_LR_D  0xf9f0707f
 #define MATCH_SC_D 0x1800302f
 #define MASK_SC_D  0xf800707f
-#define MATCH_ECALL 0x73
-#define MASK_ECALL  0xffffffff
-#define MATCH_EBREAK 0x100073
-#define MASK_EBREAK  0xffffffff
-#define MATCH_URET 0x200073
-#define MASK_URET  0xffffffff
-#define MATCH_SRET 0x10200073
-#define MASK_SRET  0xffffffff
-#define MATCH_MRET 0x30200073
-#define MASK_MRET  0xffffffff
-#define MATCH_DRET 0x7b200073
-#define MASK_DRET  0xffffffff
-#define MATCH_SFENCE_VMA 0x12000073
-#define MASK_SFENCE_VMA  0xfe007fff
-#define MATCH_WFI 0x10500073
-#define MASK_WFI  0xffffffff
-#define MATCH_CSRRW 0x1073
-#define MASK_CSRRW  0x707f
-#define MATCH_CSRRS 0x2073
-#define MASK_CSRRS  0x707f
-#define MATCH_CSRRC 0x3073
-#define MASK_CSRRC  0x707f
-#define MATCH_CSRRWI 0x5073
-#define MASK_CSRRWI  0x707f
-#define MATCH_CSRRSI 0x6073
-#define MASK_CSRRSI  0x707f
-#define MATCH_CSRRCI 0x7073
-#define MASK_CSRRCI  0x707f
 #define MATCH_FADD_S 0x53
 #define MASK_FADD_S  0xfe00007f
 #define MATCH_FSUB_S 0x8000053
@@ -444,6 +476,46 @@
 #define MASK_FMAX_S  0xfe00707f
 #define MATCH_FSQRT_S 0x58000053
 #define MASK_FSQRT_S  0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S  0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S  0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S  0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S  0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S  0xfff0007f
+#define MATCH_FMV_X_W 0xe0000053
+#define MASK_FMV_X_W  0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S  0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W  0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU  0xfff0007f
+#define MATCH_FMV_W_X 0xf0000053
+#define MASK_FMV_W_X  0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW  0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW  0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S  0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S  0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S  0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S  0x600007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S  0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S  0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L  0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU  0xfff0007f
 #define MATCH_FADD_D 0x2000053
 #define MASK_FADD_D  0xfe00007f
 #define MATCH_FSUB_D 0xa000053
@@ -468,6 +540,46 @@
 #define MASK_FCVT_D_S  0xfff0007f
 #define MATCH_FSQRT_D 0x5a000053
 #define MASK_FSQRT_D  0xfff0007f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D  0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D  0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D  0xfe00707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D  0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D  0xfff0007f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D  0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W  0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU  0xfff0007f
+#define MATCH_FLD 0x3007
+#define MASK_FLD  0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD  0x707f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D  0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D  0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D  0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D  0x600007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D  0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D  0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D  0xfff0707f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L  0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU  0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X  0xfff0707f
 #define MATCH_FADD_Q 0x6000053
 #define MASK_FADD_Q  0xfe00007f
 #define MATCH_FSUB_Q 0xe000053
@@ -496,118 +608,26 @@
 #define MASK_FCVT_Q_D  0xfff0007f
 #define MATCH_FSQRT_Q 0x5e000053
 #define MASK_FSQRT_Q  0xfff0007f
-#define MATCH_FLE_S 0xa0000053
-#define MASK_FLE_S  0xfe00707f
-#define MATCH_FLT_S 0xa0001053
-#define MASK_FLT_S  0xfe00707f
-#define MATCH_FEQ_S 0xa0002053
-#define MASK_FEQ_S  0xfe00707f
-#define MATCH_FLE_D 0xa2000053
-#define MASK_FLE_D  0xfe00707f
-#define MATCH_FLT_D 0xa2001053
-#define MASK_FLT_D  0xfe00707f
-#define MATCH_FEQ_D 0xa2002053
-#define MASK_FEQ_D  0xfe00707f
 #define MATCH_FLE_Q 0xa6000053
 #define MASK_FLE_Q  0xfe00707f
 #define MATCH_FLT_Q 0xa6001053
 #define MASK_FLT_Q  0xfe00707f
 #define MATCH_FEQ_Q 0xa6002053
 #define MASK_FEQ_Q  0xfe00707f
-#define MATCH_FCVT_W_S 0xc0000053
-#define MASK_FCVT_W_S  0xfff0007f
-#define MATCH_FCVT_WU_S 0xc0100053
-#define MASK_FCVT_WU_S  0xfff0007f
-#define MATCH_FCVT_L_S 0xc0200053
-#define MASK_FCVT_L_S  0xfff0007f
-#define MATCH_FCVT_LU_S 0xc0300053
-#define MASK_FCVT_LU_S  0xfff0007f
-#define MATCH_FMV_X_W 0xe0000053
-#define MASK_FMV_X_W  0xfff0707f
-#define MATCH_FCLASS_S 0xe0001053
-#define MASK_FCLASS_S  0xfff0707f
-#define MATCH_FCVT_W_D 0xc2000053
-#define MASK_FCVT_W_D  0xfff0007f
-#define MATCH_FCVT_WU_D 0xc2100053
-#define MASK_FCVT_WU_D  0xfff0007f
-#define MATCH_FCVT_L_D 0xc2200053
-#define MASK_FCVT_L_D  0xfff0007f
-#define MATCH_FCVT_LU_D 0xc2300053
-#define MASK_FCVT_LU_D  0xfff0007f
-#define MATCH_FMV_X_D 0xe2000053
-#define MASK_FMV_X_D  0xfff0707f
-#define MATCH_FCLASS_D 0xe2001053
-#define MASK_FCLASS_D  0xfff0707f
 #define MATCH_FCVT_W_Q 0xc6000053
 #define MASK_FCVT_W_Q  0xfff0007f
 #define MATCH_FCVT_WU_Q 0xc6100053
 #define MASK_FCVT_WU_Q  0xfff0007f
-#define MATCH_FCVT_L_Q 0xc6200053
-#define MASK_FCVT_L_Q  0xfff0007f
-#define MATCH_FCVT_LU_Q 0xc6300053
-#define MASK_FCVT_LU_Q  0xfff0007f
-#define MATCH_FMV_X_Q 0xe6000053
-#define MASK_FMV_X_Q  0xfff0707f
 #define MATCH_FCLASS_Q 0xe6001053
 #define MASK_FCLASS_Q  0xfff0707f
-#define MATCH_FCVT_S_W 0xd0000053
-#define MASK_FCVT_S_W  0xfff0007f
-#define MATCH_FCVT_S_WU 0xd0100053
-#define MASK_FCVT_S_WU  0xfff0007f
-#define MATCH_FCVT_S_L 0xd0200053
-#define MASK_FCVT_S_L  0xfff0007f
-#define MATCH_FCVT_S_LU 0xd0300053
-#define MASK_FCVT_S_LU  0xfff0007f
-#define MATCH_FMV_W_X 0xf0000053
-#define MASK_FMV_W_X  0xfff0707f
-#define MATCH_FCVT_D_W 0xd2000053
-#define MASK_FCVT_D_W  0xfff0007f
-#define MATCH_FCVT_D_WU 0xd2100053
-#define MASK_FCVT_D_WU  0xfff0007f
-#define MATCH_FCVT_D_L 0xd2200053
-#define MASK_FCVT_D_L  0xfff0007f
-#define MATCH_FCVT_D_LU 0xd2300053
-#define MASK_FCVT_D_LU  0xfff0007f
-#define MATCH_FMV_D_X 0xf2000053
-#define MASK_FMV_D_X  0xfff0707f
 #define MATCH_FCVT_Q_W 0xd6000053
 #define MASK_FCVT_Q_W  0xfff0007f
 #define MATCH_FCVT_Q_WU 0xd6100053
 #define MASK_FCVT_Q_WU  0xfff0007f
-#define MATCH_FCVT_Q_L 0xd6200053
-#define MASK_FCVT_Q_L  0xfff0007f
-#define MATCH_FCVT_Q_LU 0xd6300053
-#define MASK_FCVT_Q_LU  0xfff0007f
-#define MATCH_FMV_Q_X 0xf6000053
-#define MASK_FMV_Q_X  0xfff0707f
-#define MATCH_FLW 0x2007
-#define MASK_FLW  0x707f
-#define MATCH_FLD 0x3007
-#define MASK_FLD  0x707f
 #define MATCH_FLQ 0x4007
 #define MASK_FLQ  0x707f
-#define MATCH_FSW 0x2027
-#define MASK_FSW  0x707f
-#define MATCH_FSD 0x3027
-#define MASK_FSD  0x707f
 #define MATCH_FSQ 0x4027
 #define MASK_FSQ  0x707f
-#define MATCH_FMADD_S 0x43
-#define MASK_FMADD_S  0x600007f
-#define MATCH_FMSUB_S 0x47
-#define MASK_FMSUB_S  0x600007f
-#define MATCH_FNMSUB_S 0x4b
-#define MASK_FNMSUB_S  0x600007f
-#define MATCH_FNMADD_S 0x4f
-#define MASK_FNMADD_S  0x600007f
-#define MATCH_FMADD_D 0x2000043
-#define MASK_FMADD_D  0x600007f
-#define MATCH_FMSUB_D 0x2000047
-#define MASK_FMSUB_D  0x600007f
-#define MATCH_FNMSUB_D 0x200004b
-#define MASK_FNMSUB_D  0x600007f
-#define MATCH_FNMADD_D 0x200004f
-#define MASK_FNMADD_D  0x600007f
 #define MATCH_FMADD_Q 0x6000043
 #define MASK_FMADD_Q  0x600007f
 #define MATCH_FMSUB_Q 0x6000047
@@ -616,6 +636,50 @@
 #define MASK_FNMSUB_Q  0x600007f
 #define MATCH_FNMADD_Q 0x600004f
 #define MASK_FNMADD_Q  0x600007f
+#define MATCH_FCVT_L_Q 0xc6200053
+#define MASK_FCVT_L_Q  0xfff0007f
+#define MATCH_FCVT_LU_Q 0xc6300053
+#define MASK_FCVT_LU_Q  0xfff0007f
+#define MATCH_FCVT_Q_L 0xd6200053
+#define MASK_FCVT_Q_L  0xfff0007f
+#define MATCH_FCVT_Q_LU 0xd6300053
+#define MASK_FCVT_Q_LU  0xfff0007f
+#define MATCH_FMV_X_Q 0xe6000053
+#define MASK_FMV_X_Q  0xfff0707f
+#define MATCH_FMV_Q_X 0xf6000053
+#define MASK_FMV_Q_X  0xfff0707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL  0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK  0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET  0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET  0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET  0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET  0xffffffff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA  0xfe007fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI  0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW  0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS  0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC  0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI  0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI  0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI  0x707f
+#define MATCH_HFENCE_VVMA 0x22000073
+#define MASK_HFENCE_VVMA  0xfe007fff
+#define MATCH_HFENCE_GVMA 0x62000073
+#define MASK_HFENCE_GVMA  0xfe007fff
 #define MATCH_C_NOP 0x1
 #define MASK_C_NOP  0xffff
 #define MATCH_C_ADDI16SP 0x6101
@@ -626,16 +690,6 @@
 #define MASK_C_JALR  0xf07f
 #define MATCH_C_EBREAK 0x9002
 #define MASK_C_EBREAK  0xffff
-#define MATCH_C_LD 0x6000
-#define MASK_C_LD  0xe003
-#define MATCH_C_SD 0xe000
-#define MASK_C_SD  0xe003
-#define MATCH_C_ADDIW 0x2001
-#define MASK_C_ADDIW  0xe003
-#define MATCH_C_LDSP 0x6002
-#define MASK_C_LDSP  0xe003
-#define MATCH_C_SDSP 0xe002
-#define MASK_C_SDSP  0xe003
 #define MATCH_C_ADDI4SPN 0x0
 #define MASK_C_ADDI4SPN  0xe003
 #define MATCH_C_FLD 0x2000
@@ -672,10 +726,6 @@
 #define MASK_C_OR  0xfc63
 #define MATCH_C_AND 0x8c61
 #define MASK_C_AND  0xfc63
-#define MATCH_C_SUBW 0x9c01
-#define MASK_C_SUBW  0xfc63
-#define MATCH_C_ADDW 0x9c21
-#define MASK_C_ADDW  0xfc63
 #define MATCH_C_J 0xa001
 #define MASK_C_J  0xe003
 #define MATCH_C_BEQZ 0xc001
@@ -700,6 +750,34 @@
 #define MASK_C_SWSP  0xe003
 #define MATCH_C_FSWSP 0xe002
 #define MASK_C_FSWSP  0xe003
+#define MATCH_C_SRLI_RV32 0x8001
+#define MASK_C_SRLI_RV32  0xfc03
+#define MATCH_C_SRAI_RV32 0x8401
+#define MASK_C_SRAI_RV32  0xfc03
+#define MATCH_C_SLLI_RV32 0x2
+#define MASK_C_SLLI_RV32  0xf003
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD  0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD  0xe003
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW  0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW  0xfc63
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW  0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP  0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP  0xe003
+#define MATCH_C_LQ 0x2000
+#define MASK_C_LQ  0xe003
+#define MATCH_C_SQ 0xa000
+#define MASK_C_SQ  0xe003
+#define MATCH_C_LQSP 0x2002
+#define MASK_C_LQSP  0xe003
+#define MATCH_C_SQSP 0xa002
+#define MASK_C_SQSP  0xe003
 #define MATCH_CUSTOM0 0xb
 #define MASK_CUSTOM0  0x707f
 #define MATCH_CUSTOM0_RS1 0x200b
@@ -748,9 +826,775 @@
 #define MASK_CUSTOM3_RD_RS1  0x707f
 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
 #define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define MATCH_VSETVLI 0x7057
+#define MASK_VSETVLI  0x8000707f
+#define MATCH_VSETVL 0x80007057
+#define MASK_VSETVL  0xfe00707f
+#define MATCH_VLB_V 0x10000007
+#define MASK_VLB_V  0x1df0707f
+#define MATCH_VLH_V 0x10005007
+#define MASK_VLH_V  0x1df0707f
+#define MATCH_VLW_V 0x10006007
+#define MASK_VLW_V  0x1df0707f
+#define MATCH_VLE_V 0x7007
+#define MASK_VLE_V  0x1df0707f
+#define MATCH_VLBU_V 0x7
+#define MASK_VLBU_V  0x1df0707f
+#define MATCH_VLHU_V 0x5007
+#define MASK_VLHU_V  0x1df0707f
+#define MATCH_VLWU_V 0x6007
+#define MASK_VLWU_V  0x1df0707f
+#define MATCH_VSB_V 0x27
+#define MASK_VSB_V  0x1df0707f
+#define MATCH_VSH_V 0x5027
+#define MASK_VSH_V  0x1df0707f
+#define MATCH_VSW_V 0x6027
+#define MASK_VSW_V  0x1df0707f
+#define MATCH_VSE_V 0x7027
+#define MASK_VSE_V  0x1df0707f
+#define MATCH_VLSB_V 0x18000007
+#define MASK_VLSB_V  0x1c00707f
+#define MATCH_VLSH_V 0x18005007
+#define MASK_VLSH_V  0x1c00707f
+#define MATCH_VLSW_V 0x18006007
+#define MASK_VLSW_V  0x1c00707f
+#define MATCH_VLSE_V 0x8007007
+#define MASK_VLSE_V  0x1c00707f
+#define MATCH_VLSBU_V 0x8000007
+#define MASK_VLSBU_V  0x1c00707f
+#define MATCH_VLSHU_V 0x8005007
+#define MASK_VLSHU_V  0x1c00707f
+#define MATCH_VLSWU_V 0x8006007
+#define MASK_VLSWU_V  0x1c00707f
+#define MATCH_VSSB_V 0x8000027
+#define MASK_VSSB_V  0x1c00707f
+#define MATCH_VSSH_V 0x8005027
+#define MASK_VSSH_V  0x1c00707f
+#define MATCH_VSSW_V 0x8006027
+#define MASK_VSSW_V  0x1c00707f
+#define MATCH_VSSE_V 0x8007027
+#define MASK_VSSE_V  0x1c00707f
+#define MATCH_VLXB_V 0x1c000007
+#define MASK_VLXB_V  0x1c00707f
+#define MATCH_VLXH_V 0x1c005007
+#define MASK_VLXH_V  0x1c00707f
+#define MATCH_VLXW_V 0x1c006007
+#define MASK_VLXW_V  0x1c00707f
+#define MATCH_VLXE_V 0xc007007
+#define MASK_VLXE_V  0x1c00707f
+#define MATCH_VLXBU_V 0xc000007
+#define MASK_VLXBU_V  0x1c00707f
+#define MATCH_VLXHU_V 0xc005007
+#define MASK_VLXHU_V  0x1c00707f
+#define MATCH_VLXWU_V 0xc006007
+#define MASK_VLXWU_V  0x1c00707f
+#define MATCH_VSXB_V 0xc000027
+#define MASK_VSXB_V  0x1c00707f
+#define MATCH_VSXH_V 0xc005027
+#define MASK_VSXH_V  0x1c00707f
+#define MATCH_VSXW_V 0xc006027
+#define MASK_VSXW_V  0x1c00707f
+#define MATCH_VSXE_V 0xc007027
+#define MASK_VSXE_V  0x1c00707f
+#define MATCH_VSUXB_V 0x1c000027
+#define MASK_VSUXB_V  0xfc00707f
+#define MATCH_VSUXH_V 0x1c005027
+#define MASK_VSUXH_V  0xfc00707f
+#define MATCH_VSUXW_V 0x1c006027
+#define MASK_VSUXW_V  0xfc00707f
+#define MATCH_VSUXE_V 0x1c007027
+#define MASK_VSUXE_V  0xfc00707f
+#define MATCH_VLBFF_V 0x11000007
+#define MASK_VLBFF_V  0x1df0707f
+#define MATCH_VLHFF_V 0x11005007
+#define MASK_VLHFF_V  0x1df0707f
+#define MATCH_VLWFF_V 0x11006007
+#define MASK_VLWFF_V  0x1df0707f
+#define MATCH_VLEFF_V 0x1007007
+#define MASK_VLEFF_V  0x1df0707f
+#define MATCH_VLBUFF_V 0x1000007
+#define MASK_VLBUFF_V  0x1df0707f
+#define MATCH_VLHUFF_V 0x1005007
+#define MASK_VLHUFF_V  0x1df0707f
+#define MATCH_VLWUFF_V 0x1006007
+#define MASK_VLWUFF_V  0x1df0707f
+#define MATCH_VL1R_V 0x2807007
+#define MASK_VL1R_V  0xfff0707f
+#define MATCH_VS1R_V 0x2807027
+#define MASK_VS1R_V  0xfff0707f
+#define MATCH_VFADD_VF 0x5057
+#define MASK_VFADD_VF  0xfc00707f
+#define MATCH_VFSUB_VF 0x8005057
+#define MASK_VFSUB_VF  0xfc00707f
+#define MATCH_VFMIN_VF 0x10005057
+#define MASK_VFMIN_VF  0xfc00707f
+#define MATCH_VFMAX_VF 0x18005057
+#define MASK_VFMAX_VF  0xfc00707f
+#define MATCH_VFSGNJ_VF 0x20005057
+#define MASK_VFSGNJ_VF  0xfc00707f
+#define MATCH_VFSGNJN_VF 0x24005057
+#define MASK_VFSGNJN_VF  0xfc00707f
+#define MATCH_VFSGNJX_VF 0x28005057
+#define MASK_VFSGNJX_VF  0xfc00707f
+#define MATCH_VFSLIDE1UP_VF 0x38005057
+#define MASK_VFSLIDE1UP_VF  0xfc00707f
+#define MATCH_VFSLIDE1DOWN_VF 0x3c005057
+#define MASK_VFSLIDE1DOWN_VF  0xfc00707f
+#define MATCH_VFMV_S_F 0x42005057
+#define MASK_VFMV_S_F  0xfff0707f
+#define MATCH_VFMERGE_VFM 0x5c005057
+#define MASK_VFMERGE_VFM  0xfe00707f
+#define MATCH_VFMV_V_F 0x5e005057
+#define MASK_VFMV_V_F  0xfff0707f
+#define MATCH_VMFEQ_VF 0x60005057
+#define MASK_VMFEQ_VF  0xfc00707f
+#define MATCH_VMFLE_VF 0x64005057
+#define MASK_VMFLE_VF  0xfc00707f
+#define MATCH_VMFLT_VF 0x6c005057
+#define MASK_VMFLT_VF  0xfc00707f
+#define MATCH_VMFNE_VF 0x70005057
+#define MASK_VMFNE_VF  0xfc00707f
+#define MATCH_VMFGT_VF 0x74005057
+#define MASK_VMFGT_VF  0xfc00707f
+#define MATCH_VMFGE_VF 0x7c005057
+#define MASK_VMFGE_VF  0xfc00707f
+#define MATCH_VFDIV_VF 0x80005057
+#define MASK_VFDIV_VF  0xfc00707f
+#define MATCH_VFRDIV_VF 0x84005057
+#define MASK_VFRDIV_VF  0xfc00707f
+#define MATCH_VFMUL_VF 0x90005057
+#define MASK_VFMUL_VF  0xfc00707f
+#define MATCH_VFRSUB_VF 0x9c005057
+#define MASK_VFRSUB_VF  0xfc00707f
+#define MATCH_VFMADD_VF 0xa0005057
+#define MASK_VFMADD_VF  0xfc00707f
+#define MATCH_VFNMADD_VF 0xa4005057
+#define MASK_VFNMADD_VF  0xfc00707f
+#define MATCH_VFMSUB_VF 0xa8005057
+#define MASK_VFMSUB_VF  0xfc00707f
+#define MATCH_VFNMSUB_VF 0xac005057
+#define MASK_VFNMSUB_VF  0xfc00707f
+#define MATCH_VFMACC_VF 0xb0005057
+#define MASK_VFMACC_VF  0xfc00707f
+#define MATCH_VFNMACC_VF 0xb4005057
+#define MASK_VFNMACC_VF  0xfc00707f
+#define MATCH_VFMSAC_VF 0xb8005057
+#define MASK_VFMSAC_VF  0xfc00707f
+#define MATCH_VFNMSAC_VF 0xbc005057
+#define MASK_VFNMSAC_VF  0xfc00707f
+#define MATCH_VFWADD_VF 0xc0005057
+#define MASK_VFWADD_VF  0xfc00707f
+#define MATCH_VFWSUB_VF 0xc8005057
+#define MASK_VFWSUB_VF  0xfc00707f
+#define MATCH_VFWADD_WF 0xd0005057
+#define MASK_VFWADD_WF  0xfc00707f
+#define MATCH_VFWSUB_WF 0xd8005057
+#define MASK_VFWSUB_WF  0xfc00707f
+#define MATCH_VFWMUL_VF 0xe0005057
+#define MASK_VFWMUL_VF  0xfc00707f
+#define MATCH_VFWMACC_VF 0xf0005057
+#define MASK_VFWMACC_VF  0xfc00707f
+#define MATCH_VFWNMACC_VF 0xf4005057
+#define MASK_VFWNMACC_VF  0xfc00707f
+#define MATCH_VFWMSAC_VF 0xf8005057
+#define MASK_VFWMSAC_VF  0xfc00707f
+#define MATCH_VFWNMSAC_VF 0xfc005057
+#define MASK_VFWNMSAC_VF  0xfc00707f
+#define MATCH_VFADD_VV 0x1057
+#define MASK_VFADD_VV  0xfc00707f
+#define MATCH_VFREDSUM_VS 0x4001057
+#define MASK_VFREDSUM_VS  0xfc00707f
+#define MATCH_VFSUB_VV 0x8001057
+#define MASK_VFSUB_VV  0xfc00707f
+#define MATCH_VFREDOSUM_VS 0xc001057
+#define MASK_VFREDOSUM_VS  0xfc00707f
+#define MATCH_VFMIN_VV 0x10001057
+#define MASK_VFMIN_VV  0xfc00707f
+#define MATCH_VFREDMIN_VS 0x14001057
+#define MASK_VFREDMIN_VS  0xfc00707f
+#define MATCH_VFMAX_VV 0x18001057
+#define MASK_VFMAX_VV  0xfc00707f
+#define MATCH_VFREDMAX_VS 0x1c001057
+#define MASK_VFREDMAX_VS  0xfc00707f
+#define MATCH_VFSGNJ_VV 0x20001057
+#define MASK_VFSGNJ_VV  0xfc00707f
+#define MATCH_VFSGNJN_VV 0x24001057
+#define MASK_VFSGNJN_VV  0xfc00707f
+#define MATCH_VFSGNJX_VV 0x28001057
+#define MASK_VFSGNJX_VV  0xfc00707f
+#define MATCH_VFMV_F_S 0x42001057
+#define MASK_VFMV_F_S  0xfe0ff07f
+#define MATCH_VMFEQ_VV 0x60001057
+#define MASK_VMFEQ_VV  0xfc00707f
+#define MATCH_VMFLE_VV 0x64001057
+#define MASK_VMFLE_VV  0xfc00707f
+#define MATCH_VMFLT_VV 0x6c001057
+#define MASK_VMFLT_VV  0xfc00707f
+#define MATCH_VMFNE_VV 0x70001057
+#define MASK_VMFNE_VV  0xfc00707f
+#define MATCH_VFDIV_VV 0x80001057
+#define MASK_VFDIV_VV  0xfc00707f
+#define MATCH_VFMUL_VV 0x90001057
+#define MASK_VFMUL_VV  0xfc00707f
+#define MATCH_VFMADD_VV 0xa0001057
+#define MASK_VFMADD_VV  0xfc00707f
+#define MATCH_VFNMADD_VV 0xa4001057
+#define MASK_VFNMADD_VV  0xfc00707f
+#define MATCH_VFMSUB_VV 0xa8001057
+#define MASK_VFMSUB_VV  0xfc00707f
+#define MATCH_VFNMSUB_VV 0xac001057
+#define MASK_VFNMSUB_VV  0xfc00707f
+#define MATCH_VFMACC_VV 0xb0001057
+#define MASK_VFMACC_VV  0xfc00707f
+#define MATCH_VFNMACC_VV 0xb4001057
+#define MASK_VFNMACC_VV  0xfc00707f
+#define MATCH_VFMSAC_VV 0xb8001057
+#define MASK_VFMSAC_VV  0xfc00707f
+#define MATCH_VFNMSAC_VV 0xbc001057
+#define MASK_VFNMSAC_VV  0xfc00707f
+#define MATCH_VFCVT_XU_F_V 0x88001057
+#define MASK_VFCVT_XU_F_V  0xfc0ff07f
+#define MATCH_VFCVT_X_F_V 0x88009057
+#define MASK_VFCVT_X_F_V  0xfc0ff07f
+#define MATCH_VFCVT_F_XU_V 0x88011057
+#define MASK_VFCVT_F_XU_V  0xfc0ff07f
+#define MATCH_VFCVT_F_X_V 0x88019057
+#define MASK_VFCVT_F_X_V  0xfc0ff07f
+#define MATCH_VFCVT_RTZ_XU_F_V 0x88031057
+#define MASK_VFCVT_RTZ_XU_F_V  0xfc0ff07f
+#define MATCH_VFCVT_RTZ_X_F_V 0x88039057
+#define MASK_VFCVT_RTZ_X_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_XU_F_V 0x88041057
+#define MASK_VFWCVT_XU_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_X_F_V 0x88049057
+#define MASK_VFWCVT_X_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_F_XU_V 0x88051057
+#define MASK_VFWCVT_F_XU_V  0xfc0ff07f
+#define MATCH_VFWCVT_F_X_V 0x88059057
+#define MASK_VFWCVT_F_X_V  0xfc0ff07f
+#define MATCH_VFWCVT_F_F_V 0x88061057
+#define MASK_VFWCVT_F_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057
+#define MASK_VFWCVT_RTZ_XU_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_RTZ_X_F_V 0x88079057
+#define MASK_VFWCVT_RTZ_X_F_V  0xfc0ff07f
+#define MATCH_VFNCVT_XU_F_W 0x88081057
+#define MASK_VFNCVT_XU_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_X_F_W 0x88089057
+#define MASK_VFNCVT_X_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_F_XU_W 0x88091057
+#define MASK_VFNCVT_F_XU_W  0xfc0ff07f
+#define MATCH_VFNCVT_F_X_W 0x88099057
+#define MASK_VFNCVT_F_X_W  0xfc0ff07f
+#define MATCH_VFNCVT_F_F_W 0x880a1057
+#define MASK_VFNCVT_F_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_ROD_F_F_W 0x880a9057
+#define MASK_VFNCVT_ROD_F_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057
+#define MASK_VFNCVT_RTZ_XU_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057
+#define MASK_VFNCVT_RTZ_X_F_W  0xfc0ff07f
+#define MATCH_VFSQRT_V 0x8c001057
+#define MASK_VFSQRT_V  0xfc0ff07f
+#define MATCH_VFCLASS_V 0x8c081057
+#define MASK_VFCLASS_V  0xfc0ff07f
+#define MATCH_VFWADD_VV 0xc0001057
+#define MASK_VFWADD_VV  0xfc00707f
+#define MATCH_VFWREDSUM_VS 0xc4001057
+#define MASK_VFWREDSUM_VS  0xfc00707f
+#define MATCH_VFWSUB_VV 0xc8001057
+#define MASK_VFWSUB_VV  0xfc00707f
+#define MATCH_VFWREDOSUM_VS 0xcc001057
+#define MASK_VFWREDOSUM_VS  0xfc00707f
+#define MATCH_VFWADD_WV 0xd0001057
+#define MASK_VFWADD_WV  0xfc00707f
+#define MATCH_VFWSUB_WV 0xd8001057
+#define MASK_VFWSUB_WV  0xfc00707f
+#define MATCH_VFWMUL_VV 0xe0001057
+#define MASK_VFWMUL_VV  0xfc00707f
+#define MATCH_VFDOT_VV 0xe4001057
+#define MASK_VFDOT_VV  0xfc00707f
+#define MATCH_VFWMACC_VV 0xf0001057
+#define MASK_VFWMACC_VV  0xfc00707f
+#define MATCH_VFWNMACC_VV 0xf4001057
+#define MASK_VFWNMACC_VV  0xfc00707f
+#define MATCH_VFWMSAC_VV 0xf8001057
+#define MASK_VFWMSAC_VV  0xfc00707f
+#define MATCH_VFWNMSAC_VV 0xfc001057
+#define MASK_VFWNMSAC_VV  0xfc00707f
+#define MATCH_VADD_VX 0x4057
+#define MASK_VADD_VX  0xfc00707f
+#define MATCH_VSUB_VX 0x8004057
+#define MASK_VSUB_VX  0xfc00707f
+#define MATCH_VRSUB_VX 0xc004057
+#define MASK_VRSUB_VX  0xfc00707f
+#define MATCH_VMINU_VX 0x10004057
+#define MASK_VMINU_VX  0xfc00707f
+#define MATCH_VMIN_VX 0x14004057
+#define MASK_VMIN_VX  0xfc00707f
+#define MATCH_VMAXU_VX 0x18004057
+#define MASK_VMAXU_VX  0xfc00707f
+#define MATCH_VMAX_VX 0x1c004057
+#define MASK_VMAX_VX  0xfc00707f
+#define MATCH_VAND_VX 0x24004057
+#define MASK_VAND_VX  0xfc00707f
+#define MATCH_VOR_VX 0x28004057
+#define MASK_VOR_VX  0xfc00707f
+#define MATCH_VXOR_VX 0x2c004057
+#define MASK_VXOR_VX  0xfc00707f
+#define MATCH_VRGATHER_VX 0x30004057
+#define MASK_VRGATHER_VX  0xfc00707f
+#define MATCH_VSLIDEUP_VX 0x38004057
+#define MASK_VSLIDEUP_VX  0xfc00707f
+#define MATCH_VSLIDEDOWN_VX 0x3c004057
+#define MASK_VSLIDEDOWN_VX  0xfc00707f
+#define MATCH_VADC_VXM 0x40004057
+#define MASK_VADC_VXM  0xfe00707f
+#define MATCH_VMADC_VXM 0x44004057
+#define MASK_VMADC_VXM  0xfc00707f
+#define MATCH_VSBC_VXM 0x48004057
+#define MASK_VSBC_VXM  0xfe00707f
+#define MATCH_VMSBC_VXM 0x4c004057
+#define MASK_VMSBC_VXM  0xfc00707f
+#define MATCH_VMERGE_VXM 0x5c004057
+#define MASK_VMERGE_VXM  0xfe00707f
+#define MATCH_VMV_V_X 0x5e004057
+#define MASK_VMV_V_X  0xfff0707f
+#define MATCH_VMSEQ_VX 0x60004057
+#define MASK_VMSEQ_VX  0xfc00707f
+#define MATCH_VMSNE_VX 0x64004057
+#define MASK_VMSNE_VX  0xfc00707f
+#define MATCH_VMSLTU_VX 0x68004057
+#define MASK_VMSLTU_VX  0xfc00707f
+#define MATCH_VMSLT_VX 0x6c004057
+#define MASK_VMSLT_VX  0xfc00707f
+#define MATCH_VMSLEU_VX 0x70004057
+#define MASK_VMSLEU_VX  0xfc00707f
+#define MATCH_VMSLE_VX 0x74004057
+#define MASK_VMSLE_VX  0xfc00707f
+#define MATCH_VMSGTU_VX 0x78004057
+#define MASK_VMSGTU_VX  0xfc00707f
+#define MATCH_VMSGT_VX 0x7c004057
+#define MASK_VMSGT_VX  0xfc00707f
+#define MATCH_VSADDU_VX 0x80004057
+#define MASK_VSADDU_VX  0xfc00707f
+#define MATCH_VSADD_VX 0x84004057
+#define MASK_VSADD_VX  0xfc00707f
+#define MATCH_VSSUBU_VX 0x88004057
+#define MASK_VSSUBU_VX  0xfc00707f
+#define MATCH_VSSUB_VX 0x8c004057
+#define MASK_VSSUB_VX  0xfc00707f
+#define MATCH_VSLL_VX 0x94004057
+#define MASK_VSLL_VX  0xfc00707f
+#define MATCH_VSMUL_VX 0x9c004057
+#define MASK_VSMUL_VX  0xfc00707f
+#define MATCH_VSRL_VX 0xa0004057
+#define MASK_VSRL_VX  0xfc00707f
+#define MATCH_VSRA_VX 0xa4004057
+#define MASK_VSRA_VX  0xfc00707f
+#define MATCH_VSSRL_VX 0xa8004057
+#define MASK_VSSRL_VX  0xfc00707f
+#define MATCH_VSSRA_VX 0xac004057
+#define MASK_VSSRA_VX  0xfc00707f
+#define MATCH_VNSRL_WX 0xb0004057
+#define MASK_VNSRL_WX  0xfc00707f
+#define MATCH_VNSRA_WX 0xb4004057
+#define MASK_VNSRA_WX  0xfc00707f
+#define MATCH_VNCLIPU_WX 0xb8004057
+#define MASK_VNCLIPU_WX  0xfc00707f
+#define MATCH_VNCLIP_WX 0xbc004057
+#define MASK_VNCLIP_WX  0xfc00707f
+#define MATCH_VQMACCU_VX 0xf0004057
+#define MASK_VQMACCU_VX  0xfc00707f
+#define MATCH_VQMACC_VX 0xf4004057
+#define MASK_VQMACC_VX  0xfc00707f
+#define MATCH_VQMACCUS_VX 0xf8004057
+#define MASK_VQMACCUS_VX  0xfc00707f
+#define MATCH_VQMACCSU_VX 0xfc004057
+#define MASK_VQMACCSU_VX  0xfc00707f
+#define MATCH_VADD_VV 0x57
+#define MASK_VADD_VV  0xfc00707f
+#define MATCH_VSUB_VV 0x8000057
+#define MASK_VSUB_VV  0xfc00707f
+#define MATCH_VMINU_VV 0x10000057
+#define MASK_VMINU_VV  0xfc00707f
+#define MATCH_VMIN_VV 0x14000057
+#define MASK_VMIN_VV  0xfc00707f
+#define MATCH_VMAXU_VV 0x18000057
+#define MASK_VMAXU_VV  0xfc00707f
+#define MATCH_VMAX_VV 0x1c000057
+#define MASK_VMAX_VV  0xfc00707f
+#define MATCH_VAND_VV 0x24000057
+#define MASK_VAND_VV  0xfc00707f
+#define MATCH_VOR_VV 0x28000057
+#define MASK_VOR_VV  0xfc00707f
+#define MATCH_VXOR_VV 0x2c000057
+#define MASK_VXOR_VV  0xfc00707f
+#define MATCH_VRGATHER_VV 0x30000057
+#define MASK_VRGATHER_VV  0xfc00707f
+#define MATCH_VADC_VVM 0x40000057
+#define MASK_VADC_VVM  0xfe00707f
+#define MATCH_VMADC_VVM 0x44000057
+#define MASK_VMADC_VVM  0xfc00707f
+#define MATCH_VSBC_VVM 0x48000057
+#define MASK_VSBC_VVM  0xfe00707f
+#define MATCH_VMSBC_VVM 0x4c000057
+#define MASK_VMSBC_VVM  0xfc00707f
+#define MATCH_VMERGE_VVM 0x5c000057
+#define MASK_VMERGE_VVM  0xfe00707f
+#define MATCH_VMV_V_V 0x5e000057
+#define MASK_VMV_V_V  0xfff0707f
+#define MATCH_VMSEQ_VV 0x60000057
+#define MASK_VMSEQ_VV  0xfc00707f
+#define MATCH_VMSNE_VV 0x64000057
+#define MASK_VMSNE_VV  0xfc00707f
+#define MATCH_VMSLTU_VV 0x68000057
+#define MASK_VMSLTU_VV  0xfc00707f
+#define MATCH_VMSLT_VV 0x6c000057
+#define MASK_VMSLT_VV  0xfc00707f
+#define MATCH_VMSLEU_VV 0x70000057
+#define MASK_VMSLEU_VV  0xfc00707f
+#define MATCH_VMSLE_VV 0x74000057
+#define MASK_VMSLE_VV  0xfc00707f
+#define MATCH_VSADDU_VV 0x80000057
+#define MASK_VSADDU_VV  0xfc00707f
+#define MATCH_VSADD_VV 0x84000057
+#define MASK_VSADD_VV  0xfc00707f
+#define MATCH_VSSUBU_VV 0x88000057
+#define MASK_VSSUBU_VV  0xfc00707f
+#define MATCH_VSSUB_VV 0x8c000057
+#define MASK_VSSUB_VV  0xfc00707f
+#define MATCH_VSLL_VV 0x94000057
+#define MASK_VSLL_VV  0xfc00707f
+#define MATCH_VSMUL_VV 0x9c000057
+#define MASK_VSMUL_VV  0xfc00707f
+#define MATCH_VSRL_VV 0xa0000057
+#define MASK_VSRL_VV  0xfc00707f
+#define MATCH_VSRA_VV 0xa4000057
+#define MASK_VSRA_VV  0xfc00707f
+#define MATCH_VSSRL_VV 0xa8000057
+#define MASK_VSSRL_VV  0xfc00707f
+#define MATCH_VSSRA_VV 0xac000057
+#define MASK_VSSRA_VV  0xfc00707f
+#define MATCH_VNSRL_WV 0xb0000057
+#define MASK_VNSRL_WV  0xfc00707f
+#define MATCH_VNSRA_WV 0xb4000057
+#define MASK_VNSRA_WV  0xfc00707f
+#define MATCH_VNCLIPU_WV 0xb8000057
+#define MASK_VNCLIPU_WV  0xfc00707f
+#define MATCH_VNCLIP_WV 0xbc000057
+#define MASK_VNCLIP_WV  0xfc00707f
+#define MATCH_VWREDSUMU_VS 0xc0000057
+#define MASK_VWREDSUMU_VS  0xfc00707f
+#define MATCH_VWREDSUM_VS 0xc4000057
+#define MASK_VWREDSUM_VS  0xfc00707f
+#define MATCH_VDOTU_VV 0xe0000057
+#define MASK_VDOTU_VV  0xfc00707f
+#define MATCH_VDOT_VV 0xe4000057
+#define MASK_VDOT_VV  0xfc00707f
+#define MATCH_VQMACCU_VV 0xf0000057
+#define MASK_VQMACCU_VV  0xfc00707f
+#define MATCH_VQMACC_VV 0xf4000057
+#define MASK_VQMACC_VV  0xfc00707f
+#define MATCH_VQMACCSU_VV 0xfc000057
+#define MASK_VQMACCSU_VV  0xfc00707f
+#define MATCH_VADD_VI 0x3057
+#define MASK_VADD_VI  0xfc00707f
+#define MATCH_VRSUB_VI 0xc003057
+#define MASK_VRSUB_VI  0xfc00707f
+#define MATCH_VAND_VI 0x24003057
+#define MASK_VAND_VI  0xfc00707f
+#define MATCH_VOR_VI 0x28003057
+#define MASK_VOR_VI  0xfc00707f
+#define MATCH_VXOR_VI 0x2c003057
+#define MASK_VXOR_VI  0xfc00707f
+#define MATCH_VRGATHER_VI 0x30003057
+#define MASK_VRGATHER_VI  0xfc00707f
+#define MATCH_VSLIDEUP_VI 0x38003057
+#define MASK_VSLIDEUP_VI  0xfc00707f
+#define MATCH_VSLIDEDOWN_VI 0x3c003057
+#define MASK_VSLIDEDOWN_VI  0xfc00707f
+#define MATCH_VADC_VIM 0x40003057
+#define MASK_VADC_VIM  0xfe00707f
+#define MATCH_VMADC_VIM 0x44003057
+#define MASK_VMADC_VIM  0xfc00707f
+#define MATCH_VMERGE_VIM 0x5c003057
+#define MASK_VMERGE_VIM  0xfe00707f
+#define MATCH_VMV_V_I 0x5e003057
+#define MASK_VMV_V_I  0xfff0707f
+#define MATCH_VMSEQ_VI 0x60003057
+#define MASK_VMSEQ_VI  0xfc00707f
+#define MATCH_VMSNE_VI 0x64003057
+#define MASK_VMSNE_VI  0xfc00707f
+#define MATCH_VMSLEU_VI 0x70003057
+#define MASK_VMSLEU_VI  0xfc00707f
+#define MATCH_VMSLE_VI 0x74003057
+#define MASK_VMSLE_VI  0xfc00707f
+#define MATCH_VMSGTU_VI 0x78003057
+#define MASK_VMSGTU_VI  0xfc00707f
+#define MATCH_VMSGT_VI 0x7c003057
+#define MASK_VMSGT_VI  0xfc00707f
+#define MATCH_VSADDU_VI 0x80003057
+#define MASK_VSADDU_VI  0xfc00707f
+#define MATCH_VSADD_VI 0x84003057
+#define MASK_VSADD_VI  0xfc00707f
+#define MATCH_VSLL_VI 0x94003057
+#define MASK_VSLL_VI  0xfc00707f
+#define MATCH_VMV1R_V 0x9e003057
+#define MASK_VMV1R_V  0xfe0ff07f
+#define MATCH_VMV2R_V 0x9e00b057
+#define MASK_VMV2R_V  0xfe0ff07f
+#define MATCH_VMV4R_V 0x9e01b057
+#define MASK_VMV4R_V  0xfe0ff07f
+#define MATCH_VMV8R_V 0x9e03b057
+#define MASK_VMV8R_V  0xfe0ff07f
+#define MATCH_VSRL_VI 0xa0003057
+#define MASK_VSRL_VI  0xfc00707f
+#define MATCH_VSRA_VI 0xa4003057
+#define MASK_VSRA_VI  0xfc00707f
+#define MATCH_VSSRL_VI 0xa8003057
+#define MASK_VSSRL_VI  0xfc00707f
+#define MATCH_VSSRA_VI 0xac003057
+#define MASK_VSSRA_VI  0xfc00707f
+#define MATCH_VNSRL_WI 0xb0003057
+#define MASK_VNSRL_WI  0xfc00707f
+#define MATCH_VNSRA_WI 0xb4003057
+#define MASK_VNSRA_WI  0xfc00707f
+#define MATCH_VNCLIPU_WI 0xb8003057
+#define MASK_VNCLIPU_WI  0xfc00707f
+#define MATCH_VNCLIP_WI 0xbc003057
+#define MASK_VNCLIP_WI  0xfc00707f
+#define MATCH_VREDSUM_VS 0x2057
+#define MASK_VREDSUM_VS  0xfc00707f
+#define MATCH_VREDAND_VS 0x4002057
+#define MASK_VREDAND_VS  0xfc00707f
+#define MATCH_VREDOR_VS 0x8002057
+#define MASK_VREDOR_VS  0xfc00707f
+#define MATCH_VREDXOR_VS 0xc002057
+#define MASK_VREDXOR_VS  0xfc00707f
+#define MATCH_VREDMINU_VS 0x10002057
+#define MASK_VREDMINU_VS  0xfc00707f
+#define MATCH_VREDMIN_VS 0x14002057
+#define MASK_VREDMIN_VS  0xfc00707f
+#define MATCH_VREDMAXU_VS 0x18002057
+#define MASK_VREDMAXU_VS  0xfc00707f
+#define MATCH_VREDMAX_VS 0x1c002057
+#define MASK_VREDMAX_VS  0xfc00707f
+#define MATCH_VAADDU_VV 0x20002057
+#define MASK_VAADDU_VV  0xfc00707f
+#define MATCH_VAADD_VV 0x24002057
+#define MASK_VAADD_VV  0xfc00707f
+#define MATCH_VASUBU_VV 0x28002057
+#define MASK_VASUBU_VV  0xfc00707f
+#define MATCH_VASUB_VV 0x2c002057
+#define MASK_VASUB_VV  0xfc00707f
+#define MATCH_VMV_X_S 0x42002057
+#define MASK_VMV_X_S  0xfe0ff07f
+#define MATCH_VCOMPRESS_VM 0x5e002057
+#define MASK_VCOMPRESS_VM  0xfe00707f
+#define MATCH_VMANDNOT_MM 0x60002057
+#define MASK_VMANDNOT_MM  0xfc00707f
+#define MATCH_VMAND_MM 0x64002057
+#define MASK_VMAND_MM  0xfc00707f
+#define MATCH_VMOR_MM 0x68002057
+#define MASK_VMOR_MM  0xfc00707f
+#define MATCH_VMXOR_MM 0x6c002057
+#define MASK_VMXOR_MM  0xfc00707f
+#define MATCH_VMORNOT_MM 0x70002057
+#define MASK_VMORNOT_MM  0xfc00707f
+#define MATCH_VMNAND_MM 0x74002057
+#define MASK_VMNAND_MM  0xfc00707f
+#define MATCH_VMNOR_MM 0x78002057
+#define MASK_VMNOR_MM  0xfc00707f
+#define MATCH_VMXNOR_MM 0x7c002057
+#define MASK_VMXNOR_MM  0xfc00707f
+#define MATCH_VMSBF_M 0x5000a057
+#define MASK_VMSBF_M  0xfc0ff07f
+#define MATCH_VMSOF_M 0x50012057
+#define MASK_VMSOF_M  0xfc0ff07f
+#define MATCH_VMSIF_M 0x5001a057
+#define MASK_VMSIF_M  0xfc0ff07f
+#define MATCH_VIOTA_M 0x50082057
+#define MASK_VIOTA_M  0xfc0ff07f
+#define MATCH_VID_V 0x5008a057
+#define MASK_VID_V  0xfdfff07f
+#define MATCH_VPOPC_M 0x40082057
+#define MASK_VPOPC_M  0xfc0ff07f
+#define MATCH_VFIRST_M 0x4008a057
+#define MASK_VFIRST_M  0xfc0ff07f
+#define MATCH_VDIVU_VV 0x80002057
+#define MASK_VDIVU_VV  0xfc00707f
+#define MATCH_VDIV_VV 0x84002057
+#define MASK_VDIV_VV  0xfc00707f
+#define MATCH_VREMU_VV 0x88002057
+#define MASK_VREMU_VV  0xfc00707f
+#define MATCH_VREM_VV 0x8c002057
+#define MASK_VREM_VV  0xfc00707f
+#define MATCH_VMULHU_VV 0x90002057
+#define MASK_VMULHU_VV  0xfc00707f
+#define MATCH_VMUL_VV 0x94002057
+#define MASK_VMUL_VV  0xfc00707f
+#define MATCH_VMULHSU_VV 0x98002057
+#define MASK_VMULHSU_VV  0xfc00707f
+#define MATCH_VMULH_VV 0x9c002057
+#define MASK_VMULH_VV  0xfc00707f
+#define MATCH_VMADD_VV 0xa4002057
+#define MASK_VMADD_VV  0xfc00707f
+#define MATCH_VNMSUB_VV 0xac002057
+#define MASK_VNMSUB_VV  0xfc00707f
+#define MATCH_VMACC_VV 0xb4002057
+#define MASK_VMACC_VV  0xfc00707f
+#define MATCH_VNMSAC_VV 0xbc002057
+#define MASK_VNMSAC_VV  0xfc00707f
+#define MATCH_VWADDU_VV 0xc0002057
+#define MASK_VWADDU_VV  0xfc00707f
+#define MATCH_VWADD_VV 0xc4002057
+#define MASK_VWADD_VV  0xfc00707f
+#define MATCH_VWSUBU_VV 0xc8002057
+#define MASK_VWSUBU_VV  0xfc00707f
+#define MATCH_VWSUB_VV 0xcc002057
+#define MASK_VWSUB_VV  0xfc00707f
+#define MATCH_VWADDU_WV 0xd0002057
+#define MASK_VWADDU_WV  0xfc00707f
+#define MATCH_VWADD_WV 0xd4002057
+#define MASK_VWADD_WV  0xfc00707f
+#define MATCH_VWSUBU_WV 0xd8002057
+#define MASK_VWSUBU_WV  0xfc00707f
+#define MATCH_VWSUB_WV 0xdc002057
+#define MASK_VWSUB_WV  0xfc00707f
+#define MATCH_VWMULU_VV 0xe0002057
+#define MASK_VWMULU_VV  0xfc00707f
+#define MATCH_VWMULSU_VV 0xe8002057
+#define MASK_VWMULSU_VV  0xfc00707f
+#define MATCH_VWMUL_VV 0xec002057
+#define MASK_VWMUL_VV  0xfc00707f
+#define MATCH_VWMACCU_VV 0xf0002057
+#define MASK_VWMACCU_VV  0xfc00707f
+#define MATCH_VWMACC_VV 0xf4002057
+#define MASK_VWMACC_VV  0xfc00707f
+#define MATCH_VWMACCSU_VV 0xfc002057
+#define MASK_VWMACCSU_VV  0xfc00707f
+#define MATCH_VAADDU_VX 0x20006057
+#define MASK_VAADDU_VX  0xfc00707f
+#define MATCH_VAADD_VX 0x24006057
+#define MASK_VAADD_VX  0xfc00707f
+#define MATCH_VASUBU_VX 0x28006057
+#define MASK_VASUBU_VX  0xfc00707f
+#define MATCH_VASUB_VX 0x2c006057
+#define MASK_VASUB_VX  0xfc00707f
+#define MATCH_VMV_S_X 0x42006057
+#define MASK_VMV_S_X  0xfff0707f
+#define MATCH_VSLIDE1UP_VX 0x38006057
+#define MASK_VSLIDE1UP_VX  0xfc00707f
+#define MATCH_VSLIDE1DOWN_VX 0x3c006057
+#define MASK_VSLIDE1DOWN_VX  0xfc00707f
+#define MATCH_VDIVU_VX 0x80006057
+#define MASK_VDIVU_VX  0xfc00707f
+#define MATCH_VDIV_VX 0x84006057
+#define MASK_VDIV_VX  0xfc00707f
+#define MATCH_VREMU_VX 0x88006057
+#define MASK_VREMU_VX  0xfc00707f
+#define MATCH_VREM_VX 0x8c006057
+#define MASK_VREM_VX  0xfc00707f
+#define MATCH_VMULHU_VX 0x90006057
+#define MASK_VMULHU_VX  0xfc00707f
+#define MATCH_VMUL_VX 0x94006057
+#define MASK_VMUL_VX  0xfc00707f
+#define MATCH_VMULHSU_VX 0x98006057
+#define MASK_VMULHSU_VX  0xfc00707f
+#define MATCH_VMULH_VX 0x9c006057
+#define MASK_VMULH_VX  0xfc00707f
+#define MATCH_VMADD_VX 0xa4006057
+#define MASK_VMADD_VX  0xfc00707f
+#define MATCH_VNMSUB_VX 0xac006057
+#define MASK_VNMSUB_VX  0xfc00707f
+#define MATCH_VMACC_VX 0xb4006057
+#define MASK_VMACC_VX  0xfc00707f
+#define MATCH_VNMSAC_VX 0xbc006057
+#define MASK_VNMSAC_VX  0xfc00707f
+#define MATCH_VWADDU_VX 0xc0006057
+#define MASK_VWADDU_VX  0xfc00707f
+#define MATCH_VWADD_VX 0xc4006057
+#define MASK_VWADD_VX  0xfc00707f
+#define MATCH_VWSUBU_VX 0xc8006057
+#define MASK_VWSUBU_VX  0xfc00707f
+#define MATCH_VWSUB_VX 0xcc006057
+#define MASK_VWSUB_VX  0xfc00707f
+#define MATCH_VWADDU_WX 0xd0006057
+#define MASK_VWADDU_WX  0xfc00707f
+#define MATCH_VWADD_WX 0xd4006057
+#define MASK_VWADD_WX  0xfc00707f
+#define MATCH_VWSUBU_WX 0xd8006057
+#define MASK_VWSUBU_WX  0xfc00707f
+#define MATCH_VWSUB_WX 0xdc006057
+#define MASK_VWSUB_WX  0xfc00707f
+#define MATCH_VWMULU_VX 0xe0006057
+#define MASK_VWMULU_VX  0xfc00707f
+#define MATCH_VWMULSU_VX 0xe8006057
+#define MASK_VWMULSU_VX  0xfc00707f
+#define MATCH_VWMUL_VX 0xec006057
+#define MASK_VWMUL_VX  0xfc00707f
+#define MATCH_VWMACCU_VX 0xf0006057
+#define MASK_VWMACCU_VX  0xfc00707f
+#define MATCH_VWMACC_VX 0xf4006057
+#define MASK_VWMACC_VX  0xfc00707f
+#define MATCH_VWMACCUS_VX 0xf8006057
+#define MASK_VWMACCUS_VX  0xfc00707f
+#define MATCH_VWMACCSU_VX 0xfc006057
+#define MASK_VWMACCSU_VX  0xfc00707f
+#define MATCH_VAMOSWAPW_V 0x800602f
+#define MASK_VAMOSWAPW_V  0xf800707f
+#define MATCH_VAMOADDW_V 0x602f
+#define MASK_VAMOADDW_V  0xf800707f
+#define MATCH_VAMOXORW_V 0x2000602f
+#define MASK_VAMOXORW_V  0xf800707f
+#define MATCH_VAMOANDW_V 0x6000602f
+#define MASK_VAMOANDW_V  0xf800707f
+#define MATCH_VAMOORW_V 0x4000602f
+#define MASK_VAMOORW_V  0xf800707f
+#define MATCH_VAMOMINW_V 0x8000602f
+#define MASK_VAMOMINW_V  0xf800707f
+#define MATCH_VAMOMAXW_V 0xa000602f
+#define MASK_VAMOMAXW_V  0xf800707f
+#define MATCH_VAMOMINUW_V 0xc000602f
+#define MASK_VAMOMINUW_V  0xf800707f
+#define MATCH_VAMOMAXUW_V 0xe000602f
+#define MASK_VAMOMAXUW_V  0xf800707f
+#define MATCH_VAMOSWAPE_V 0x800702f
+#define MASK_VAMOSWAPE_V  0xf800707f
+#define MATCH_VAMOADDE_V 0x702f
+#define MASK_VAMOADDE_V  0xf800707f
+#define MATCH_VAMOXORE_V 0x2000702f
+#define MASK_VAMOXORE_V  0xf800707f
+#define MATCH_VAMOANDE_V 0x6000702f
+#define MASK_VAMOANDE_V  0xf800707f
+#define MATCH_VAMOORE_V 0x4000702f
+#define MASK_VAMOORE_V  0xf800707f
+#define MATCH_VAMOMINE_V 0x8000702f
+#define MASK_VAMOMINE_V  0xf800707f
+#define MATCH_VAMOMAXE_V 0xa000702f
+#define MASK_VAMOMAXE_V  0xf800707f
+#define MATCH_VAMOMINUE_V 0xc000702f
+#define MASK_VAMOMINUE_V  0xf800707f
+#define MATCH_VAMOMAXUE_V 0xe000702f
+#define MASK_VAMOMAXUE_V  0xf800707f
+#define MATCH_VMVNFR_V 0x9e003057
+#define MASK_VMVNFR_V  0xfe00707f
 #define CSR_FFLAGS 0x1
 #define CSR_FRM 0x2
 #define CSR_FCSR 0x3
+#define CSR_USTATUS 0x0
+#define CSR_UIE 0x4
+#define CSR_UTVEC 0x5
+#define CSR_VSTART 0x8
+#define CSR_VXSAT 0x9
+#define CSR_VXRM 0xa
+#define CSR_VCSR 0xf
+#define CSR_USCRATCH 0x40
+#define CSR_UEPC 0x41
+#define CSR_UCAUSE 0x42
+#define CSR_UTVAL 0x43
+#define CSR_UIP 0x44
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
 #define CSR_INSTRET 0xc02
@@ -783,7 +1627,12 @@
 #define CSR_HPMCOUNTER29 0xc1d
 #define CSR_HPMCOUNTER30 0xc1e
 #define CSR_HPMCOUNTER31 0xc1f
+#define CSR_VL 0xc20
+#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
 #define CSR_SSTATUS 0x100
+#define CSR_SEDELEG 0x102
+#define CSR_SIDELEG 0x103
 #define CSR_SIE 0x104
 #define CSR_STVEC 0x105
 #define CSR_SCOUNTEREN 0x106
@@ -793,6 +1642,43 @@
 #define CSR_STVAL 0x143
 #define CSR_SIP 0x144
 #define CSR_SATP 0x180
+#define CSR_VSSTATUS 0x200
+#define CSR_VSIE 0x204
+#define CSR_VSTVEC 0x205
+#define CSR_VSSCRATCH 0x240
+#define CSR_VSEPC 0x241
+#define CSR_VSCAUSE 0x242
+#define CSR_VSTVAL 0x243
+#define CSR_VSIP 0x244
+#define CSR_VSATP 0x280
+#define CSR_HSTATUS 0x600
+#define CSR_HEDELEG 0x602
+#define CSR_HIDELEG 0x603
+#define CSR_HIE 0x604
+#define CSR_HTIMEDELTA 0x605
+#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
+#define CSR_HTVAL 0x643
+#define CSR_HIP 0x644
+#define CSR_HVIP 0x645
+#define CSR_HTINST 0x64a
+#define CSR_HGATP 0x680
+#define CSR_HGEIP 0xe12
+#define CSR_UTVT 0x7
+#define CSR_UNXTI 0x45
+#define CSR_UINTSTATUS 0x46
+#define CSR_USCRATCHCSW 0x48
+#define CSR_USCRATCHCSWL 0x49
+#define CSR_STVT 0x107
+#define CSR_SNXTI 0x145
+#define CSR_SINTSTATUS 0x146
+#define CSR_SSCRATCHCSW 0x148
+#define CSR_SSCRATCHCSWL 0x149
+#define CSR_MTVT 0x307
+#define CSR_MNXTI 0x345
+#define CSR_MINTSTATUS 0x346
+#define CSR_MSCRATCHCSW 0x348
+#define CSR_MSCRATCHCSWL 0x349
 #define CSR_MSTATUS 0x300
 #define CSR_MISA 0x301
 #define CSR_MEDELEG 0x302
@@ -800,11 +1686,14 @@
 #define CSR_MIE 0x304
 #define CSR_MTVEC 0x305
 #define CSR_MCOUNTEREN 0x306
+#define CSR_MCOUNTINHIBIT 0x320
 #define CSR_MSCRATCH 0x340
 #define CSR_MEPC 0x341
 #define CSR_MCAUSE 0x342
 #define CSR_MTVAL 0x343
 #define CSR_MIP 0x344
+#define CSR_MTINST 0x34a
+#define CSR_MTVAL2 0x34b
 #define CSR_PMPCFG0 0x3a0
 #define CSR_PMPCFG1 0x3a1
 #define CSR_PMPCFG2 0x3a2
@@ -831,7 +1720,8 @@
 #define CSR_TDATA3 0x7a3
 #define CSR_DCSR 0x7b0
 #define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
 #define CSR_MCYCLE 0xb00
 #define CSR_MINSTRET 0xb02
 #define CSR_MHPMCOUNTER3 0xb03
@@ -896,6 +1786,7 @@
 #define CSR_MARCHID 0xf12
 #define CSR_MIMPID 0xf13
 #define CSR_MHARTID 0xf14
+#define CSR_HTIMEDELTAH 0x615
 #define CSR_CYCLEH 0xc80
 #define CSR_TIMEH 0xc81
 #define CSR_INSTRETH 0xc82
@@ -928,6 +1819,7 @@
 #define CSR_HPMCOUNTER29H 0xc9d
 #define CSR_HPMCOUNTER30H 0xc9e
 #define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MSTATUSH 0x310
 #define CSR_MCYCLEH 0xb80
 #define CSR_MINSTRETH 0xb82
 #define CSR_MHPMCOUNTER3H 0xb83
@@ -976,6 +1868,29 @@
 #define CAUSE_STORE_PAGE_FAULT 0xf
 #endif
 #ifdef DECLARE_INSN
+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO)
+DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE)
 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
@@ -1005,6 +1920,16 @@
 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
 DECLARE_INSN(or, MATCH_OR, MASK_OR)
 DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
@@ -1014,19 +1939,9 @@
 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-DECLARE_INSN(lw, MATCH_LW, MASK_LW)
 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-DECLARE_INSN(sw, MATCH_SW, MASK_SW)
 DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
@@ -1062,20 +1977,6 @@
 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
-DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
-DECLARE_INSN(uret, MATCH_URET, MASK_URET)
-DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
-DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
-DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
-DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
-DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
@@ -1086,6 +1987,26 @@
 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
@@ -1098,6 +2019,26 @@
 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
 DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
 DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
 DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
@@ -1112,76 +2053,47 @@
 DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
 DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
 DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
-DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
 DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
 DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
 DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
-DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
-DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
 DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
 DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
-DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
-DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
-DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
 DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
-DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
-DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
 DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
 DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
-DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
-DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
-DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
-DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
 DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
-DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
 DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
-DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
 DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
 DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
 DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
 DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA)
+DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA)
 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
-DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
@@ -1200,8 +2112,6 @@
 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
-DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
-DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
@@ -1214,6 +2124,20 @@
 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(c_srli_rv32, MATCH_C_SRLI_RV32, MASK_C_SRLI_RV32)
+DECLARE_INSN(c_srai_rv32, MATCH_C_SRAI_RV32, MASK_C_SRAI_RV32)
+DECLARE_INSN(c_slli_rv32, MATCH_C_SLLI_RV32, MASK_C_SLLI_RV32)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ)
+DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ)
+DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP)
+DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP)
 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
@@ -1238,11 +2162,400 @@
 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI)
+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
+DECLARE_INSN(vlb_v, MATCH_VLB_V, MASK_VLB_V)
+DECLARE_INSN(vlh_v, MATCH_VLH_V, MASK_VLH_V)
+DECLARE_INSN(vlw_v, MATCH_VLW_V, MASK_VLW_V)
+DECLARE_INSN(vle_v, MATCH_VLE_V, MASK_VLE_V)
+DECLARE_INSN(vlbu_v, MATCH_VLBU_V, MASK_VLBU_V)
+DECLARE_INSN(vlhu_v, MATCH_VLHU_V, MASK_VLHU_V)
+DECLARE_INSN(vlwu_v, MATCH_VLWU_V, MASK_VLWU_V)
+DECLARE_INSN(vsb_v, MATCH_VSB_V, MASK_VSB_V)
+DECLARE_INSN(vsh_v, MATCH_VSH_V, MASK_VSH_V)
+DECLARE_INSN(vsw_v, MATCH_VSW_V, MASK_VSW_V)
+DECLARE_INSN(vse_v, MATCH_VSE_V, MASK_VSE_V)
+DECLARE_INSN(vlsb_v, MATCH_VLSB_V, MASK_VLSB_V)
+DECLARE_INSN(vlsh_v, MATCH_VLSH_V, MASK_VLSH_V)
+DECLARE_INSN(vlsw_v, MATCH_VLSW_V, MASK_VLSW_V)
+DECLARE_INSN(vlse_v, MATCH_VLSE_V, MASK_VLSE_V)
+DECLARE_INSN(vlsbu_v, MATCH_VLSBU_V, MASK_VLSBU_V)
+DECLARE_INSN(vlshu_v, MATCH_VLSHU_V, MASK_VLSHU_V)
+DECLARE_INSN(vlswu_v, MATCH_VLSWU_V, MASK_VLSWU_V)
+DECLARE_INSN(vssb_v, MATCH_VSSB_V, MASK_VSSB_V)
+DECLARE_INSN(vssh_v, MATCH_VSSH_V, MASK_VSSH_V)
+DECLARE_INSN(vssw_v, MATCH_VSSW_V, MASK_VSSW_V)
+DECLARE_INSN(vsse_v, MATCH_VSSE_V, MASK_VSSE_V)
+DECLARE_INSN(vlxb_v, MATCH_VLXB_V, MASK_VLXB_V)
+DECLARE_INSN(vlxh_v, MATCH_VLXH_V, MASK_VLXH_V)
+DECLARE_INSN(vlxw_v, MATCH_VLXW_V, MASK_VLXW_V)
+DECLARE_INSN(vlxe_v, MATCH_VLXE_V, MASK_VLXE_V)
+DECLARE_INSN(vlxbu_v, MATCH_VLXBU_V, MASK_VLXBU_V)
+DECLARE_INSN(vlxhu_v, MATCH_VLXHU_V, MASK_VLXHU_V)
+DECLARE_INSN(vlxwu_v, MATCH_VLXWU_V, MASK_VLXWU_V)
+DECLARE_INSN(vsxb_v, MATCH_VSXB_V, MASK_VSXB_V)
+DECLARE_INSN(vsxh_v, MATCH_VSXH_V, MASK_VSXH_V)
+DECLARE_INSN(vsxw_v, MATCH_VSXW_V, MASK_VSXW_V)
+DECLARE_INSN(vsxe_v, MATCH_VSXE_V, MASK_VSXE_V)
+DECLARE_INSN(vsuxb_v, MATCH_VSUXB_V, MASK_VSUXB_V)
+DECLARE_INSN(vsuxh_v, MATCH_VSUXH_V, MASK_VSUXH_V)
+DECLARE_INSN(vsuxw_v, MATCH_VSUXW_V, MASK_VSUXW_V)
+DECLARE_INSN(vsuxe_v, MATCH_VSUXE_V, MASK_VSUXE_V)
+DECLARE_INSN(vlbff_v, MATCH_VLBFF_V, MASK_VLBFF_V)
+DECLARE_INSN(vlhff_v, MATCH_VLHFF_V, MASK_VLHFF_V)
+DECLARE_INSN(vlwff_v, MATCH_VLWFF_V, MASK_VLWFF_V)
+DECLARE_INSN(vleff_v, MATCH_VLEFF_V, MASK_VLEFF_V)
+DECLARE_INSN(vlbuff_v, MATCH_VLBUFF_V, MASK_VLBUFF_V)
+DECLARE_INSN(vlhuff_v, MATCH_VLHUFF_V, MASK_VLHUFF_V)
+DECLARE_INSN(vlwuff_v, MATCH_VLWUFF_V, MASK_VLWUFF_V)
+DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V)
+DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V)
+DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF)
+DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF)
+DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF)
+DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF)
+DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF)
+DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF)
+DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF)
+DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF)
+DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF)
+DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F)
+DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM)
+DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F)
+DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF)
+DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF)
+DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF)
+DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF)
+DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF)
+DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF)
+DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF)
+DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF)
+DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF)
+DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF)
+DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF)
+DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF)
+DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF)
+DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF)
+DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF)
+DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF)
+DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF)
+DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF)
+DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF)
+DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF)
+DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF)
+DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF)
+DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF)
+DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF)
+DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF)
+DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF)
+DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF)
+DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV)
+DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS)
+DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV)
+DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS)
+DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV)
+DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS)
+DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV)
+DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS)
+DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV)
+DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV)
+DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV)
+DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S)
+DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV)
+DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV)
+DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV)
+DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV)
+DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV)
+DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV)
+DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV)
+DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV)
+DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV)
+DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV)
+DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV)
+DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV)
+DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV)
+DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV)
+DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V)
+DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V)
+DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V)
+DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V)
+DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V)
+DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V)
+DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V)
+DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V)
+DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V)
+DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V)
+DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V)
+DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V)
+DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V)
+DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W)
+DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W)
+DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W)
+DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W)
+DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W)
+DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W)
+DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W)
+DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W)
+DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V)
+DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V)
+DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV)
+DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS)
+DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV)
+DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS)
+DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV)
+DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV)
+DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV)
+DECLARE_INSN(vfdot_vv, MATCH_VFDOT_VV, MASK_VFDOT_VV)
+DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV)
+DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV)
+DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV)
+DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV)
+DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX)
+DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX)
+DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX)
+DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX)
+DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX)
+DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX)
+DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX)
+DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX)
+DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX)
+DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX)
+DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX)
+DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX)
+DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX)
+DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM)
+DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM)
+DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM)
+DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM)
+DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM)
+DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X)
+DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX)
+DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX)
+DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX)
+DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX)
+DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX)
+DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX)
+DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX)
+DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX)
+DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX)
+DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX)
+DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX)
+DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX)
+DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX)
+DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX)
+DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX)
+DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX)
+DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX)
+DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX)
+DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX)
+DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX)
+DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX)
+DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX)
+DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX)
+DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX)
+DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX)
+DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX)
+DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV)
+DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV)
+DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV)
+DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV)
+DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV)
+DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV)
+DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV)
+DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV)
+DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV)
+DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV)
+DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM)
+DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM)
+DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM)
+DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM)
+DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM)
+DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V)
+DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV)
+DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV)
+DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV)
+DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV)
+DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV)
+DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV)
+DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV)
+DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV)
+DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV)
+DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV)
+DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV)
+DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV)
+DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV)
+DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV)
+DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV)
+DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV)
+DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV)
+DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV)
+DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV)
+DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV)
+DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS)
+DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS)
+DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV)
+DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV)
+DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV)
+DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV)
+DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV)
+DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI)
+DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI)
+DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI)
+DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI)
+DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI)
+DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI)
+DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI)
+DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI)
+DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM)
+DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM)
+DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM)
+DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I)
+DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI)
+DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI)
+DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI)
+DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI)
+DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI)
+DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI)
+DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI)
+DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI)
+DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI)
+DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V)
+DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V)
+DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V)
+DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V)
+DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI)
+DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI)
+DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI)
+DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI)
+DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI)
+DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI)
+DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI)
+DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI)
+DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS)
+DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS)
+DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS)
+DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS)
+DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS)
+DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS)
+DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS)
+DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS)
+DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV)
+DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV)
+DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV)
+DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV)
+DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S)
+DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM)
+DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM)
+DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM)
+DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM)
+DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM)
+DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM)
+DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM)
+DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM)
+DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM)
+DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M)
+DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
+DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)
+DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M)
+DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V)
+DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
+DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
+DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV)
+DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV)
+DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV)
+DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV)
+DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV)
+DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV)
+DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV)
+DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV)
+DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV)
+DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV)
+DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV)
+DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV)
+DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV)
+DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV)
+DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV)
+DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV)
+DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV)
+DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV)
+DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV)
+DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV)
+DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV)
+DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV)
+DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV)
+DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV)
+DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV)
+DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV)
+DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX)
+DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX)
+DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX)
+DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX)
+DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X)
+DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX)
+DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX)
+DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX)
+DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX)
+DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX)
+DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX)
+DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX)
+DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX)
+DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX)
+DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX)
+DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX)
+DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX)
+DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX)
+DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX)
+DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX)
+DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX)
+DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX)
+DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX)
+DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX)
+DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX)
+DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX)
+DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX)
+DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX)
+DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX)
+DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX)
+DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX)
+DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX)
+DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX)
+DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX)
+DECLARE_INSN(vamoswapw_v, MATCH_VAMOSWAPW_V, MASK_VAMOSWAPW_V)
+DECLARE_INSN(vamoaddw_v, MATCH_VAMOADDW_V, MASK_VAMOADDW_V)
+DECLARE_INSN(vamoxorw_v, MATCH_VAMOXORW_V, MASK_VAMOXORW_V)
+DECLARE_INSN(vamoandw_v, MATCH_VAMOANDW_V, MASK_VAMOANDW_V)
+DECLARE_INSN(vamoorw_v, MATCH_VAMOORW_V, MASK_VAMOORW_V)
+DECLARE_INSN(vamominw_v, MATCH_VAMOMINW_V, MASK_VAMOMINW_V)
+DECLARE_INSN(vamomaxw_v, MATCH_VAMOMAXW_V, MASK_VAMOMAXW_V)
+DECLARE_INSN(vamominuw_v, MATCH_VAMOMINUW_V, MASK_VAMOMINUW_V)
+DECLARE_INSN(vamomaxuw_v, MATCH_VAMOMAXUW_V, MASK_VAMOMAXUW_V)
+DECLARE_INSN(vamoswape_v, MATCH_VAMOSWAPE_V, MASK_VAMOSWAPE_V)
+DECLARE_INSN(vamoadde_v, MATCH_VAMOADDE_V, MASK_VAMOADDE_V)
+DECLARE_INSN(vamoxore_v, MATCH_VAMOXORE_V, MASK_VAMOXORE_V)
+DECLARE_INSN(vamoande_v, MATCH_VAMOANDE_V, MASK_VAMOANDE_V)
+DECLARE_INSN(vamoore_v, MATCH_VAMOORE_V, MASK_VAMOORE_V)
+DECLARE_INSN(vamomine_v, MATCH_VAMOMINE_V, MASK_VAMOMINE_V)
+DECLARE_INSN(vamomaxe_v, MATCH_VAMOMAXE_V, MASK_VAMOMAXE_V)
+DECLARE_INSN(vamominue_v, MATCH_VAMOMINUE_V, MASK_VAMOMINUE_V)
+DECLARE_INSN(vamomaxue_v, MATCH_VAMOMAXUE_V, MASK_VAMOMAXUE_V)
+DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V)
 #endif
 #ifdef DECLARE_CSR
 DECLARE_CSR(fflags, CSR_FFLAGS)
 DECLARE_CSR(frm, CSR_FRM)
 DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(ustatus, CSR_USTATUS)
+DECLARE_CSR(uie, CSR_UIE)
+DECLARE_CSR(utvec, CSR_UTVEC)
+DECLARE_CSR(vstart, CSR_VSTART)
+DECLARE_CSR(vxsat, CSR_VXSAT)
+DECLARE_CSR(vxrm, CSR_VXRM)
+DECLARE_CSR(vcsr, CSR_VCSR)
+DECLARE_CSR(uscratch, CSR_USCRATCH)
+DECLARE_CSR(uepc, CSR_UEPC)
+DECLARE_CSR(ucause, CSR_UCAUSE)
+DECLARE_CSR(utval, CSR_UTVAL)
+DECLARE_CSR(uip, CSR_UIP)
 DECLARE_CSR(cycle, CSR_CYCLE)
 DECLARE_CSR(time, CSR_TIME)
 DECLARE_CSR(instret, CSR_INSTRET)
@@ -1275,7 +2588,12 @@
 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(vl, CSR_VL)
+DECLARE_CSR(vtype, CSR_VTYPE)
+DECLARE_CSR(vlenb, CSR_VLENB)
 DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sedeleg, CSR_SEDELEG)
+DECLARE_CSR(sideleg, CSR_SIDELEG)
 DECLARE_CSR(sie, CSR_SIE)
 DECLARE_CSR(stvec, CSR_STVEC)
 DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
@@ -1285,6 +2603,43 @@
 DECLARE_CSR(stval, CSR_STVAL)
 DECLARE_CSR(sip, CSR_SIP)
 DECLARE_CSR(satp, CSR_SATP)
+DECLARE_CSR(vsstatus, CSR_VSSTATUS)
+DECLARE_CSR(vsie, CSR_VSIE)
+DECLARE_CSR(vstvec, CSR_VSTVEC)
+DECLARE_CSR(vsscratch, CSR_VSSCRATCH)
+DECLARE_CSR(vsepc, CSR_VSEPC)
+DECLARE_CSR(vscause, CSR_VSCAUSE)
+DECLARE_CSR(vstval, CSR_VSTVAL)
+DECLARE_CSR(vsip, CSR_VSIP)
+DECLARE_CSR(vsatp, CSR_VSATP)
+DECLARE_CSR(hstatus, CSR_HSTATUS)
+DECLARE_CSR(hedeleg, CSR_HEDELEG)
+DECLARE_CSR(hideleg, CSR_HIDELEG)
+DECLARE_CSR(hie, CSR_HIE)
+DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
+DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
+DECLARE_CSR(hgeie, CSR_HGEIE)
+DECLARE_CSR(htval, CSR_HTVAL)
+DECLARE_CSR(hip, CSR_HIP)
+DECLARE_CSR(hvip, CSR_HVIP)
+DECLARE_CSR(htinst, CSR_HTINST)
+DECLARE_CSR(hgatp, CSR_HGATP)
+DECLARE_CSR(hgeip, CSR_HGEIP)
+DECLARE_CSR(utvt, CSR_UTVT)
+DECLARE_CSR(unxti, CSR_UNXTI)
+DECLARE_CSR(uintstatus, CSR_UINTSTATUS)
+DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW)
+DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL)
+DECLARE_CSR(stvt, CSR_STVT)
+DECLARE_CSR(snxti, CSR_SNXTI)
+DECLARE_CSR(sintstatus, CSR_SINTSTATUS)
+DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW)
+DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL)
+DECLARE_CSR(mtvt, CSR_MTVT)
+DECLARE_CSR(mnxti, CSR_MNXTI)
+DECLARE_CSR(mintstatus, CSR_MINTSTATUS)
+DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW)
+DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL)
 DECLARE_CSR(mstatus, CSR_MSTATUS)
 DECLARE_CSR(misa, CSR_MISA)
 DECLARE_CSR(medeleg, CSR_MEDELEG)
@@ -1292,11 +2647,14 @@
 DECLARE_CSR(mie, CSR_MIE)
 DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT)
 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 DECLARE_CSR(mepc, CSR_MEPC)
 DECLARE_CSR(mcause, CSR_MCAUSE)
 DECLARE_CSR(mtval, CSR_MTVAL)
 DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(mtinst, CSR_MTINST)
+DECLARE_CSR(mtval2, CSR_MTVAL2)
 DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
 DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
 DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
@@ -1323,7 +2681,8 @@
 DECLARE_CSR(tdata3, CSR_TDATA3)
 DECLARE_CSR(dcsr, CSR_DCSR)
 DECLARE_CSR(dpc, CSR_DPC)
-DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
 DECLARE_CSR(mcycle, CSR_MCYCLE)
 DECLARE_CSR(minstret, CSR_MINSTRET)
 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
@@ -1388,6 +2747,7 @@
 DECLARE_CSR(marchid, CSR_MARCHID)
 DECLARE_CSR(mimpid, CSR_MIMPID)
 DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
 DECLARE_CSR(cycleh, CSR_CYCLEH)
 DECLARE_CSR(timeh, CSR_TIMEH)
 DECLARE_CSR(instreth, CSR_INSTRETH)
@@ -1420,6 +2780,7 @@
 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mstatush, CSR_MSTATUSH)
 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
 DECLARE_CSR(minstreth, CSR_MINSTRETH)
 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
diff --git a/src/riscv-tests/env/p/riscv_test.h b/src/riscv-tests/env/p/riscv_test.h
index 3fbcb50..a08f49e 100644
--- a/src/riscv-tests/env/p/riscv_test.h
+++ b/src/riscv-tests/env/p/riscv_test.h
@@ -18,6 +18,11 @@
   RVTEST_FP_ENABLE;                                                     \
   .endm
 
+#define RVTEST_RV64UV                                                   \
+  .macro init;                                                          \
+  RVTEST_VECTOR_ENABLE;                                                 \
+  .endm
+
 #define RVTEST_RV32U                                                    \
   .macro init;                                                          \
   .endm
@@ -27,6 +32,11 @@
   RVTEST_FP_ENABLE;                                                     \
   .endm
 
+#define RVTEST_RV32UV                                                   \
+  .macro init;                                                          \
+  RVTEST_VECTOR_ENABLE;                                                 \
+  .endm
+
 #define RVTEST_RV64M                                                    \
   .macro init;                                                          \
   RVTEST_ENABLE_MACHINE;                                                \
@@ -53,10 +63,44 @@
 # define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
 #endif
 
+#define INIT_XREG                                                       \
+  li x1, 0;                                                             \
+  li x2, 0;                                                             \
+  li x3, 0;                                                             \
+  li x4, 0;                                                             \
+  li x5, 0;                                                             \
+  li x6, 0;                                                             \
+  li x7, 0;                                                             \
+  li x8, 0;                                                             \
+  li x9, 0;                                                             \
+  li x10, 0;                                                            \
+  li x11, 0;                                                            \
+  li x12, 0;                                                            \
+  li x13, 0;                                                            \
+  li x14, 0;                                                            \
+  li x15, 0;                                                            \
+  li x16, 0;                                                            \
+  li x17, 0;                                                            \
+  li x18, 0;                                                            \
+  li x19, 0;                                                            \
+  li x20, 0;                                                            \
+  li x21, 0;                                                            \
+  li x22, 0;                                                            \
+  li x23, 0;                                                            \
+  li x24, 0;                                                            \
+  li x25, 0;                                                            \
+  li x26, 0;                                                            \
+  li x27, 0;                                                            \
+  li x28, 0;                                                            \
+  li x29, 0;                                                            \
+  li x30, 0;                                                            \
+  li x31, 0;
+
 #define INIT_PMP                                                        \
   la t0, 1f;                                                            \
   csrw mtvec, t0;                                                       \
-  li t0, -1;        /* Set up a PMP to permit all accesses */           \
+  /* Set up a PMP to permit all accesses */                             \
+  li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1;             \
   csrw pmpaddr0, t0;                                                    \
   li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X;                             \
   csrw pmpcfg0, t0;                                                     \
@@ -66,16 +110,16 @@
 #define INIT_SATP                                                      \
   la t0, 1f;                                                            \
   csrw mtvec, t0;                                                       \
-  csrwi sptbr, 0;                                                       \
+  csrwi satp, 0;                                                       \
   .align 2;                                                             \
 1:
 
 #define DELEGATE_NO_TRAPS                                               \
+  csrwi mie, 0;                                                         \
   la t0, 1f;                                                            \
   csrw mtvec, t0;                                                       \
   csrwi medeleg, 0;                                                     \
   csrwi mideleg, 0;                                                     \
-  csrwi mie, 0;                                                         \
   .align 2;                                                             \
 1:
 
@@ -94,6 +138,13 @@
   csrs mstatus, a0;                                                     \
   csrwi fcsr, 0
 
+#define RVTEST_VECTOR_ENABLE                                            \
+  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) |                             \
+         (MSTATUS_FS & (MSTATUS_FS >> 1));                              \
+  csrs mstatus, a0;                                                     \
+  csrwi fcsr, 0;                                                        \
+  csrwi vcsr, 0;
+
 #define RISCV_MULTICORE_DISABLE                                         \
   csrr a0, mhartid;                                                     \
   1: bnez a0, 1b
@@ -141,8 +192,9 @@
         sw TESTNUM, tohost, t5;                                         \
         j write_tohost;                                                 \
 reset_vector:                                                           \
+        INIT_XREG;                                                      \
         RISCV_MULTICORE_DISABLE;                                        \
-        INIT_SATP;                                                     \
+        INIT_SATP;                                                      \
         INIT_PMP;                                                       \
         DELEGATE_NO_TRAPS;                                              \
         li TESTNUM, 0;                                                  \
@@ -160,8 +212,6 @@
                (1 << CAUSE_USER_ECALL) |                                \
                (1 << CAUSE_BREAKPOINT);                                 \
         csrw medeleg, t0;                                               \
-        csrr t1, medeleg;                                               \
-        bne t0, t1, other_exception;                                    \
 1:      csrwi mstatus, 0;                                               \
         init;                                                           \
         EXTRA_INIT;                                                     \
@@ -186,6 +236,8 @@
 #define RVTEST_PASS                                                     \
         fence;                                                          \
         li TESTNUM, 1;                                                  \
+        li a7, 93;                                                      \
+        li a0, 0;                                                       \
         ecall
 
 #define TESTNUM gp
@@ -194,6 +246,8 @@
 1:      beqz TESTNUM, 1b;                                               \
         sll TESTNUM, TESTNUM, 1;                                        \
         or TESTNUM, TESTNUM, 1;                                         \
+        li a7, 93;                                                      \
+        addi a0, TESTNUM, 0;                                            \
         ecall
 
 //-----------------------------------------------------------------------
diff --git a/src/riscv-tests/env/v/entry.S b/src/riscv-tests/env/v/entry.S
index 9719662..49b2d3e 100644
--- a/src/riscv-tests/env/v/entry.S
+++ b/src/riscv-tests/env/v/entry.S
@@ -14,17 +14,52 @@
 
   .section ".text.init","ax",@progbits
   .globl _start
+  .align 2
 _start:
   j handle_reset
 
   /* NMI vector */
+  .align 2
 nmi_vector:
   j wtf
 
+  .align 2
 trap_vector:
   j wtf
 
 handle_reset:
+  li x1, 0
+  li x2, 0
+  li x3, 0
+  li x4, 0
+  li x5, 0
+  li x6, 0
+  li x7, 0
+  li x8, 0
+  li x9, 0
+  li x10, 0
+  li x11, 0
+  li x12, 0
+  li x13, 0
+  li x14, 0
+  li x15, 0
+  li x16, 0
+  li x17, 0
+  li x18, 0
+  li x19, 0
+  li x20, 0
+  li x21, 0
+  li x22, 0
+  li x23, 0
+  li x24, 0
+  li x25, 0
+  li x26, 0
+  li x27, 0
+  li x28, 0
+  li x29, 0
+  li x30, 0
+  li x31, 0
+
   la t0, trap_vector
   csrw mtvec, t0
   la sp, STACK_TOP - SIZEOF_TRAPFRAME_T
@@ -32,6 +67,7 @@
   slli t0, t0, 12
   add sp, sp, t0
   csrw mscratch, sp
+  call extra_boot
   la a0, userstart
   j vm_boot
 
@@ -73,6 +109,7 @@
   sret
 
   .global  trap_entry
+  .align 2
 trap_entry:
   csrrw sp, sscratch, sp
 
@@ -116,7 +153,7 @@
   STORE  t0,32*REGBYTES(sp)
   csrr   t0,sepc
   STORE  t0,33*REGBYTES(sp)
-  csrr   t0,sbadaddr
+  csrr   t0,stval
   STORE  t0,34*REGBYTES(sp)
   csrr   t0,scause
   STORE  t0,35*REGBYTES(sp)
diff --git a/src/riscv-tests/env/v/riscv_test.h b/src/riscv-tests/env/v/riscv_test.h
index 8ca9ffd..c74e05d 100644
--- a/src/riscv-tests/env/v/riscv_test.h
+++ b/src/riscv-tests/env/v/riscv_test.h
@@ -12,9 +12,18 @@
 #undef RVTEST_FP_ENABLE
 #define RVTEST_FP_ENABLE fssr x0
 
+#undef RVTEST_VECTOR_ENABLE
+#define RVTEST_VECTOR_ENABLE                                            \
+  csrwi fcsr, 0;                                                        \
+  csrwi vcsr, 0;
+
 #undef RVTEST_CODE_BEGIN
 #define RVTEST_CODE_BEGIN                                               \
         .text;                                                          \
+        .global extra_boot;                                             \
+extra_boot:                                                             \
+        EXTRA_INIT                                                      \
+        ret;                                                            \
         .global userstart;                                              \
 userstart:                                                              \
         init
diff --git a/src/riscv-tests/env/v/vm.c b/src/riscv-tests/env/v/vm.c
index a2e5533..9802fb7 100644
--- a/src/riscv-tests/env/v/vm.c
+++ b/src/riscv-tests/env/v/vm.c
@@ -6,11 +6,19 @@
 
 #include "riscv_test.h"
 
+#if __riscv_xlen == 32
+# define SATP_MODE_CHOICE SATP_MODE_SV32
+#elif defined(Sv48)
+# define SATP_MODE_CHOICE SATP_MODE_SV48
+#else
+# define SATP_MODE_CHOICE SATP_MODE_SV39
+#endif
+
 void trap_entry();
 void pop_tf(trapframe_t*);
 
-volatile uint64_t tohost;
-volatile uint64_t fromhost;
+extern volatile uint64_t tohost;
+extern volatile uint64_t fromhost;
 
 static void do_tohost(uint64_t tohost_value)
 {
@@ -62,13 +70,21 @@
 
 #define l1pt pt[0]
 #define user_l2pt pt[1]
-#if __riscv_xlen == 64
+#if SATP_MODE_CHOICE == SATP_MODE_SV48
+# define NPT 6
+# define kernel_l2pt pt[2]
+# define kernel_l3pt pt[3]
+# define user_l3pt pt[4]
+# define user_llpt pt[5]
+#elif SATP_MODE_CHOICE == SATP_MODE_SV39
 # define NPT 4
-#define kernel_l2pt pt[2]
-# define user_l3pt pt[3]
-#else
+# define kernel_l2pt pt[2]
+# define user_llpt pt[3]
+#elif SATP_MODE_CHOICE == SATP_MODE_SV32
 # define NPT 2
-# define user_l3pt user_l2pt
+# define user_llpt user_l2pt
+#else
+# error Unknown SATP_MODE_CHOICE
 #endif
 pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE)));
 
@@ -100,10 +116,10 @@
   if (node->addr)
   {
     // check accessed and dirty bits
-    assert(user_l3pt[addr/PGSIZE] & PTE_A);
+    assert(user_llpt[addr/PGSIZE] & PTE_A);
     uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
     if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) {
-      assert(user_l3pt[addr/PGSIZE] & PTE_D);
+      assert(user_llpt[addr/PGSIZE] & PTE_D);
       memcpy((void*)addr, uva2kva(addr), PGSIZE);
     }
     write_csr(sstatus, sstatus);
@@ -125,12 +141,12 @@
   assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
   addr = addr/PGSIZE*PGSIZE;
 
-  if (user_l3pt[addr/PGSIZE]) {
-    if (!(user_l3pt[addr/PGSIZE] & PTE_A)) {
-      user_l3pt[addr/PGSIZE] |= PTE_A;
+  if (user_llpt[addr/PGSIZE]) {
+    if (!(user_llpt[addr/PGSIZE] & PTE_A)) {
+      user_llpt[addr/PGSIZE] |= PTE_A;
     } else {
-      assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
-      user_l3pt[addr/PGSIZE] |= PTE_D;
+      assert(!(user_llpt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
+      user_llpt[addr/PGSIZE] |= PTE_D;
     }
     flush_page(addr);
     return;
@@ -143,7 +159,7 @@
     freelist_tail = 0;
 
   uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X;
-  user_l3pt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
+  user_llpt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
   flush_page(addr);
 
   assert(user_mapping[addr/PGSIZE].addr == 0);
@@ -153,10 +169,10 @@
   memcpy((void*)addr, uva2kva(addr), PGSIZE);
   write_csr(sstatus, sstatus);
 
-  user_l3pt[addr/PGSIZE] = new_pte;
+  user_llpt[addr/PGSIZE] = new_pte;
   flush_page(addr);
 
-  __builtin___clear_cache(0,0);
+  asm volatile ("fence.i");
 }
 
 void handle_trap(trapframe_t* tf)
@@ -194,7 +210,7 @@
 static void coherence_torture()
 {
   // cause coherence misses without affecting program semantics
-  unsigned int random = ENTROPY;
+  uint64_t random = ENTROPY;
   while (1) {
     uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4);
 #ifdef __riscv_atomic
@@ -209,7 +225,7 @@
 
 void vm_boot(uintptr_t test_addr)
 {
-  unsigned int random = ENTROPY;
+  uint64_t random = ENTROPY;
   if (read_csr(mhartid) > 0)
     coherence_torture();
 
@@ -221,27 +237,38 @@
   // map user to lowermost megapage
   l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
   // map kernel to uppermost megapage
-#if __riscv_xlen == 64
+#if SATP_MODE_CHOICE == SATP_MODE_SV48
+  l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  kernel_l2pt[PTES_PER_PT-1] = ((pte_t)kernel_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  kernel_l3pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
+  user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  user_l3pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+#elif SATP_MODE_CHOICE == SATP_MODE_SV39
   l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
   kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
-  user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
-  uintptr_t vm_choice = SATP_MODE_SV39;
-#else
+  user_l2pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+#elif SATP_MODE_CHOICE == SATP_MODE_SV32
   l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
-  uintptr_t vm_choice = SATP_MODE_SV32;
+#else
+# error
 #endif
-  write_csr(sptbr, ((uintptr_t)l1pt >> PGSHIFT) |
-                   (vm_choice * (SATP_MODE & ~(SATP_MODE<<1))));
+  uintptr_t vm_choice = SATP_MODE_CHOICE;
+  uintptr_t satp_value = ((uintptr_t)l1pt >> PGSHIFT)
+                        | (vm_choice * (SATP_MODE & ~(SATP_MODE<<1)));
+  write_csr(satp, satp_value);
+  if (read_csr(satp) != satp_value)
+    assert(!"unsupported satp mode");
 
   // Set up PMPs if present, ignoring illegal instruction trap if not.
   uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
+  uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1;
   asm volatile ("la t0, 1f\n\t"
                 "csrrw t0, mtvec, t0\n\t"
                 "csrw pmpaddr0, %1\n\t"
                 "csrw pmpcfg0, %0\n\t"
                 ".align 2\n\t"
-                "1:"
-                : : "r" (pmpc), "r" (-1UL) : "t0");
+                "1: csrw mtvec, t0"
+                : : "r" (pmpc), "r" (pmpa) : "t0");
 
   // set up supervisor trap handling
   write_csr(stvec, pa2kva(trap_entry));
@@ -251,8 +278,8 @@
     (1 << CAUSE_FETCH_PAGE_FAULT) |
     (1 << CAUSE_LOAD_PAGE_FAULT) |
     (1 << CAUSE_STORE_PAGE_FAULT));
-  // FPU on; accelerator on; allow supervisor access to user memory access
-  write_csr(mstatus, MSTATUS_FS | MSTATUS_XS);
+  // FPU on; accelerator on; vector unit on
+  write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_VS);
   write_csr(mie, 0);
 
   random = 1 + (random % MAX_TEST_PAGES);
diff --git a/src/riscv-tests/isa/Makefile b/src/riscv-tests/isa/Makefile
index 4e1ba20..a514cb2 100644
--- a/src/riscv-tests/isa/Makefile
+++ b/src/riscv-tests/isa/Makefile
@@ -13,7 +13,9 @@
 include $(src_dir)/rv64ua/Makefrag
 include $(src_dir)/rv64uf/Makefrag
 include $(src_dir)/rv64ud/Makefrag
+include $(src_dir)/rv64uzfh/Makefrag
 include $(src_dir)/rv64si/Makefrag
+include $(src_dir)/rv64ssvnapot/Makefrag
 include $(src_dir)/rv64mi/Makefrag
 endif
 include $(src_dir)/rv32ui/Makefrag
@@ -22,6 +24,7 @@
 include $(src_dir)/rv32ua/Makefrag
 include $(src_dir)/rv32uf/Makefrag
 include $(src_dir)/rv32ud/Makefrag
+include $(src_dir)/rv32uzfh/Makefrag
 include $(src_dir)/rv32si/Makefrag
 include $(src_dir)/rv32mi/Makefrag
 
@@ -67,7 +70,11 @@
 
 .PHONY: $(1)
 
+COMPILER_SUPPORTS_$(1) := $$(shell $$(RISCV_GCC) $(2) -c -x c /dev/null -o /dev/null 2> /dev/null; echo $$$$?)
+
+ifeq ($$(COMPILER_SUPPORTS_$(1)),0)
 tests += $$($(1)_tests)
+endif
 
 endef
 
@@ -77,6 +84,7 @@
 $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32))
 $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32))
 ifeq ($(XLEN),64)
@@ -86,14 +94,16 @@
 $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64))
 $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64mi,-march=rv64g -mabi=lp64))
 endif
 
 tests_dump = $(addsuffix .dump, $(tests))
 tests_hex = $(addsuffix .hex, $(tests))
-tests_out = $(addsuffix .out, $(spike_tests))
-tests32_out = $(addsuffix .out32, $(spike32_tests))
+tests_out = $(addsuffix .out, $(filter rv64%,$(tests)))
+tests32_out = $(addsuffix .out32, $(filter rv32%,$(tests)))
 
 run: $(tests_out) $(tests32_out)
 
diff --git a/src/riscv-tests/isa/macros/scalar/test_macros.h b/src/riscv-tests/isa/macros/scalar/test_macros.h
index ed4cab0..a8a78a7 100644
--- a/src/riscv-tests/isa/macros/scalar/test_macros.h
+++ b/src/riscv-tests/isa/macros/scalar/test_macros.h
@@ -374,11 +374,35 @@
 # Tests floating-point instructions
 #-----------------------------------------------------------------------
 
+#define qNaNh 0h:7e00
+#define sNaNh 0h:7c01
 #define qNaNf 0f:7fc00000
 #define sNaNf 0f:7f800001
 #define qNaN 0d:7ff8000000000000
 #define sNaN 0d:7ff0000000000001
 
+#define TEST_FP_OP_H_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  flh f0, 0(a0); \
+  flh f1, 2(a0); \
+  flh f2, 4(a0); \
+  lh  a3, 6(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  .pushsection .data; \
+  .align 1; \
+  test_ ## testnum ## _data: \
+  .float16 val1; \
+  .float16 val2; \
+  .float16 val3; \
+  .result; \
+  .popsection
+
 #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
 test_ ## testnum: \
   li  TESTNUM, testnum; \
@@ -460,6 +484,19 @@
   TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
                     fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
 
+#define TEST_FCVT_H_S( testnum, result, val1 ) \
+  TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \
+                    fcvt.s.h f3, f0; fcvt.h.s f3, f3; fmv.x.h a0, f3)
+
+#define TEST_FCVT_H_D( testnum, result, val1 ) \
+  TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \
+                    fcvt.d.h f3, f0; fcvt.h.d f3, f3; fmv.x.h a0, f3)
+
+
+#define TEST_FP_OP1_H( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.h a0, f3;)
+
 #define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
   TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
                     inst f3, f0; fmv.x.s a0, f3)
@@ -477,6 +514,10 @@
   TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
                     inst f3, f0; fmv.x.s a0, f3)
 
+#define TEST_FP_OP1_H_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.h a0, f3)
+
 #define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
   TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
                     inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
@@ -490,6 +531,10 @@
   TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
                     inst f3, f0, f1; fmv.x.s a0, f3)
 
+#define TEST_FP_OP2_H( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.h a0, f3)
+
 #define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
   TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
                     inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
@@ -503,6 +548,10 @@
   TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
                     inst f3, f0, f1, f2; fmv.x.s a0, f3)
 
+#define TEST_FP_OP3_H( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.h a0, f3)
+
 #define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
   TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
                     inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
@@ -516,6 +565,10 @@
   TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
                     inst a0, f0, rm)
 
+#define TEST_FP_INT_OP_H( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
 #define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
   TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
                     inst a0, f0, f1; li t2, 0)
@@ -528,6 +581,10 @@
   TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
                     inst a0, f0, f1)
 
+#define TEST_FP_CMP_OP_H( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
 #define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
   TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
                     inst a0, f0, f1; li t2, 0)
@@ -571,6 +628,22 @@
   .float result; \
   .popsection
 
+#define TEST_INT_FP_OP_H( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  lh  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.h a0, f0; \
+  bne a0, a3, fail; \
+  .pushsection .data; \
+  .align 1; \
+  test_ ## testnum ## _data: \
+  .float16 result; \
+  .popsection
+
 #define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
 test_ ## testnum: \
   li  TESTNUM, testnum; \
diff --git a/src/riscv-tests/isa/rv32mi/Makefrag b/src/riscv-tests/isa/rv32mi/Makefrag
index 5ee7edc..2142570 100644
--- a/src/riscv-tests/isa/rv32mi/Makefrag
+++ b/src/riscv-tests/isa/rv32mi/Makefrag
@@ -14,5 +14,3 @@
 	shamt \
 
 rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests))
-
-spike32_tests += $(rv32mi_p_tests)
diff --git a/src/riscv-tests/isa/rv32mi/shamt.S b/src/riscv-tests/isa/rv32mi/shamt.S
index 622fde4..c4d154c 100644
--- a/src/riscv-tests/isa/rv32mi/shamt.S
+++ b/src/riscv-tests/isa/rv32mi/shamt.S
@@ -21,6 +21,7 @@
 
   TEST_PASSFAIL
 
+.align 2
 .global mtvec_handler
 mtvec_handler:
   # Trapping on test 3 is good.
diff --git a/src/riscv-tests/isa/rv32si/Makefrag b/src/riscv-tests/isa/rv32si/Makefrag
index f423788..1392c24 100644
--- a/src/riscv-tests/isa/rv32si/Makefrag
+++ b/src/riscv-tests/isa/rv32si/Makefrag
@@ -11,5 +11,3 @@
 	wfi \
 
 rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
-
-spike32_tests += $(rv32si_p_tests)
diff --git a/src/riscv-tests/isa/rv32ua/Makefrag b/src/riscv-tests/isa/rv32ua/Makefrag
index 575dc6a..3f35810 100644
--- a/src/riscv-tests/isa/rv32ua/Makefrag
+++ b/src/riscv-tests/isa/rv32ua/Makefrag
@@ -8,5 +8,3 @@
 
 rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests))
 rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests))
-
-spike32_tests += $(rv32ua_p_tests) $(rv32ua_v_tests)
diff --git a/src/riscv-tests/isa/rv32uc/Makefrag b/src/riscv-tests/isa/rv32uc/Makefrag
index 0586843..674ece8 100644
--- a/src/riscv-tests/isa/rv32uc/Makefrag
+++ b/src/riscv-tests/isa/rv32uc/Makefrag
@@ -7,5 +7,3 @@
 
 rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests))
 rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests))
-
-spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests)
diff --git a/src/riscv-tests/isa/rv32ud/Makefrag b/src/riscv-tests/isa/rv32ud/Makefrag
index 998078d..1a38cec 100644
--- a/src/riscv-tests/isa/rv32ud/Makefrag
+++ b/src/riscv-tests/isa/rv32ud/Makefrag
@@ -11,5 +11,3 @@
 
 rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests))
 rv32ud_v_tests = $(addprefix rv32ud-v-, $(rv32ud_sc_tests))
-
-spike32_tests += $(rv32ud_p_tests) $(rv32ud_v_tests)
diff --git a/src/riscv-tests/isa/rv32uf/Makefrag b/src/riscv-tests/isa/rv32uf/Makefrag
index 7dde664..e82705f 100644
--- a/src/riscv-tests/isa/rv32uf/Makefrag
+++ b/src/riscv-tests/isa/rv32uf/Makefrag
@@ -8,5 +8,3 @@
 
 rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests))
 rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests))
-
-spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests)
diff --git a/src/riscv-tests/isa/rv32ui/Makefrag b/src/riscv-tests/isa/rv32ui/Makefrag
index 7903b15..48a3a91 100644
--- a/src/riscv-tests/isa/rv32ui/Makefrag
+++ b/src/riscv-tests/isa/rv32ui/Makefrag
@@ -23,5 +23,3 @@
 
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
 rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
-
-spike32_tests += $(rv32ui_p_tests) $(rv32ui_v_tests)
diff --git a/src/riscv-tests/isa/rv32um/Makefrag b/src/riscv-tests/isa/rv32um/Makefrag
index 1391c6a..688cb5a 100644
--- a/src/riscv-tests/isa/rv32um/Makefrag
+++ b/src/riscv-tests/isa/rv32um/Makefrag
@@ -9,5 +9,3 @@
 
 rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))
 rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests))
-
-spike32_tests += $(rv32um_p_tests) $(rv32um_v_tests)
diff --git a/src/riscv-tests/isa/rv32uzfh/Makefrag b/src/riscv-tests/isa/rv32uzfh/Makefrag
new file mode 100644
index 0000000..f24cdf2
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/Makefrag
@@ -0,0 +1,10 @@
+#=======================================================================
+# Makefrag for rv32uzfh tests
+#-----------------------------------------------------------------------
+
+rv32uzfh_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+	ldst move recoding \
+
+rv32uzfh_p_tests = $(addprefix rv32uzfh-p-, $(rv32uzfh_sc_tests))
+rv32uzfh_v_tests = $(addprefix rv32uzfh-v-, $(rv32uzfh_sc_tests))
diff --git a/src/riscv-tests/isa/rv32uzfh/fadd.S b/src/riscv-tests/isa/rv32uzfh/fadd.S
new file mode 100644
index 0000000..11dba9d
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fadd.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fclass.S b/src/riscv-tests/isa/rv32uzfh/fclass.S
new file mode 100644
index 0000000..b1fcf24
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fclass.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fclass.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fcmp.S b/src/riscv-tests/isa/rv32uzfh/fcmp.S
new file mode 100644
index 0000000..9793dea
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fcmp.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fcmp.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fcvt.S b/src/riscv-tests/isa/rv32uzfh/fcvt.S
new file mode 100644
index 0000000..2b5bf5a
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fcvt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uzfh/fcvt.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fcvt_w.S b/src/riscv-tests/isa/rv32uzfh/fcvt_w.S
new file mode 100644
index 0000000..d532b35
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fcvt_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uzfh/fcvt_w.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fdiv.S b/src/riscv-tests/isa/rv32uzfh/fdiv.S
new file mode 100644
index 0000000..2bf43a7
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fdiv.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fdiv.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fmadd.S b/src/riscv-tests/isa/rv32uzfh/fmadd.S
new file mode 100644
index 0000000..2a5ea91
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fmadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fmadd.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fmin.S b/src/riscv-tests/isa/rv32uzfh/fmin.S
new file mode 100644
index 0000000..360e02f
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fmin.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fmin.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/ldst.S b/src/riscv-tests/isa/rv32uzfh/ldst.S
new file mode 100644
index 0000000..7f09872
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0xcafe4000, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); lw a0, 20(a1))
+  TEST_CASE(3, a0, 0xabadbf80, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); lw a0, 24(a1))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf80bf80
+.word 0x40004000
+.word 0x40404040
+.word 0xc080c080
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv32uzfh/move.S b/src/riscv-tests/isa/rv32uzfh/move.S
new file mode 100644
index 0000000..b399a76
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/move.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/move.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/recoding.S b/src/riscv-tests/isa/rv32uzfh/recoding.S
new file mode 100644
index 0000000..271a5cb
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/recoding.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/recoding.S"
diff --git a/src/riscv-tests/isa/rv64mi/Makefrag b/src/riscv-tests/isa/rv64mi/Makefrag
index c81c24e..645622b 100644
--- a/src/riscv-tests/isa/rv64mi/Makefrag
+++ b/src/riscv-tests/isa/rv64mi/Makefrag
@@ -14,5 +14,3 @@
 	sbreak \
 
 rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests))
-
-spike_tests += $(rv64mi_p_tests)
diff --git a/src/riscv-tests/isa/rv64mi/illegal.S b/src/riscv-tests/isa/rv64mi/illegal.S
index 5531570..fb6643b 100644
--- a/src/riscv-tests/isa/rv64mi/illegal.S
+++ b/src/riscv-tests/isa/rv64mi/illegal.S
@@ -59,14 +59,18 @@
 1:
   # Make sure WFI doesn't trap when TW=0.
   wfi
-bad3:
-  .word 0
-  j fail
 
-bad4:
-  # Make sure WFI does trap when TW=1.
-  wfi
-  j fail
+  # Check if paging is supported (Set SUM & MXR and read it back)
+  and t0, t0, zero
+  li t0, (SSTATUS_SUM | SSTATUS_MXR)
+  csrc sstatus, t0
+  and t1, t1, zero
+  li t1, (SSTATUS_SUM | SSTATUS_MXR) 
+  csrs sstatus, t1
+  csrr t2, sstatus
+  and t2, t2, t0
+  beqz t2, bare_s_1
+  csrc sstatus, t0
 
   # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
   sfence.vma
@@ -83,6 +87,7 @@
   csrr t0, sptbr
   j fail
 
+test_tsr:
   # Make sure SRET doesn't trap when TSR=0.
   la t0, bad8
   csrw sepc, t0
@@ -102,7 +107,26 @@
   sret
 1:
   j fail
+  j skip_bare_s
 
+bare_s_1:
+  # Make sure SFENCE.VMA trap when TVM=0.
+  sfence.vma
+  j fail
+
+bare_s_2:
+  # Set TVM=1. TVM should stay 0 and SFENCE.VMA should still trap 
+  sfence.vma
+  j fail
+
+  # And access to satp should not trap
+  csrr t0, sptbr
+bare_s_3:
+  .word 0
+  j fail
+  j test_tsr
+
+skip_bare_s:
   TEST_PASSFAIL
 
   .align 8
@@ -144,10 +168,6 @@
 
   la t1, bad2
   beq t0, t1, 2f
-  la t1, bad3
-  beq t0, t1, 3f
-  la t1, bad4
-  beq t0, t1, 4f
   la t1, bad5
   beq t0, t1, 5f
   la t1, bad6
@@ -158,20 +178,20 @@
   beq t0, t1, 8f
   la t1, bad9
   beq t0, t1, 9f
+  la t1, bare_s_1
+  beq t0, t1, 5f
+  la t1, bare_s_2
+  beq t0, t1, 7f
+  la t1, bare_s_3
+  beq t0, t1, 7f
   j fail
 2:
-4:
 6:
 7:
   addi t0, t0, 8
   csrw mepc, t0
   mret
 
-3:
-  li t1, MSTATUS_TW
-  csrs mstatus, t1
-  j 2b
-
 5:
   li t1, MSTATUS_TVM
   csrs mstatus, t1
diff --git a/src/riscv-tests/isa/rv64mi/mcsr.S b/src/riscv-tests/isa/rv64mi/mcsr.S
index e0256e7..03cf29a 100644
--- a/src/riscv-tests/isa/rv64mi/mcsr.S
+++ b/src/riscv-tests/isa/rv64mi/mcsr.S
@@ -28,7 +28,7 @@
   csrr a0, marchid
   csrr a0, mvendorid
 
-  # Check that writing hte following CSRs doesn't cause an exception
+  # Check that writing the following CSRs doesn't cause an exception
   li t0, 0
   csrs mtvec, t0
   csrs mepc, t0
diff --git a/src/riscv-tests/isa/rv64si/Makefrag b/src/riscv-tests/isa/rv64si/Makefrag
index f01a332..604005c 100644
--- a/src/riscv-tests/isa/rv64si/Makefrag
+++ b/src/riscv-tests/isa/rv64si/Makefrag
@@ -12,5 +12,3 @@
 	sbreak \
 
 rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests))
-
-spike_tests += $(rv64si_p_tests)
diff --git a/src/riscv-tests/isa/rv64si/csr.S b/src/riscv-tests/isa/rv64si/csr.S
index 09494ef..0ba1e1f 100644
--- a/src/riscv-tests/isa/rv64si/csr.S
+++ b/src/riscv-tests/isa/rv64si/csr.S
@@ -46,8 +46,17 @@
 #endif
 #endif
 
+  # Make sure reading the cycle counter in four ways doesn't trap.
+#ifdef __MACHINE_MODE
+  TEST_CASE(25, x0, 0, csrrc  x0, cycle, x0);
+  TEST_CASE(26, x0, 0, csrrs  x0, cycle, x0);
+  TEST_CASE(27, x0, 0, csrrci x0, cycle, 0);
+  TEST_CASE(28, x0, 0, csrrsi x0, cycle, 0);
+#endif
+
   TEST_CASE(20, a0,         0, csrw sscratch, zero; csrr a0, sscratch);
   TEST_CASE(21, a0,         0, csrrwi a0, sscratch, 0; csrrwi a0, sscratch, 0xF);
+  TEST_CASE(22, a0,      0x1f, csrrsi x0, sscratch, 0x10; csrr a0, sscratch);
 
   csrwi sscratch, 3
   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
@@ -86,6 +95,19 @@
   srli a0, a0, 20 # a0 = a0 >> 20
   andi a0, a0, 1  # a0 = a0 & 1
   beqz a0, finish # if no user mode, skip the rest of these checks
+
+  # Enable access to the cycle counter
+  csrwi mcounteren, 1
+
+  # Figure out if 'S' is set in misa
+  csrr a0, misa   # a0 = csr(misa)
+  srli a0, a0, 18 # a0 = a0 >> 20
+  andi a0, a0, 1  # a0 = a0 & 1
+  beqz a0, 1f
+
+  # Enable access to the cycle counter
+  csrwi scounteren, 1
+1:
 #endif /* __MACHINE_MODE */
 
   # jump to user land
diff --git a/src/riscv-tests/isa/rv64si/sbreak.S b/src/riscv-tests/isa/rv64si/sbreak.S
index 31efff8..475bf65 100644
--- a/src/riscv-tests/isa/rv64si/sbreak.S
+++ b/src/riscv-tests/isa/rv64si/sbreak.S
@@ -17,6 +17,7 @@
   #define sscratch mscratch
   #define sstatus mstatus
   #define scause mcause
+  #define stvec mtvec
   #define sepc mepc
   #define sret mret
   #define stvec_handler mtvec_handler
@@ -35,6 +36,13 @@
 stvec_handler:
   li t1, CAUSE_BREAKPOINT
   csrr t0, scause
+  # Check if CLIC mode
+  csrr t2, stvec
+  andi t2, t2, 2
+  # Skip masking if non-CLIC mode
+  beqz t2, skip_mask 
+  andi t0, t0, 255
+skip_mask:
   bne t0, t1, fail
   la t1, do_break
   csrr t0, sepc
diff --git a/src/riscv-tests/isa/rv64si/scall.S b/src/riscv-tests/isa/rv64si/scall.S
index 9956e03..eb6f1e6 100644
--- a/src/riscv-tests/isa/rv64si/scall.S
+++ b/src/riscv-tests/isa/rv64si/scall.S
@@ -17,6 +17,7 @@
   #define sscratch mscratch
   #define sstatus mstatus
   #define scause mcause
+  #define stvec mtvec
   #define sepc mepc
   #define sret mret
   #define stvec_handler mtvec_handler
@@ -67,6 +68,13 @@
   .global stvec_handler
 stvec_handler:
   csrr t0, scause
+  # Check if CLIC mode
+  csrr t2, stvec
+  andi t2, t2, 2
+  # Skip masking if non-CLIC mode
+  beqz t2, skip_mask 
+  andi t0, t0, 255
+skip_mask:
   bne t0, t1, fail
   la t2, do_scall
   csrr t0, sepc
diff --git a/src/riscv-tests/isa/rv64ssvnapot/Makefrag b/src/riscv-tests/isa/rv64ssvnapot/Makefrag
new file mode 100644
index 0000000..79e1f2a
--- /dev/null
+++ b/src/riscv-tests/isa/rv64ssvnapot/Makefrag
@@ -0,0 +1,8 @@
+#=======================================================================
+# Makefrag for rv64ssvnapot tests
+#-----------------------------------------------------------------------
+
+rv64ssvnapot_sc_tests = \
+	napot \
+
+rv64ssvnapot_p_tests = $(addprefix rv64ssvnapot-p-, $(rv64ssvnapot_sc_tests))
diff --git a/src/riscv-tests/isa/rv64ssvnapot/napot.S b/src/riscv-tests/isa/rv64ssvnapot/napot.S
new file mode 100644
index 0000000..92d2b49
--- /dev/null
+++ b/src/riscv-tests/isa/rv64ssvnapot/napot.S
@@ -0,0 +1,172 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# napot.S
+#-----------------------------------------------------------------------------
+#
+# Test Svnapot
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+#if (DRAM_BASE >> 30 << 30) != DRAM_BASE
+# error This test requires DRAM_BASE be SV39 superpage-aligned
+#endif
+
+#if __riscv_xlen != 64
+# error This test requires RV64
+#endif
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # Construct the page table
+
+#define MY_VA 0x40201010
+  # VPN 2 == VPN 1 == VPN 0 == 0x1
+  # Page offset == 0x10
+
+  ####
+
+  # Level 0 PTE contents
+
+  # PPN
+  la a0, my_data
+  srl a0, a0, 12
+
+  # adjust the PPN to be in NAPOT form
+  li a1, ~0xF
+  and a0, a0, a1
+  ori a0, a0, 0x8
+
+  # attributes
+  sll a0, a0, PTE_PPN_SHIFT
+  li a1, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D | PTE_N
+  or a0, a0, a1
+
+  # Level 0 PTE address
+  la a1, page_table
+  addi a1, a1, ((MY_VA >> 12) & 0x1FF) * 8
+
+  # Level 0 PTE store
+  sd a0, (a1)
+
+  ####
+
+  # Level 1 PTE contents
+  la a0, page_table
+  srl a0, a0, 12
+  sll a0, a0, PTE_PPN_SHIFT
+  li a1, PTE_V
+  or a0, a0, a1
+
+  # Level 1 PTE address
+  la a1, page_table
+  addi a1, a1, ((MY_VA >> 21) & 0x1FF) * 8
+  li a2, 1 << 12
+  add a1, a1, a2
+
+  # Level 1 PTE store
+  sd a0, (a1)
+
+  ####
+
+  # Level 2 PTE contents
+  la a0, page_table
+  li a1, 1 << 12
+  add a0, a0, a1
+  srl a0, a0, 12
+  sll a0, a0, PTE_PPN_SHIFT
+  li a1, PTE_V
+  or a0, a0, a1
+
+  # Level 2 PTE address
+  la a1, page_table
+  addi a1, a1, ((MY_VA >> 30) & 0x1FF) * 8
+  li a2, 2 << 12
+  add a1, a1, a2
+
+  # Level 2 PTE store
+  sd a0, (a1)
+
+  ####
+
+  # Do a load from the PA that would be written if the PTE were misinterpreted as non-NAPOT
+  la a0, my_data
+  li a1, ~0xFFFF
+  and a0, a0, a1
+  li a1, 0x8000 | (MY_VA & 0xFFF)
+  or a3, a0, a1
+  li a1, 0
+  sw a1, (a3)
+
+  ####
+  li TESTNUM, 1
+
+  ## Turn on VM
+  la a1, page_table
+  li a2, 2 << 12
+  add a1, a1, a2
+  srl a1, a1, 12
+  li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
+  or a0, a0, a1
+  csrw satp, a0
+  sfence.vma
+
+  # Set up MPRV with MPP=S and SUM=1, so loads and stores use S-mode and S can access U pages
+  li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV | MSTATUS_SUM
+  csrs mstatus, a1
+
+  # Do a store to MY_VA
+  li a0, MY_VA
+  li a1, 42
+  sw a1, (a0)
+
+  # Clear MPRV
+  li a1, MSTATUS_MPRV
+  csrc mstatus, a1
+
+  # Do a load from the PA that would be written if the PTE were misinterpreted as non-NAPOT
+  lw a1, (a3)
+
+  # Check the result
+  li a0, 42
+  beq a1, a0, die
+
+  # Do a load from the PA for MY_VA
+  la a0, my_data
+  li a1, MY_VA & 0xFFFF
+  add a0, a0, a1
+  lw a1, (a0)
+  li a2, 42
+
+  # Check the result
+  bne a1, a2, die
+
+  ####
+
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  .align 2
+  .global mtvec_handler
+mtvec_handler:
+die:
+  RVTEST_FAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+.align 20
+page_table: .dword 0
+
+.align 20
+my_data: .dword 0
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64ua/Makefrag b/src/riscv-tests/isa/rv64ua/Makefrag
index 3af8856..f0e8ad6 100644
--- a/src/riscv-tests/isa/rv64ua/Makefrag
+++ b/src/riscv-tests/isa/rv64ua/Makefrag
@@ -9,5 +9,3 @@
 
 rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests))
 rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests))
-
-spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests)
diff --git a/src/riscv-tests/isa/rv64ua/lrsc.S b/src/riscv-tests/isa/rv64ua/lrsc.S
index c7589d7..5711f8d 100644
--- a/src/riscv-tests/isa/rv64ua/lrsc.S
+++ b/src/riscv-tests/isa/rv64ua/lrsc.S
@@ -37,14 +37,20 @@
   lw a4, foo; \
 )
 
-# make sure that sc with the wrong reservation fails.
-# TODO is this actually mandatory behavior?
-TEST_CASE( 4, a4, 1, \
-  la a0, foo; \
-  la a1, fooTest3; \
-  lr.w a1, (a1); \
-  sc.w a4, a1, (a0); \
-)
+#
+# Disable test case 4 for now. It assumes a <1K reservation granule, when
+# in reality any size granule is valid. After discussion in issue #315,
+# decided to simply disable the test for now.
+# (See https://github.com/riscv/riscv-tests/issues/315)
+#
+## make sure that sc with the wrong reservation fails.
+## TODO is this actually mandatory behavior?
+#TEST_CASE( 4, a4, 1, \
+#  la a0, foo; \
+#  la a1, fooTest3; \
+#  lr.w a1, (a1); \
+#  sc.w a4, a1, (a0); \
+#)
 
 #define LOG_ITERATIONS 10
 
diff --git a/src/riscv-tests/isa/rv64uc/Makefrag b/src/riscv-tests/isa/rv64uc/Makefrag
index f5e49b7..557ca6c 100644
--- a/src/riscv-tests/isa/rv64uc/Makefrag
+++ b/src/riscv-tests/isa/rv64uc/Makefrag
@@ -7,5 +7,3 @@
 
 rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests))
 rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests))
-
-spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests)
diff --git a/src/riscv-tests/isa/rv64ud/Makefrag b/src/riscv-tests/isa/rv64ud/Makefrag
index 9cffb5d..de456cd 100644
--- a/src/riscv-tests/isa/rv64ud/Makefrag
+++ b/src/riscv-tests/isa/rv64ud/Makefrag
@@ -8,5 +8,3 @@
 
 rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests))
 rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests))
-
-spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests)
diff --git a/src/riscv-tests/isa/rv64ud/structural.S b/src/riscv-tests/isa/rv64ud/structural.S
index 3cf87aa..726275a 100644
--- a/src/riscv-tests/isa/rv64ud/structural.S
+++ b/src/riscv-tests/isa/rv64ud/structural.S
@@ -19,7 +19,9 @@
 li x2, 0x3FF0000000000000
 li x1, 0x3F800000
 
-#define TEST(nops, errcode)     \
+#define TEST(testnum, nops)     \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
   fmv.d.x  f4, x0    ;\
   fmv.s.x  f3, x0    ;\
   fmv.d.x  f2, x2    ;\
@@ -32,21 +34,21 @@
   fmv.x.d  x4, f4    ;\
   fmv.x.s  x5, f3    ;\
   beq     x1, x5, 2f  ;\
-  RVTEST_FAIL ;\
+  j fail;\
 2:beq     x2, x4, 2f  ;\
-  RVTEST_FAIL; \
+  j fail; \
 2:fmv.d.x  f2, zero    ;\
   fmv.s.x  f1, zero    ;\
 
-TEST(;,2)
-TEST(nop,4)
-TEST(nop;nop,6)
-TEST(nop;nop;nop,8)
-TEST(nop;nop;nop;nop,10)
-TEST(nop;nop;nop;nop;nop,12)
-TEST(nop;nop;nop;nop;nop;nop,14)
+TEST(1,;)
+TEST(2,nop)
+TEST(3,nop;nop)
+TEST(4,nop;nop;nop)
+TEST(5,nop;nop;nop;nop)
+TEST(6,nop;nop;nop;nop;nop)
+TEST(7,nop;nop;nop;nop;nop;nop)
 
-RVTEST_PASS
+TEST_PASSFAIL
 
 RVTEST_CODE_END
 
diff --git a/src/riscv-tests/isa/rv64uf/Makefrag b/src/riscv-tests/isa/rv64uf/Makefrag
index 33c11db..2b67905 100644
--- a/src/riscv-tests/isa/rv64uf/Makefrag
+++ b/src/riscv-tests/isa/rv64uf/Makefrag
@@ -8,5 +8,3 @@
 
 rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
 rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
-
-spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests)
diff --git a/src/riscv-tests/isa/rv64ui/Makefrag b/src/riscv-tests/isa/rv64ui/Makefrag
index 1867ea5..b5bf7ba 100644
--- a/src/riscv-tests/isa/rv64ui/Makefrag
+++ b/src/riscv-tests/isa/rv64ui/Makefrag
@@ -23,5 +23,3 @@
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
-
-spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests)
diff --git a/src/riscv-tests/isa/rv64ui/fence_i.S b/src/riscv-tests/isa/rv64ui/fence_i.S
index 2893c5e..e6a6912 100644
--- a/src/riscv-tests/isa/rv64ui/fence_i.S
+++ b/src/riscv-tests/isa/rv64ui/fence_i.S
@@ -24,7 +24,7 @@
 fence.i
 
 la a5, 2f
-jalr a6, a5, 0
+jalr t1, a5, 0
 TEST_CASE( 2, a3, 444, nop )
 
 # test prefetcher hit
@@ -38,7 +38,7 @@
 
 .align 6
 la a5, 3f
-jalr a6, a5, 0
+jalr t1, a5, 0
 TEST_CASE( 3, a3, 777, nop )
 
 TEST_PASSFAIL
@@ -54,9 +54,9 @@
   addi a3, a3, 333
 
 2: addi a3, a3, 222
-jalr a5, a6, 0
+jalr a5, t1, 0
 
 3: addi a3, a3, 555
-jalr a5, a6, 0
+jalr a5, t1, 0
 
 RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64um/Makefrag b/src/riscv-tests/isa/rv64um/Makefrag
index 360bd7a..2a9e66d 100644
--- a/src/riscv-tests/isa/rv64um/Makefrag
+++ b/src/riscv-tests/isa/rv64um/Makefrag
@@ -9,5 +9,3 @@
 
 rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests))
 rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests))
-
-spike_tests += $(rv64um_p_tests) $(rv64um_v_tests)
diff --git a/src/riscv-tests/isa/rv64uzfh/Makefrag b/src/riscv-tests/isa/rv64uzfh/Makefrag
new file mode 100644
index 0000000..af247fd
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/Makefrag
@@ -0,0 +1,10 @@
+#=======================================================================
+# Makefrag for rv64uzfh tests
+#-----------------------------------------------------------------------
+
+rv64uzfh_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+	ldst move recoding \
+
+rv64uzfh_p_tests = $(addprefix rv64uzfh-p-, $(rv64uzfh_sc_tests))
+rv64uzfh_v_tests = $(addprefix rv64uzfh-v-, $(rv64uzfh_sc_tests))
diff --git a/src/riscv-tests/isa/rv64uzfh/fadd.S b/src/riscv-tests/isa/rv64uzfh/fadd.S
new file mode 100644
index 0000000..6ca7f33
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fadd.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f{add|sub|mul}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_H( 2,  fadd.h, 0,                3.5,        2.5,        1.0 );
+  TEST_FP_OP2_H( 3,  fadd.h, 1,              -1234,    -1235.1,        1.1 );
+  TEST_FP_OP2_H( 4,  fadd.h, 1,                3.14,       3.13,      0.01 );
+
+  TEST_FP_OP2_H( 5,  fsub.h, 0,                1.5,        2.5,        1.0 );
+  TEST_FP_OP2_H( 6,  fsub.h, 1,              -1234,    -1235.1,       -1.1 );
+  TEST_FP_OP2_H( 7,  fsub.h, 1,              3.14,        3.15,       0.01 );
+
+  TEST_FP_OP2_H( 8,  fmul.h, 0,                2.5,        2.5,        1.0 );
+  TEST_FP_OP2_H( 9,  fmul.h, 0,             1235.1,    -1235.1,       -1.0 );
+  TEST_FP_OP2_H(10,  fmul.h, 1,                 1.1,      11.0,        0.1 );
+
+  # Is the canonical NaN generated for Inf - Inf?
+  TEST_FP_OP2_H(11,  fsub.h, 0x10, qNaNh, Inf, Inf);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fclass.S b/src/riscv-tests/isa/rv64uzfh/fclass.S
new file mode 100644
index 0000000..86af7e5
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fclass.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  #define TEST_FCLASS_H(testnum, correct, input) \
+    TEST_CASE(testnum, a0, correct, li a0, input; fmv.h.x fa0, a0; \
+                                    fclass.h a0, fa0)
+
+  TEST_FCLASS_H( 2, 1 << 0, 0xfc00 )
+  TEST_FCLASS_H( 3, 1 << 1, 0xbc00 )
+  TEST_FCLASS_H( 4, 1 << 2, 0x83ff )
+  TEST_FCLASS_H( 5, 1 << 3, 0x8000 )
+  TEST_FCLASS_H( 6, 1 << 4, 0x0000 )
+  TEST_FCLASS_H( 7, 1 << 5, 0x03ff )
+  TEST_FCLASS_H( 8, 1 << 6, 0x3c00 )
+  TEST_FCLASS_H( 9, 1 << 7, 0x7c00 )
+  TEST_FCLASS_H(10, 1 << 8, 0x7c01 )
+  TEST_FCLASS_H(11, 1 << 9, 0x7e00 )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fcmp.S b/src/riscv-tests/isa/rv64uzfh/fcmp.S
new file mode 100644
index 0000000..9f8a4e3
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fcmp.S
@@ -0,0 +1,37 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcmp.S
+#-----------------------------------------------------------------------------
+#
+# Test f{eq|lt|le}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_CMP_OP_H( 2, feq.h, 0x00, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_H( 3, fle.h, 0x00, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_H( 4, flt.h, 0x00, 0, -1.36, -1.36)
+
+  TEST_FP_CMP_OP_H( 5, feq.h, 0x00, 0, -1.37, -1.36)
+  TEST_FP_CMP_OP_H( 6, fle.h, 0x00, 1, -1.37, -1.36)
+  TEST_FP_CMP_OP_H( 7, flt.h, 0x00, 1, -1.37, -1.36)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fcvt.S b/src/riscv-tests/isa/rv64uzfh/fcvt.S
new file mode 100644
index 0000000..5f130e1
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fcvt.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt.h.{wu|w|lu|l}, fcvt.h.d, and fcvt.d.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_INT_FP_OP_H( 2,  fcvt.h.w,                   2.0,  2);
+  TEST_INT_FP_OP_H( 3,  fcvt.h.w,                  -2.0, -2);
+
+  TEST_INT_FP_OP_H( 4, fcvt.h.wu,                   2.0,  2);
+  TEST_INT_FP_OP_H( 5, fcvt.h.wu,               0h:7c00, -2);
+
+#if __riscv_xlen >= 64
+  TEST_INT_FP_OP_H( 6,  fcvt.h.l,                   2.0,  2);
+  TEST_INT_FP_OP_H( 7,  fcvt.h.l,                  -2.0, -2);
+
+  TEST_INT_FP_OP_H( 8, fcvt.h.lu,                   2.0,  2);
+  TEST_INT_FP_OP_H( 9, fcvt.h.lu,               0h:7c00, -2);
+#endif
+  
+  TEST_FCVT_H_S( 10, -1.5, -1.5)
+
+#if __riscv_xlen >= 64
+  TEST_FCVT_H_D( 11, -1.5, -1.5)
+#endif
+  
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fcvt_w.S b/src/riscv-tests/isa/rv64uzfh/fcvt_w.S
new file mode 100644
index 0000000..013ecac
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fcvt_w.S
@@ -0,0 +1,104 @@
+# See LICENSE for license details.
+#*****************************************************************************
+# fcvt_w.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt{wu|w|lu|l}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_INT_OP_H( 2,  fcvt.w.h, 0x01,         -1,    -1.1, rtz);
+  TEST_FP_INT_OP_H( 3,  fcvt.w.h, 0x00,         -1,    -1.0, rtz);
+  TEST_FP_INT_OP_H( 4,  fcvt.w.h, 0x01,          0,    -0.9, rtz);
+  TEST_FP_INT_OP_H( 5,  fcvt.w.h, 0x01,          0,     0.9, rtz);
+  TEST_FP_INT_OP_H( 6,  fcvt.w.h, 0x00,          1,     1.0, rtz);
+  TEST_FP_INT_OP_H( 7,  fcvt.w.h, 0x01,          1,     1.1, rtz);
+  TEST_FP_INT_OP_H( 8,  fcvt.w.h, 0x00,      -2054, 0h:e803, rtz);
+  TEST_FP_INT_OP_H( 9,  fcvt.w.h, 0x00,       2054, 0h:6803, rtz);
+
+  TEST_FP_INT_OP_H(12, fcvt.wu.h, 0x10,          0,    -3.0, rtz);
+  TEST_FP_INT_OP_H(13, fcvt.wu.h, 0x10,          0,    -1.0, rtz);
+  TEST_FP_INT_OP_H(14, fcvt.wu.h, 0x01,          0,    -0.9, rtz);
+  TEST_FP_INT_OP_H(15, fcvt.wu.h, 0x01,          0,     0.9, rtz);
+  TEST_FP_INT_OP_H(16, fcvt.wu.h, 0x00,          1,     1.0, rtz);
+  TEST_FP_INT_OP_H(17, fcvt.wu.h, 0x01,          1,     1.1, rtz);
+  TEST_FP_INT_OP_H(18, fcvt.wu.h, 0x10,          0, 0h:e803, rtz);
+  TEST_FP_INT_OP_H(19, fcvt.wu.h, 0x00,       2054, 0h:6803, rtz);
+
+#if __riscv_xlen >= 64
+  TEST_FP_INT_OP_H(22,  fcvt.l.h, 0x01,         -1,    -1.1, rtz);
+  TEST_FP_INT_OP_H(23,  fcvt.l.h, 0x00,         -1,    -1.0, rtz);
+  TEST_FP_INT_OP_H(24,  fcvt.l.h, 0x01,          0,    -0.9, rtz);
+  TEST_FP_INT_OP_H(25,  fcvt.l.h, 0x01,          0,     0.9, rtz);
+  TEST_FP_INT_OP_H(26,  fcvt.l.h, 0x00,          1,     1.0, rtz);
+  TEST_FP_INT_OP_H(27,  fcvt.l.h, 0x01,          1,     1.1, rtz);
+
+  TEST_FP_INT_OP_H(32, fcvt.lu.h, 0x10,          0,    -3.0, rtz);
+  TEST_FP_INT_OP_H(33, fcvt.lu.h, 0x10,          0,    -1.0, rtz);
+  TEST_FP_INT_OP_H(34, fcvt.lu.h, 0x01,          0,    -0.9, rtz);
+  TEST_FP_INT_OP_H(35, fcvt.lu.h, 0x01,          0,     0.9, rtz);
+  TEST_FP_INT_OP_H(36, fcvt.lu.h, 0x00,          1,     1.0, rtz);
+  TEST_FP_INT_OP_H(37, fcvt.lu.h, 0x01,          1,     1.1, rtz);
+  TEST_FP_INT_OP_H(38, fcvt.lu.h, 0x10,          0, 0h:e483, rtz);
+#endif
+
+  # test negative NaN, negative infinity conversion
+  TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.w.h x1, f1)
+  TEST_CASE( 43, x1, 0xffffffff80000000, la x1, tdat  ; flw f1,  8(x1); fcvt.w.h x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE( 44, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.l.h x1, f1)
+  TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat  ; flw f1,  8(x1); fcvt.l.h x1, f1)
+#endif
+
+  # test positive NaN, positive infinity conversion
+  TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.w.h x1, f1)
+  TEST_CASE( 53, x1, 0x000000007fffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.w.h x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE( 54, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.l.h x1, f1)
+  TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.l.h x1, f1)
+#endif
+
+  # test NaN, infinity conversions to unsigned integer
+  TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.wu.h x1, f1)
+  TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.wu.h x1, f1)
+  TEST_CASE( 64, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.wu.h x1, f1)
+  TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.wu.h x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.lu.h x1, f1)
+  TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.lu.h x1, f1)
+  TEST_CASE( 68, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.lu.h x1, f1)
+  TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.lu.h x1, f1)
+#endif
+   
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+# -NaN, NaN, -inf, +inf
+#tdat:
+#.word 0xffffffff
+#.word 0x7fffffff
+#.word 0xff800000
+#.word 0x7f800000
+
+tdat:
+.word 0xffffffff
+.word 0xffff7fff
+.word 0xfffffc00
+.word 0xffff7c00
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fdiv.S b/src/riscv-tests/isa/rv64uzfh/fdiv.S
new file mode 100644
index 0000000..894ebfc
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fdiv.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test f{div|sqrt}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_H(2,  fdiv.h, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
+  TEST_FP_OP2_H(3,  fdiv.h, 1,-0.9991093838555584,      -1234,     1235.1 );
+  TEST_FP_OP2_H(4,  fdiv.h, 0,         3.14159265, 3.14159265,        1.0 );
+
+  TEST_FP_OP1_H(5,  fsqrt.h, 1, 1.7724538498928541, 3.14159265 );
+  TEST_FP_OP1_H(6,  fsqrt.h, 0,                100,      10000 );
+
+  TEST_FP_OP1_H_DWORD_RESULT(7,  fsqrt.h, 0x10, 0x00007e00, -1.0 );
+
+  TEST_FP_OP1_H(8,  fsqrt.h, 1, 13.076696, 171.0);
+
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fmadd.S b/src/riscv-tests/isa/rv64uzfh/fmadd.S
new file mode 100644
index 0000000..2b49763
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fmadd.S
@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f[n]m{add|sub}.h and f[n]m{add|sub}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP3_H( 2,  fmadd.h, 0,                 3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_H( 3,  fmadd.h, 1,                13.2, -1.0,      -12.1,        1.1 );
+  TEST_FP_OP3_H( 4,  fmadd.h, 0,               -12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_H( 5, fnmadd.h, 0,                -3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_H( 6, fnmadd.h, 1,               -13.2, -1.0,      -12.1,        1.1 );
+  TEST_FP_OP3_H( 7, fnmadd.h, 0,                12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_H( 8,  fmsub.h, 0,                 1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_H( 9,  fmsub.h, 1,                  11, -1.0,      -12.1,        1.1 );
+  TEST_FP_OP3_H(10,  fmsub.h, 0,                -8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_H(11, fnmsub.h, 0,                -1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_H(12, fnmsub.h, 1,                 -11, -1.0,      -12.1,        1.1 );
+  TEST_FP_OP3_H(13, fnmsub.h, 0,                 8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fmin.S b/src/riscv-tests/isa/rv64uzfh/fmin.S
new file mode 100644
index 0000000..3feec99
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fmin.S
@@ -0,0 +1,54 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test f{min|max}.h instructinos.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_H( 2,  fmin.h, 0,        1.0,        2.5,        1.0 );
+  TEST_FP_OP2_H( 3,  fmin.h, 0,    -1235.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_H( 4,  fmin.h, 0,    -1235.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_H( 5,  fmin.h, 0,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_H( 6,  fmin.h, 0, 0.00000001, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_H( 7,  fmin.h, 0,       -2.0,       -1.0,       -2.0 );
+
+  TEST_FP_OP2_H(12,  fmax.h, 0,        2.5,        2.5,        1.0 );
+  TEST_FP_OP2_H(13,  fmax.h, 0,        1.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_H(14,  fmax.h, 0,        1.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_H(15,  fmax.h, 0,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_H(16,  fmax.h, 0, 3.14159265, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_H(17,  fmax.h, 0,       -1.0,       -1.0,       -2.0 );
+
+  # FMIN(hNaN, x) = x
+  TEST_FP_OP2_H(20,  fmax.h, 0x10, 1.0, sNaNh, 1.0);
+  # FMIN(hNaN, hNaN) = canonical NaN
+  TEST_FP_OP2_H(21,  fmax.h, 0x00, qNaNh, NaN, NaN);
+
+  # -0.0 < +0.0
+  TEST_FP_OP2_H(30,  fmin.h, 0,       -0.0,       -0.0,        0.0 );
+  TEST_FP_OP2_H(31,  fmin.h, 0,       -0.0,        0.0,       -0.0 );
+  TEST_FP_OP2_H(32,  fmax.h, 0,        0.0,       -0.0,        0.0 );
+  TEST_FP_OP2_H(33,  fmax.h, 0,        0.0,        0.0,       -0.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/ldst.S b/src/riscv-tests/isa/rv64uzfh/ldst.S
new file mode 100644
index 0000000..ff1cdab
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0xcafe1000deadbeef, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); ld a0, 16(a1))
+  TEST_CASE(3, a0, 0x1337d00dabad0001, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); ld a0, 24(a1))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800001
+.word 0x40001000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/move.S b/src/riscv-tests/isa/rv64uzfh/move.S
new file mode 100644
index 0000000..20021df
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/move.S
@@ -0,0 +1,58 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# move.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that the fmv.h.x, fmv.x.h, and fsgnj[x|n].d instructions
+# and the fcsr work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0)
+  TEST_CASE(3, a0, 0x34, frsr a0)
+  TEST_CASE(4, a0, 0x14, frflags a0)
+  TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2)
+  TEST_CASE(6, a0, 0x54, frsr a0)
+  TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4)
+  TEST_CASE(8, a0, 0x50, frsr a0)
+
+#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \
+  TEST_CASE(n, a0, 0x1234 | (-(new_sign) << 15), \
+    li a1, ((rs1_sign) << 15) | 0x1234; \
+    li a2, -(rs2_sign); \
+    fmv.h.x f1, a1; \
+    fmv.h.x f2, a2; \
+    insn f0, f1, f2; \
+    fmv.x.h a0, f0)
+
+  TEST_FSGNJS(10, fsgnj.h, 0, 0, 0)
+  TEST_FSGNJS(11, fsgnj.h, 1, 0, 1)
+  TEST_FSGNJS(12, fsgnj.h, 0, 1, 0)
+  TEST_FSGNJS(13, fsgnj.h, 1, 1, 1)
+
+  TEST_FSGNJS(20, fsgnjn.h, 1, 0, 0)
+  TEST_FSGNJS(21, fsgnjn.h, 0, 0, 1)
+  TEST_FSGNJS(22, fsgnjn.h, 1, 1, 0)
+  TEST_FSGNJS(23, fsgnjn.h, 0, 1, 1)
+
+  TEST_FSGNJS(30, fsgnjx.h, 0, 0, 0)
+  TEST_FSGNJS(31, fsgnjx.h, 1, 0, 1)
+  TEST_FSGNJS(32, fsgnjx.h, 1, 1, 0)
+  TEST_FSGNJS(33, fsgnjx.h, 0, 1, 1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/recoding.S b/src/riscv-tests/isa/rv64uzfh/recoding.S
new file mode 100644
index 0000000..802be66
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/recoding.S
@@ -0,0 +1,46 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# recoding.S
+#-----------------------------------------------------------------------------
+#
+# Test corner cases of John Hauser's microarchitectural recoding scheme.
+# There are twice as many recoded values as IEEE-754 values; some of these
+# extras are redundant (e.g. Inf) and others are illegal (subnormals with
+# too many bits set).
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  # Make sure infinities with different mantissas compare as equal.
+  flw f0, minf, a0
+  flw f1, three, a0
+  fmul.s f1, f1, f0
+  TEST_CASE( 2, a0, 1, feq.s a0, f0, f1)
+  TEST_CASE( 3, a0, 1, fle.s a0, f0, f1)
+  TEST_CASE( 4, a0, 0, flt.s a0, f0, f1)
+
+  # Likewise, but for zeroes.
+  fcvt.s.w f0, x0
+  li a0, 1
+  fcvt.s.w f1, a0
+  fmul.s f1, f1, f0
+  TEST_CASE(5, a0, 1, feq.s a0, f0, f1)
+  TEST_CASE(6, a0, 1, fle.s a0, f0, f1)
+  TEST_CASE(7, a0, 0, flt.s a0, f0, f1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+minf: .float -Inf
+three: .float 3.0
+
+RVTEST_DATA_END