resources: Fix SPEC 2017 gem5 configs
* Revert the MMUbus and itb/dtb port connection change.
This change should not be merged until gem5 v21.0.
* Update the MemCtrl object initialization as the interface
has been change.
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I502e570f913de5239d0ea5f24c02724466e581b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/41556
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/spec-2017/configs/system/caches.py b/src/spec-2017/configs/system/caches.py
index 5b273eb..7cc3d8d 100644
--- a/src/spec-2017/configs/system/caches.py
+++ b/src/spec-2017/configs/system/caches.py
@@ -116,8 +116,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
+ for tlb in [cpu.itb, cpu.dtb]:
+ self.mmubus.cpu_side_ports = tlb.walker.port
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
diff --git a/src/spec-2017/configs/system/system.py b/src/spec-2017/configs/system/system.py
index 1f4642c..12b7880 100644
--- a/src/spec-2017/configs/system/system.py
+++ b/src/spec-2017/configs/system/system.py
@@ -158,13 +158,13 @@
kernel_controller = self._createKernelMemoryController(cls)
ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
self.mem_cntrls = [
- cls(range = ranges[i],
- port = self.membus.mem_side_ports)
+ MemCtrl(dram = cls(range = ranges[i]),
+ port = self.membus.mem_side_ports)
for i in range(num)
] + [kernel_controller]
def _createKernelMemoryController(self, cls):
- return cls(range = self.mem_ranges[0],
- port = self.membus.mem_side_ports)
+ return MemCtrl(dram = cls(range = self.mem_ranges[0]),
+ port = self.membus.mem_side_ports)
def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
from math import log
bits = int(log(num, 2))