diff --git a/src/gapbs/configs/system/caches.py b/src/gapbs/configs/system/caches.py
index 6f82baa..a58f3af 100644
--- a/src/gapbs/configs/system/caches.py
+++ b/src/gapbs/configs/system/caches.py
@@ -118,8 +118,8 @@
         """
         self.mmubus = L2XBar()
         self.cpu_side = self.mmubus.mem_side_ports
-        for tlb in [cpu.itb, cpu.dtb]:
-            self.mmubus.cpu_side_ports = tlb.walker.port
+        cpu.mmu.connectWalkerPorts(
+            self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
 
     def connectBus(self, bus):
         """Connect this cache to a memory-side bus"""
diff --git a/src/parsec/configs/system/caches.py b/src/parsec/configs/system/caches.py
index 497c7e4..4316aa1 100644
--- a/src/parsec/configs/system/caches.py
+++ b/src/parsec/configs/system/caches.py
@@ -114,8 +114,8 @@
         """
         self.mmubus = L2XBar()
         self.cpu_side = self.mmubus.mem_side_ports
-        for tlb in [cpu.itb, cpu.dtb]:
-            self.mmubus.cpu_side_ports = tlb.walker.port
+        cpu.mmu.connectWalkerPorts(
+            self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
 
     def connectBus(self, bus):
         """Connect this cache to a memory-side bus"""