resources: Instructions to run SPEC CPU2017 with gem5 stdlib.
This change updates the README.md for SPEC CPU2017, providing
instructions on how to use gem5 stdlib to simulate SPEC CPU2017.
It also removes the contents of the
gem5-resources/src/spec-2017/configs directory.
Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: I79a31a9af47cfc68e7077a44c72e852f7296ee89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/53446
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby Bruce <bbruce@ucdavis.edu>
diff --git a/src/spec-2017/README.md b/src/spec-2017/README.md
index 4a355c5..ed579e2 100644
--- a/src/spec-2017/README.md
+++ b/src/spec-2017/README.md
@@ -11,8 +11,8 @@
---
This document aims to provide instructions to create a gem5-compatible disk
-image containing the SPEC 2017 benchmark suite and also to provide necessary
-configuration files.
+image containing the SPEC 2017 benchmark suite. It also demonstrates how to
+simulate the SPEC CPU2017 benchmarks using an example configuration script.
## Building the Disk Image
Creating a disk-image for SPEC 2017 requires the benchmark suite ISO file.
@@ -38,10 +38,6 @@
| |___ spec-2017.json # the Packer script
| |___ cpu2017-1.1.0.iso # SPEC 2017 ISO (add here)
|
- |___ configs
- | |___ system/
- | |___ run_spec.py # gem5 run script
- |
|___ vmlinux-4.19.83 # Linux kernel, link to download provided below
|
|___ README.md
@@ -69,106 +65,98 @@
./packer build spec-2017/spec-2017.json
```
-## gem5 Configuration Scripts
-gem5 scripts which configure the system and run the simulation are available
-in `configs/`.
-The main script `run_spec.py` expects following arguments:
+## Simulating SPEC CPU2017 using an example script
-`usage: run_spec.py [-h] [-l] [-z] kernel disk cpu benchmark size`
-
-`-h`: show this help message and exit.
-
-`-l`, `--no-copy-logs`: optional, to not copy SPEC run logs to the host system,
-logs are copied by default, and are available in the result folder.
-
-`-z`, `--allow-listeners`: optional, to turn on GDB listening ports, the ports
-are off by default.
-
-`kernel`: required, a positional argument specifying the path to the Linux
-kernel. This has been tested with version 4.19.83, available at
-<http://dist.gem5.org/dist/v21-1/kernels/x86/static/vmlinux-4.19.83>. Info on
-building Linux kernels can be found in `src/linux-kernels`.
-
-`disk`: required, a positional argument specifying the path to the disk image
-containing SPEC 2017 benchmark suite.
-
-`cpu`: required, a positional argument specifying the name of either a
-detailed CPU model or KVM CPU model.
-
-The available CPU models are,
-
-| cpu | Corresponding CPU model in gem5 |
-| ------ | ------------------------------- |
-| kvm | |
-| o3 | DerivO3CPU |
-| atomic | AtomicSimpleCPU |
-| timing | TimingSimpleCPU |
-
-`benchmark`: required, a positional argument specifying the name of the SPEC
-2017 to run. Listed below are valid options:
-
-* 500.perlbench_r
-* 502.gcc_r
-* 503.bwaves_r
-* 505.mcf_r
-* 507.cactuBSSN_r
-* 508.namd_r
-* 510.parest_r
-* 511.povray_r
-* 519.lbm_r
-* 520.omnetpp_r
-* 521.wrf_r
-* 523.xalancbmk_r
-* 525.x264_r
-* 526.blender_r
-* 527.cam4_r
-* 531.deepsjeng_r
-* 538.imagick_r
-* 541.leela_r
-* 544.nab_r
-* 548.exchange2_r
-* 549.fotonik3d_r
-* 554.roms_r
-* 557.xz_r
-* 600.perlbench_s
-* 602.gcc_s
-* 603.bwaves_s
-* 605.mcf_s
-* 607.cactuBSSN_s
-* 619.lbm_s
-* 620.omnetpp_s
-* 621.wrf_s
-* 623.xalancbmk_s
-* 625.x264_s
-* 627.cam4_s
-* 628.pop2_s
-* 631.deepsjeng_s
-* 638.imagick_s
-* 641.leela_s
-* 644.nab_s
-* 648.exchange2_s
-* 649.fotonik3d_s
-* 654.roms_s
-* 657.xz_s
-* 996.specrand_fs
-* 997.specrand_fr
-* 998.specrand_is
-* 999.specrand_ir
-
-`size`: required, a positional argument specifying the input data size. Valid
-values are `test`, `train`, and `ref`.
-
-As a minimum the following parameters must be specified:
+An example script with a pre-configured system is available in the following directory within the gem5 repository:
```
-<gem5 X86 binary> --outdir <output directory> configs/run_spec.py <kernel> <disk> <cpu> <mem_sys> <benchmark> <size>
+gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
```
-**Note**: `--outdir` is a required argument when running the gem5 binary with SPEC 2006.
+The example script specifies a system with the following parameters:
+* A `SimpleSwitchableProcessor` (`KVM` for startup and `TIMING` for ROI execution). There are 2 CPU cores, each clocked at 3 GHz.
+* 2 Level `MESI_Two_Level` cache with 32 kB L1I and L1D size, and, 256 kB L2 size. The L1 cache(s) has associativity of 8, and, the L2 cache has associativity 16. There are 2 L2 cache banks.
+* The system has 3 GB `SingleChannelDDR4_2400` memory.
+* The script uses `x86-linux-kernel-4.19.83` and the disk image created from following the instructions in this `README.md`.
+* The user inputs the path to the built disk image, along with the root partition.
+* The script then uses `CustomResource` class to use the `spec-2017` disk-image.
+
+The example script must be run with the `X86_MESI_Two_Level` binary. To build:
+
+```sh
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+scons build/X86/gem5.opt -j<proc>
+```
+Once compiled, you may use the example configuration file to run the SPEC CPU2017 benchmark programs using the following command:
+
+```sh
+# In the gem5 directory
+build/X86/gem5.opt \
+configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py \
+--image <path_to_built_spec-2017_disk_image> \
+--partition <root_partition_to_mount> \
+--benchmark <benchmark_program> \
+--size <workload_size>
+```
+
+Description of the four arguments, provided in the above command are:
+* **--image** refers to the full path of the the SPEC CPU2017 disk-image, built using the instructions specified above.
+* **--partition** refers to the root partition of the disk-image to mount. If the disk has no partitions, then pass `--partition ""`. Otherwise, pass an integer specifying the partition number. Set `--partition 1` if the above instructions to build the disk-image are followed.
+* **--benchmark**, which refers to one of 47 benchmark programs, provided in the SPEC CPU2017 Benchmark Suite. For more information on the workloads can be found at <https://www.spec.org/cpu2017/>. The list of benchmark programs include:
+ * 500.perlbench_r
+ * 502.gcc_r
+ * 503.bwaves_r
+ * 505.mcf_r
+ * 507.cactuBSSN_r
+ * 508.namd_r
+ * 510.parest_r
+ * 511.povray_r
+ * 519.lbm_r
+ * 520.omnetpp_r
+ * 521.wrf_r
+ * 523.xalancbmk_r
+ * 525.x264_r
+ * 526.blender_r
+ * 527.cam4_r
+ * 531.deepsjeng_r
+ * 538.imagick_r
+ * 541.leela_r
+ * 544.nab_r
+ * 548.exchange2_r
+ * 549.fotonik3d_r
+ * 554.roms_r
+ * 557.xz_r
+ * 600.perlbench_s
+ * 602.gcc_s
+ * 603.bwaves_s
+ * 605.mcf_s
+ * 607.cactuBSSN_s
+ * 619.lbm_s
+ * 620.omnetpp_s
+ * 621.wrf_s
+ * 623.xalancbmk_s
+ * 625.x264_s
+ * 627.cam4_s
+ * 628.pop2_s
+ * 631.deepsjeng_s
+ * 638.imagick_s
+ * 641.leela_s
+ * 644.nab_s
+ * 648.exchange2_s
+ * 649.fotonik3d_s
+ * 654.roms_s
+ * 657.xz_s
+ * 996.specrand_fs
+ * 997.specrand_fr
+ * 998.specrand_is
+ * 999.specrand_ir
+* **--size**, which refers to the workload size to simulate. Valid choices for `--size` are `test`, `train` and `ref`.
+
+The output directory, where the simulation statistics will be redirected to, will have a new folder named `speclogs_<Day><Month><Date><Hour><Minute><Second>`. The time is of execution is appended to avoid conflicts while coping the files. The output files, generated on the disk-image in the folder `speclogs` will be copied to this aforementioned directory.
## Working Status
Status of these benchmarks runs with respect to gem5-20, linux kernel version
4.19.83 and gcc version 7.5.0 can be found
[here](https://www.gem5.org/documentation/benchmark_status/gem5-20#spec-2017-tests)
-
diff --git a/src/spec-2017/configs/run_spec.py b/src/spec-2017/configs/run_spec.py
deleted file mode 100644
index 63f3934..0000000
--- a/src/spec-2017/configs/run_spec.py
+++ /dev/null
@@ -1,301 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2019 The Regents of the University of California.
-# All rights reserved.
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power, Ayaz Akram, Hoa Nguyen
-
-""" Script to run a SPEC benchmark in full system mode with gem5.
-
- Inputs:
- * This script expects the following as arguments:
- ** kernel:
- This is a positional argument specifying the path to
- vmlinux.
- ** disk:
- This is a positional argument specifying the path to the
- disk image containing the installed SPEC benchmarks.
- ** cpu:
- This is a positional argument specifying the name of the
- detailed CPU model. The names of the available CPU models
- are available in the getDetailedCPUModel(cpu_name) function.
- The function should be modified to add new CPU models.
- Currently, the available CPU models are:
- - kvm: this is not a detailed CPU model, ideal for testing.
- - o3: DerivO3CPU.
- - atomic: AtomicSimpleCPU.
- - timing: TimingSimpleCPU.
- ** benchmark:
- This is a positional argument specifying the name of the
- SPEC benchmark to run. Most SPEC benchmarks are available.
- Please follow this link to check the availability of the
- benchmarks. The working benchmark matrix is near the end
- of the page:
- (SPEC 2006) https://gem5art.readthedocs.io/en/latest/tutorials/spec2006-tutorial.html#appendix-i-working-spec-2006-benchmarks-x-cpu-model-table
- (SPEC 2017) https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html#appendix-i-working-spec-2017-benchmarks-x-cpu-model-table
- ** size:
- This is a positional argument specifying the size of the
- benchmark. The available sizes are: ref, test, train.
- ** --no-copy-logs:
- This is an optional argument specifying the reports of
- the benchmark run is not copied to the output folder.
- The reports are copied by default.
- ** --allow-listeners:
- This is an optional argument specifying gem5 to open GDB
- listening ports. Usually, the ports are opened for debugging
- purposes.
- By default, the ports are off.
-"""
-import os
-
-import m5
-import m5.ticks
-from m5.objects import *
-
-import argparse
-
-from system import *
-
-
-def writeBenchScript(dir, benchmark_name, size, output_path):
- """
- This method creates a script in dir which will be eventually
- passed to the simulated system (to run a specific benchmark
- at bootup).
- """
- input_file_name = '{}/run_{}_{}'.format(dir, benchmark_name, size)
- with open(input_file_name, "w") as f:
- f.write('{} {} {}'.format(benchmark_name, size, output_path))
- return input_file_name
-
-def parse_arguments():
- parser = argparse.ArgumentParser(description=
- "gem5 config file to run SPEC benchmarks")
- parser.add_argument("kernel", type = str, help = "Path to vmlinux")
- parser.add_argument("disk", type = str,
- help = "Path to the disk image containing SPEC benchmarks")
- parser.add_argument("cpu", type = str, help = "Name of the detailed CPU")
- parser.add_argument("mem_sys", type = str, help = "Name of the memory system")
- parser.add_argument("benchmark", type = str,
- help = "Name of the SPEC benchmark")
- parser.add_argument("size", type = str,
- help = "Available sizes: test, train, ref")
- parser.add_argument("-l", "--no-copy-logs", default = False,
- action = "store_true",
- help = "Not to copy SPEC run logs to the host system;"
- "Logs are copied by default")
- parser.add_argument("-z", "--allow-listeners", default = False,
- action = "store_true",
- help = "Turn on ports;"
- "The ports are off by default")
- return parser.parse_args()
-
-def getDetailedCPUModel(cpu_name):
- '''
- Return the CPU model corresponding to the cpu_name.
- '''
- available_models = {"kvm": X86KvmCPU,
- "o3": DerivO3CPU,
- "atomic": AtomicSimpleCPU,
- "timing": TimingSimpleCPU
- }
- try:
- available_models["FlexCPU"] = FlexCPU
- except NameError:
- # FlexCPU is not defined
- pass
- # https://docs.python.org/3/library/stdtypes.html#dict.get
- # dict.get() returns None if the key does not exist
- return available_models.get(cpu_name)
-
-def getBenchmarkName(benchmark_name):
- if benchmark_name.endswith("(base)"):
- benchmark_name = benchmark_name[:-6]
- return benchmark_name
-
-def create_system(linux_kernel_path, disk_image_path, detailed_cpu_model, memory_system):
- # create the system we are going to simulate
- ruby_protocols = [ "MI_example", "MESI_Two_Level", "MOESI_CMP_directory"]
- if memory_system == 'classic':
- system = MySystem(kernel = linux_kernel_path,
- disk = disk_image_path,
- num_cpus = 1, # run the benchmark in a single thread
- no_kvm = False,
- TimingCPUModel = detailed_cpu_model)
- elif memory_system in ruby_protocols:
- system = MyRubySystem(kernel = linux_kernel_path,
- disk = disk_image_path,
- num_cpus = 1, # run the benchmark in a single thread
- mem_sys = memory_system,
- no_kvm = False,
- TimingCPUModel = detailed_cpu_model)
- else:
- m5.fatal("Bad option for mem_sys, should be "
- "{}, or 'classic'".format(', '.join(ruby_protocols)))
-
- # For workitems to work correctly
- # This will cause the simulator to exit simulation when the first work
- # item is reached and when the first work item is finished.
- system.work_begin_exit_count = 1
- system.work_end_exit_count = 1
-
- # set up the root SimObject and start the simulation
- root = Root(full_system = True, system = system)
-
- if system.getHostParallel():
- # Required for running kvm on multiple host cores.
- # Uses gem5's parallel event queue feature
- # Note: The simulator is quite picky about this number!
- root.sim_quantum = int(1e9) # 1 ms
-
- return root, system
-
-
-def boot_linux():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Booting Linux")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while booting linux: {}".format(exit_cause))
- exit(1)
- print("Done booting Linux")
- return success, exit_cause
-
-def run_spec_benchmark():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Start running benchmark")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while running benchmark: {}".format(exit_cause))
- exit(1)
- print("Benchmark done")
- return success, exit_cause
-
-def copy_spec_logs():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Copying SPEC logs")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while copying SPEC log files: {}".format(exit_cause))
- exit(1)
- print("Copying done")
- return success, exit_cause
-
-if __name__ == "__m5_main__":
- args = parse_arguments()
-
- cpu_name = args.cpu
- mem_sys = args.mem_sys
- benchmark_name = getBenchmarkName(args.benchmark)
- benchmark_size = args.size
- linux_kernel_path = args.kernel
- disk_image_path = args.disk
- no_copy_logs = args.no_copy_logs
- allow_listeners = args.allow_listeners
-
- if not no_copy_logs and not os.path.isabs(m5.options.outdir):
- print("Please specify the --outdir (output directory) of gem5"
- " in the form of an absolute path")
- print("An example: build/X86/gem5.opt --outdir /home/user/m5out/"
- " configs-spec-tests/run_spec ...")
- exit(1)
-
- output_dir = os.path.join(m5.options.outdir, "speclogs")
-
- # Get the DetailedCPU class from its name
- detailed_cpu = getDetailedCPUModel(cpu_name)
- if detailed_cpu == None:
- print("'{}' is not define in the config script.".format(cpu_name))
- print("Change getDeatiledCPUModel() in run_spec.py "
- "to add more CPU Models.")
- exit(1)
-
- if not benchmark_size in ["ref", "train", "test"]:
- print("Benchmark size must be one of the following: ref, train, test")
- exit(1)
-
- root, system = create_system(linux_kernel_path, disk_image_path,
- detailed_cpu, mem_sys)
-
- # Create and pass a script to the simulated system to run the required
- # benchmark
- system.readfile = writeBenchScript(m5.options.outdir, benchmark_name,
- benchmark_size, output_dir)
-
- # needed for long running jobs
- if not allow_listeners:
- m5.disableAllListeners()
-
- # instantiate all of the objects we've created above
- m5.instantiate()
-
- # booting linux
- success, exit_cause = boot_linux()
-
- # reset stats
- print("Reset stats")
- m5.stats.reset()
-
- # switch from KVM to detailed CPU
- if not cpu_name == "kvm":
- print("Switching to detailed CPU")
- system.switchCpus(system.cpu, system.detailed_cpu)
- print("Switching done")
-
- # running benchmark
- print("Benchmark: {}; Size: {}".format(benchmark_name, benchmark_size))
- success, exit_cause = run_spec_benchmark()
-
- # output the stats after the benchmark is complete
- print("Output stats")
- m5.stats.dump()
-
- if not no_copy_logs:
- # create the output folder
- if not os.path.exists(output_dir):
- os.makedirs(output_dir)
-
- # switch from detailed CPU to KVM
- if not cpu_name == "kvm":
- print("Switching to KVM")
- system.switchCpus(system.detailed_cpu, system.cpu)
- print("Switching done")
-
- # copying logs
- success, exit_cause = copy_spec_logs()
diff --git a/src/spec-2017/configs/system/MESI_Two_Level.py b/src/spec-2017/configs/system/MESI_Two_Level.py
deleted file mode 100644
index 17df7c0..0000000
--- a/src/spec-2017/configs/system/MESI_Two_Level.py
+++ /dev/null
@@ -1,340 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2020 The Regents of the University of California.
-# All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MESI TWO Level protocol
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MESITwoLevelCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
- fatal("This system assumes MESI_Two_Level!")
-
- super(MESITwoLevelCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MESI_Two_Level example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU core.
- # The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in range(self._numL2Caches)] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False)
- self.l2_select_num_bits = int(math.log(num_l2Caches , 2))
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.enable_prefetch = False
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.out_port = ruby_system.network.in_port
-
- self.optionalQueue = MessageBuffer()
-
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getBlockSizeBits(system,
- num_l2Caches))
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
- self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2017/configs/system/MI_example_caches.py b/src/spec-2017/configs/system/MI_example_caches.py
deleted file mode 100644
index 0d028df..0000000
--- a/src/spec-2017/configs/system/MI_example_caches.py
+++ /dev/null
@@ -1,279 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2015 Jason Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Power
-
-""" This file creates a set of Ruby caches, the Ruby network, and a simple
-point-to-point topology.
-See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
-You can change simple_ruby to import from this file instead of from msi_caches
-to use the MI_example protocol instead of MSI.
-
-IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
- also needs to be updated. For now, email Jason <jason@lowepower.com>
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MIExampleSystem(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MI_example':
- fatal("This system assumes MI_example!")
-
- super(MIExampleSystem, self).__init__()
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MI example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # Create one controller for each L1 cache (and the cache mem obj.)
- # Create a single directory controller (Really the memory cntrl)
- self.controllers = \
- [L1Cache(system, self, cpu) for cpu in cpus] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU. In many systems this is more
- # complicated since you have to create sequencers for DMA controllers
- # and other controllers, too.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].cacheMemory,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[0:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu):
- """CPUs are needed to grab the clock domain and system is needed for
- the cache block size.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.cacheMemory = RubyCache(size = '16kB',
- assoc = 8,
- start_index_bit = self.getBlockSizeBits(system))
- self.clk_domain = cpu.clk_domain
- self.send_evictions = self.sendEvicts(cpu)
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromCache = MessageBuffer(ordered = True)
- self.requestFromCache.out_port = ruby_system.network.in_port
- self.responseFromCache = MessageBuffer(ordered = True)
- self.responseFromCache.out_port = ruby_system.network.in_port
- self.forwardToCache = MessageBuffer(ordered = True)
- self.forwardToCache.in_port = ruby_system.network.out_port
- self.responseToCache = MessageBuffer(ordered = True)
- self.responseToCache.in_port = ruby_system.network.out_port
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer(ordered = True)
- self.requestToDir.in_port = ruby_system.network.out_port
- self.dmaRequestToDir = MessageBuffer(ordered = True)
- self.dmaRequestToDir.in_port = ruby_system.network.out_port
-
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.dmaResponseFromDir = MessageBuffer(ordered = True)
- self.dmaResponseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2017/configs/system/MOESI_CMP_directory.py b/src/spec-2017/configs/system/MOESI_CMP_directory.py
deleted file mode 100644
index 15b215d..0000000
--- a/src/spec-2017/configs/system/MOESI_CMP_directory.py
+++ /dev/null
@@ -1,350 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2020 The Regents of the University of California.
-# All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MOESI CMP directory
-protocol.
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MOESICMPDirCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
- fatal("This system assumes MOESI_CMP_directory!")
-
- super(MOESICMPDirCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MOESI_CMP_directory example uses 3 virtual networks
- self.number_of_virtual_networks = 3
- self.network.number_of_virtual_networks = 3
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU core.
- # The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in range(self._numL2Caches)] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getL2StartIdx(system,
- num_l2Caches),
- dataAccessLatency = 20,
- tagAccessLatency = 20)
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getL2StartIdx(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.GlobalRequestFromL2Cache = MessageBuffer()
- self.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
-
- self.GlobalRequestToL2Cache = MessageBuffer()
- self.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.reqToDir = MessageBuffer()
- self.reqToDir.out_port = ruby_system.network.in_port
- self.respToDir = MessageBuffer()
- self.respToDir.out_port = ruby_system.network.in_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2017/configs/system/__init__.py b/src/spec-2017/configs/system/__init__.py
deleted file mode 100644
index 94e676f..0000000
--- a/src/spec-2017/configs/system/__init__.py
+++ /dev/null
@@ -1,31 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from .system import MySystem
-from .ruby_system import MyRubySystem
diff --git a/src/spec-2017/configs/system/caches.py b/src/spec-2017/configs/system/caches.py
deleted file mode 100644
index 84f63e7..0000000
--- a/src/spec-2017/configs/system/caches.py
+++ /dev/null
@@ -1,171 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-""" Caches with options for a simple gem5 configuration script
-
-This file contains L1 I/D and L2 caches to be used in the simple
-gem5 configuration script.
-"""
-
-from m5.objects import Cache, L2XBar, StridePrefetcher
-# Some specific options for caches
-# For all options see src/mem/cache/BaseCache.py
-
-class PrefetchCache(Cache):
-
- def __init__(self, options = None):
- super(PrefetchCache, self).__init__()
- if not options or options.no_prefetchers:
- return
- self.prefetcher = StridePrefetcher()
-
-class L1Cache(PrefetchCache):
- """Simple L1 Cache with default values"""
-
- assoc = 8
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 16
- tgts_per_mshr = 20
- writeback_clean = True
-
- def __init__(self):
- super(L1Cache, self).__init__()
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU-side port
- This must be defined in a subclass"""
- raise NotImplementedError
-
-class L1ICache(L1Cache):
- """Simple L1 instruction cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1ICache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU icache port"""
- self.cpu_side = cpu.icache_port
-
-class L1DCache(L1Cache):
- """Simple L1 data cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1DCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU dcache port"""
- self.cpu_side = cpu.dcache_port
-
-class MMUCache(Cache):
- # Default parameters
- size = '8kB'
- assoc = 4
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(MMUCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect the CPU itb and dtb to the cache
- Note: This creates a new crossbar
- """
- self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
-class L2Cache(PrefetchCache):
- """Simple L2 Cache with default values"""
-
- # Default parameters
- size = '256kB'
- assoc = 16
- tag_latency = 10
- data_latency = 10
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(L2Cache, self).__init__()
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
-
-class L3Cache(Cache):
- """Simple L3 Cache bank with default values
- This assumes that the L3 is made up of multiple banks. This cannot
- be used as a standalone L3 cache.
- """
-
- # Default parameters
- assoc = 32
- tag_latency = 40
- data_latency = 40
- response_latency = 10
- mshrs = 256
- tgts_per_mshr = 12
- clusivity = 'mostly_excl'
-
- size = '4MB'
-
- def __init__(self):
- super(L3Cache, self).__init__()
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
-
diff --git a/src/spec-2017/configs/system/fs_tools.py b/src/spec-2017/configs/system/fs_tools.py
deleted file mode 100644
index 5e5e2df..0000000
--- a/src/spec-2017/configs/system/fs_tools.py
+++ /dev/null
@@ -1,39 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
-
-class CowDisk(IdeDisk):
-
- def __init__(self, filename):
- super(CowDisk, self).__init__()
- self.driveID = 'device0'
- self.image = CowDiskImage(child=RawDiskImage(read_only=True),
- read_only=False)
- self.image.child.image_file = filename
diff --git a/src/spec-2017/configs/system/ruby_system.py b/src/spec-2017/configs/system/ruby_system.py
deleted file mode 100755
index d1ddb07..0000000
--- a/src/spec-2017/configs/system/ruby_system.py
+++ /dev/null
@@ -1,244 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-
-
-class MyRubySystem(System):
-
- def __init__(self, kernel, disk, mem_sys, num_cpus, TimingCPUModel, no_kvm=False):
- super(MyRubySystem, self).__init__()
- self._no_kvm = no_kvm
-
- self._host_parallel = True
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '2.3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- self.initFS(num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus,TimingCPUModel)
-
- self.createMemoryControllersDDR4()
-
- # Create the cache hierarchy for the system.
- if mem_sys == 'MI_example':
- from .MI_example_caches import MIExampleSystem
- self.caches = MIExampleSystem()
- elif mem_sys == 'MESI_Two_Level':
- from .MESI_Two_Level import MESITwoLevelCache
- self.caches = MESITwoLevelCache()
- elif mem_sys == 'MOESI_CMP_directory':
- from .MOESI_CMP_directory import MOESICMPDirCache
- self.caches = MOESICMPDirCache()
- self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports],
- self.iobus)
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus, TimingCPUModel):
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.mem_mode = 'timing'
-
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.detailed_cpu = [TimingCPUModel(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
-
- self.createCPUThreads(self.detailed_cpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createMemoryControllersDDR4(self):
- self._createMemoryControllers(1, DDR4_2400_16x4)
-
- def _createMemoryControllers(self, num, cls):
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = self.mem_ranges[0]))
- for i in range(num)
- ]
-
- def _createKernelMemoryController(self, cls):
- return cls(range = self.mem_ranges[0],
- port = self.membus.mem_side_ports)
-
- def initFS(self, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # North Bridge
- self.iobus = IOXBar()
-
- # connect the io bus
- # Note: pass in a reference to where Ruby will connect to in the future
- # so the port isn't connected twice.
- self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/spec-2017/configs/system/system.py b/src/spec-2017/configs/system/system.py
deleted file mode 100644
index b07596c..0000000
--- a/src/spec-2017/configs/system/system.py
+++ /dev/null
@@ -1,375 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2018 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-from .caches import *
-
-
-class MySystem(System):
-
- def __init__(self, kernel, disk, num_cpus, TimingCPUModel, no_kvm=False):
- super(MySystem, self).__init__()
- self._no_kvm = no_kvm
-
- self._host_parallel = True
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '2.3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- mem_size = '32GB'
- self.mem_ranges = [AddrRange('100MB'), # For kernel
- AddrRange(0xC0000000, size=0x100000), # For I/0
- AddrRange(Addr('4GB'), size = mem_size) # All data
- ]
-
- # Create the main memory bus
- # This connects to main memory
- self.membus = SystemXBar(width = 64) # 64-byte width
- self.membus.badaddr_responder = BadAddr()
- self.membus.default = Self.badaddr_responder.pio
-
- # Set up the system port for functional access from the simulator
- self.system_port = self.membus.cpu_side_ports
-
- self.initFS(self.membus, num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus, TimingCPUModel)
-
- # Create the cache heirarchy for the system.
- self.createCacheHierarchy()
-
- # Set up the interrupt controllers for the system (x86 specific)
- self.setupInterrupts()
-
- self.createMemoryControllersDDR4()
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus, TimingCPUModel):
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.mem_mode = 'timing'
-
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.detailed_cpu = [TimingCPUModel(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
-
- self.createCPUThreads(self.detailed_cpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createCacheHierarchy(self):
- # Create an L3 cache (with crossbar)
- self.l3bus = L2XBar(width = 64,
- snoop_filter = SnoopFilter(max_capacity='32MB'))
-
- for cpu in self.cpu:
- # Create a memory bus, a coherent crossbar, in this case
- cpu.l2bus = L2XBar()
-
- # Create an L1 instruction and data cache
- cpu.icache = L1ICache()
- cpu.dcache = L1DCache()
- cpu.mmucache = MMUCache()
-
- # Connect the instruction and data caches to the CPU
- cpu.icache.connectCPU(cpu)
- cpu.dcache.connectCPU(cpu)
- cpu.mmucache.connectCPU(cpu)
-
- # Hook the CPU ports up to the l2bus
- cpu.icache.connectBus(cpu.l2bus)
- cpu.dcache.connectBus(cpu.l2bus)
- cpu.mmucache.connectBus(cpu.l2bus)
-
- # Create an L2 cache and connect it to the l2bus
- cpu.l2cache = L2Cache()
- cpu.l2cache.connectCPUSideBus(cpu.l2bus)
-
- # Connect the L2 cache to the L3 bus
- cpu.l2cache.connectMemSideBus(self.l3bus)
-
- self.l3cache = L3Cache()
- self.l3cache.connectCPUSideBus(self.l3bus)
-
- # Connect the L3 cache to the membus
- self.l3cache.connectMemSideBus(self.membus)
-
- def setupInterrupts(self):
- for cpu in self.cpu:
- # create the interrupt controller CPU and connect to the membus
- cpu.createInterruptController()
-
- # For x86 only, connect interrupts to the memory
- # Note: these are directly connected to the memory bus and
- # not cached
- cpu.interrupts[0].pio = self.membus.mem_side_ports
- cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
- cpu.interrupts[0].int_responder = self.membus.mem_side_ports
-
- # Memory latency: Using the smaller number from [3]: 96ns
- def createMemoryControllersDDR4(self):
- self._createMemoryControllers(8, DDR4_2400_16x4)
-
- def _createMemoryControllers(self, num, cls):
- kernel_controller = self._createKernelMemoryController(cls)
-
- ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = ranges[i]),
- port = self.membus.mem_side_ports)
- for i in range(num)
- ] + [kernel_controller]
-
- def _createKernelMemoryController(self, cls):
- return MemCtrl(dram = cls(range = self.mem_ranges[0]),
- port = self.membus.mem_side_ports)
-
- def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
- from math import log
- bits = int(log(num, 2))
- if 2**bits != num:
- m5.fatal("Non-power of two number of memory controllers")
-
- intlv_bits = bits
- ranges = [
- AddrRange(start=rng.start,
- end=rng.end,
- intlvHighBit = intlv_low_bit + intlv_bits - 1,
- xorHighBit = xor_low_bit + intlv_bits - 1,
- intlvBits = intlv_bits,
- intlvMatch = i)
- for i in range(num)
- ]
-
- return ranges
-
- def initFS(self, membus, cpus):
- self.pc = Pc()
- self.workload = X86FsLinux()
- # Constants similar to x86_traits.hh
- IO_address_space_base = 0x8000000000000000
- pci_config_address_space_base = 0xc000000000000000
- interrupts_address_space_base = 0xa000000000000000
- APIC_range_size = 1 << 12
-
- # North Bridge
- self.iobus = IOXBar()
- self.bridge = Bridge(delay='50ns')
- self.bridge.mem_side_port = self.iobus.cpu_side_ports
- self.bridge.cpu_side_port = membus.mem_side_ports
- # Allow the bridge to pass through:
- # 1) kernel configured PCI device memory map address: address range
- # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
- # 2) the bridge to pass through the IO APIC (two pages, already
- # contained in 1),
- # 3) everything in the IO address range up to the local APIC, and
- # 4) then the entire PCI address space and beyond.
- self.bridge.ranges = \
- [
- AddrRange(0xC0000000, 0xFFFF0000),
- AddrRange(IO_address_space_base,
- interrupts_address_space_base - 1),
- AddrRange(pci_config_address_space_base,
- Addr.max)
- ]
-
- # Create a bridge from the IO bus to the memory bus to allow access
- # to the local APIC (two pages)
- self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
- self.apicbridge.mem_side_port = membus.cpu_side_ports
- self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
- interrupts_address_space_base +
- cpus * APIC_range_size
- - 1)]
-
- # connect the io bus
- self.pc.attachIO(self.iobus)
-
- # Add a tiny cache to the IO bus.
- # This cache is required for the classic memory model for coherence
- self.iocache = Cache(assoc=8,
- tag_latency = 50,
- data_latency = 50,
- response_latency = 50,
- mshrs = 20,
- size = '1kB',
- tgts_per_mshr = 12,
- addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.mem_side_ports
- self.iocache.mem_side = self.membus.cpu_side_ports
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
- # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which
- # force IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests
- # to this specific range can pass though bridge to iobus.
- entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
- size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
- range_type=2))
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- # Add the rest of memory. This is where all the actual data is
- entries.append(X86E820Entry(addr = self.mem_ranges[-1].start,
- size='%dB' % (self.mem_ranges[-1].size()),
- range_type=1))
-
- self.workload.e820_table.entries = entries
