diff --git a/src/boot-exit/configs/system/ruby_system.py b/src/boot-exit/configs/system/ruby_system.py
index 30eebd4..687e252 100755
--- a/src/boot-exit/configs/system/ruby_system.py
+++ b/src/boot-exit/configs/system/ruby_system.py
@@ -147,8 +147,6 @@
         # so the port isn't connected twice.
         self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/boot-exit/configs/system/system.py b/src/boot-exit/configs/system/system.py
index d92cd72..b6ad6b9 100755
--- a/src/boot-exit/configs/system/system.py
+++ b/src/boot-exit/configs/system/system.py
@@ -233,8 +233,6 @@
         self.iocache.cpu_side = self.iobus.mem_side_ports
         self.iocache.mem_side = self.membus.cpu_side_ports
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/gapbs/configs/system/ruby_system.py b/src/gapbs/configs/system/ruby_system.py
index e7c1135..38960f9 100644
--- a/src/gapbs/configs/system/ruby_system.py
+++ b/src/gapbs/configs/system/ruby_system.py
@@ -150,8 +150,6 @@
         # so the port isn't connected twice.
         self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/gapbs/configs/system/system.py b/src/gapbs/configs/system/system.py
index 3287c3e..70a6255 100644
--- a/src/gapbs/configs/system/system.py
+++ b/src/gapbs/configs/system/system.py
@@ -259,8 +259,6 @@
         self.iocache.cpu_side = self.iobus.mem_side_ports
         self.iocache.mem_side = self.membus.cpu_side_ports
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/npb/configs/system/ruby_system.py b/src/npb/configs/system/ruby_system.py
index 4d313bb..6b3435a 100755
--- a/src/npb/configs/system/ruby_system.py
+++ b/src/npb/configs/system/ruby_system.py
@@ -157,8 +157,6 @@
         # so the port isn't connected twice.
         self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/npb/configs/system/system.py b/src/npb/configs/system/system.py
index 23b8b60..e7a0753 100755
--- a/src/npb/configs/system/system.py
+++ b/src/npb/configs/system/system.py
@@ -306,8 +306,6 @@
         self.iocache.cpu_side = self.iobus.mem_side_ports
         self.iocache.mem_side = self.membus.cpu_side_ports
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/parsec/configs-mesi-two-level/system/ruby_system.py b/src/parsec/configs-mesi-two-level/system/ruby_system.py
index d0adcc7..b6a647e 100755
--- a/src/parsec/configs-mesi-two-level/system/ruby_system.py
+++ b/src/parsec/configs-mesi-two-level/system/ruby_system.py
@@ -161,8 +161,6 @@
         # so the port isn't connected twice.
         self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/parsec/configs/system/ruby_system.py b/src/parsec/configs/system/ruby_system.py
index 30eebd4..687e252 100644
--- a/src/parsec/configs/system/ruby_system.py
+++ b/src/parsec/configs/system/ruby_system.py
@@ -147,8 +147,6 @@
         # so the port isn't connected twice.
         self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/parsec/configs/system/system.py b/src/parsec/configs/system/system.py
index fe4d198..c2360c0 100644
--- a/src/parsec/configs/system/system.py
+++ b/src/parsec/configs/system/system.py
@@ -250,8 +250,6 @@
         self.iocache.cpu_side = self.iobus.mem_side_ports
         self.iocache.mem_side = self.membus.cpu_side_ports
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/riscv-fs/configs-riscv-fs/system/system.py b/src/riscv-fs/configs-riscv-fs/system/system.py
index 5032664..0150972 100755
--- a/src/riscv-fs/configs-riscv-fs/system/system.py
+++ b/src/riscv-fs/configs-riscv-fs/system/system.py
@@ -184,8 +184,6 @@
         self.platform.attachOffChipIO(self.iobus)
 
     def setupIntrCtrl(self):
-        self.intrctrl = IntrControl()
-
         # Set the frequency of RTC (real time clock) used by
         # CLINT (core level interrupt controller).
         # This frequency is 1MHz in SiFive's U54MC.
diff --git a/src/spec-2006/configs/system/ruby_system.py b/src/spec-2006/configs/system/ruby_system.py
index 4860504..1ffea57 100755
--- a/src/spec-2006/configs/system/ruby_system.py
+++ b/src/spec-2006/configs/system/ruby_system.py
@@ -163,8 +163,6 @@
         # so the port isn't connected twice.
         self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/spec-2006/configs/system/system.py b/src/spec-2006/configs/system/system.py
index a5fbe16..b6e434e 100644
--- a/src/spec-2006/configs/system/system.py
+++ b/src/spec-2006/configs/system/system.py
@@ -281,8 +281,6 @@
         self.iocache.cpu_side = self.iobus.mem_side_ports
         self.iocache.mem_side = self.membus.cpu_side_ports
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/spec-2017/configs/system/ruby_system.py b/src/spec-2017/configs/system/ruby_system.py
index 4860504..1ffea57 100755
--- a/src/spec-2017/configs/system/ruby_system.py
+++ b/src/spec-2017/configs/system/ruby_system.py
@@ -163,8 +163,6 @@
         # so the port isn't connected twice.
         self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.
diff --git a/src/spec-2017/configs/system/system.py b/src/spec-2017/configs/system/system.py
index de2afc8..a35e570 100644
--- a/src/spec-2017/configs/system/system.py
+++ b/src/spec-2017/configs/system/system.py
@@ -283,8 +283,6 @@
         self.iocache.cpu_side = self.iobus.mem_side_ports
         self.iocache.mem_side = self.membus.cpu_side_ports
 
-        self.intrctrl = IntrControl()
-
         ###############################################
 
         # Add in a Bios information structure.