resources: Merge branch 'stable' into 'develop'
Change-Id: Ib9f0fdc15ff4e5e73af2e6e3ccc9c3405d0a9205
diff --git a/README.md b/README.md
index 88d8abc..6179118 100644
--- a/README.md
+++ b/README.md
@@ -68,14 +68,14 @@
## Resource: RISCV Tests
-The RISCV Tests soruce can be found in the `src/riscv-tests` directory. More
+The RISCV Tests source can be found in the `src/riscv-tests` directory. More
information about these tests can be found in `src/riscv-tests/README.md`.
### RISCV Tests Origins
The RISCV Tests in this repository were obtained from
-<https://github.com/riscv/riscv-tests.git>, revision
-19bfdab48c2a6da4a2c67d5779757da7b073811d.
+<https://github.com/riscv-software-src/riscv-tests.git>, revision
+e65ecdf941a5484af27f9be223fb655ebcb0398b.
### RISCV Tests Compilation
@@ -123,7 +123,7 @@
## Resource: simple
The simple resources are small binaries, often used to run quick tests and
-checks in gem5. Their bare-meltal
+checks in gem5. They are baremetal.
### simple Compilation
@@ -441,7 +441,7 @@
docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu make
```
-By default, the makefile builds for gfx801, and is placed in the `src/gpu/lulesh/bin` folder.
+By default, the Makefile builds for gfx801, and is placed in the `src/gpu/lulesh/bin` folder.
lulesh is a GPU application, which requires that gem5 is built with the GCN3_X86 architecture.
To build GCN3_X86:
@@ -673,7 +673,7 @@
The NAS Parallel Benchmarks (NPB) are a small set of programs designed to
help evaluate the performance of parallel supercomputers. The set consists of
-five Lunux Kernels and three pseudo-applications. gem5 resources provides a
+five Linux Kernels and three pseudo-applications. gem5 resources provides a
disk image, and scripts allowing for the NPB image to be run within gem5 X86
simulations.
@@ -703,11 +703,11 @@
More information on Linux boot tests can be found [here](https://www.gem5.org/project/2020/03/09/boot-tests.html).
The boot-tests resources consist of three main components:
-- boot-tests disk image
+- x86-ubuntu disk image
- gem5 run scripts to execute boot tests
- linux kernel configuration files
-The instructions to build the boot-tests disk image (`boot-exit`), the Linux binaries, and how to use gem5 run scripts to run boot-tests are available in this [README](src/boot-tests/README.md) file.
+The instructions to build the x86-ubuntu disk image, the Linux binaries, and how to use gem5 run scripts to run boot-tests are available in this [README](src/x86-ubuntu/README.md) file.
## Resource: RISCV Full System
@@ -724,6 +724,20 @@
<http://dist.gem5.org/dist/develop/kernels/riscv/static/bootloader-vmlinux-5.10>
+
+## Resource: RISCV Full System with Disk Image
+
+The RISCV Full System resource includes a RISCV bootloader (`berkeley bootloader (bbl)`) to boot the Linux 5.10 kernel on a RISCV system.
+The workload and the Linux utils (provided by BusyBox) are also included in the bootloader.
+The resource also contains simple gem5 run/config scripts to run Linux full system simulations in which a user may telnet into.
+
+More details on building such a RISCV bootloader and hwo does it work are available in the [README.md](src/riscv-boot-exit-nodisk/README.md) file.
+
+### RISCV Full System pre-built Linux bootloader with embedded workload
+
+<http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit>
+
+
## Resource: Insttest
@@ -819,9 +833,9 @@
[`src/npb`](
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/npb).
The NAS Parallel Benchmarks utilize a permissive BSD-style license.
-* **boot-exit**: Consult individual copyright notices of source files in
-[`src/boot-exit`](
-https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit).
+* **x86-ubuntu**: Consult individual copyright notices of source files in
+[`src/x86-ubuntu`](
+https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/x86-ubuntu).
* **insttest**: Consult individual copyright notices of source files in
[`src/insttest`](
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/insttest).
diff --git a/resources.json b/resources.json
new file mode 100644
index 0000000..dec0e31
--- /dev/null
+++ b/resources.json
@@ -0,0 +1,3814 @@
+
+{
+ "version" : "[DEVELOP FOR v21.2]",
+ "url_base" : "http://dist.gem5.org/dist/develop",
+ "previous-versions" : {},
+ "resources": [
+ {
+ "type": "resource",
+ "name" : "riscv-disk-img",
+ "documentation" : "A simple RISCV disk image based on busybox.",
+ "architecture": "RISCV",
+ "is_zipped" : true,
+ "md5sum" : "d6126db9f6bed7774518ae25aa35f153",
+ "url": "{url_base}/images/riscv/busybox/riscv-disk.img.gz",
+ "source" : "src/riscv-fs",
+ "additional_metadata" : {
+ "root_partition": null
+ }
+ },
+ {
+ "type": "resource",
+ "name" : "riscv-lupio-busybox-img",
+ "documentation" : "A RISCV disk image, based on busybox, to be used with the LupioBoard. Should be used with the 'riscv-lupio-busybox-img' kernel resource.",
+ "architecture": "RISCV",
+ "is_zipped" : true,
+ "md5sum" : "e5bee8a31f45f4803f87c0d781553ccc",
+ "url": "{url_base}/images/riscv/busybox/riscv-lupio-busybox.img.gz",
+ "source" : null,
+ "additional_metadata" : {
+ "root_partition": "1"
+ }
+ },
+
+ {
+ "type" : "resource",
+ "name" : "x86-m5-exit",
+ "documentation" : "A simple binary which will run `m5 exit`. Compiled to the X86 ISA.",
+ "architecture" : "X86",
+ "is_zipped" : false,
+ "md5sum" : "19e178622935fdcee1aff0dd7d6d0ebc",
+ "url" : "{url_base}/test-progs/m5-exit/bin/x86/linux/m5_exit",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-parsec",
+ "documentation" : "A disk image containing the PARSEC benchmark suite, compiled to X86, built on top of Ubuntu 18.04.",
+ "architecture" : "X86",
+ "is_zipped" : true,
+ "md5sum" : "19131e62c5b10f137948ec5975391477",
+ "url" : "{url_base}/images/x86/ubuntu-18-04/parsec.img.gz",
+ "source" : "src/parsec",
+ "additional_metadata" : {
+ "root_partition": "1"
+ }
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-gapbs",
+ "documentation" : "A disk image containing the GAPBS benchmark suite, compiled to X86, built on top of Ubuntu 18.04.",
+ "architecture" : "X86",
+ "is_zipped" : true,
+ "md5sum" : "c9217a88eff20e5547be87368a1499c1",
+ "url" : "{url_base}/images/x86/ubuntu-18-04/gapbs.img.gz",
+ "source" : "src/gabps",
+ "additional_metadata" : {
+ "root_partition": "1"
+ }
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-npb",
+ "documentation" : "A disk image containing the NAS Parallel benchmark (NPB) suite, compiled to X86, built on top of Ubuntu 18.04.",
+ "architecture" : "X86",
+ "is_zipped" : true,
+ "md5sum" : "68073181c1ecca2347ad18c3577e0cd9",
+ "url" : "{url_base}/images/x86/ubuntu-18-04/npb.img.gz",
+ "source" : "src/npb",
+ "additional_metadata" : {
+ "root_partition": "1"
+ }
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-boot-exit",
+ "documentation" : "A disk image containing Ubuntu 18.04 for X86 which will run a `m5 exit` instruction after booting. [This is deprecated. Please use 'x86-ubuntu-18.04-img'].",
+ "architecture" : "X86",
+ "is_zipped" : true,
+ "md5sum" : "008a4bf505a04efed0758b49183e01f7",
+ "url" : "{url_base}/images/x86/ubuntu-18-04/boot-exit.img.gz",
+ "source" : "src/boot-exit",
+ "additional_metadata" : {
+ "root_partition": "1"
+ }
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-ubuntu-img",
+ "documentation" : "A disk image containing Ubuntu 18.04 for x86. This image will run an `m5 readfile` instruction after booting. If no script file is specified an `m5 exit` instruction will be executed. [This is deprecated. Please use 'x86-ubuntu-18.04-img'].",
+ "architecture" : "X86",
+ "is_zipped" : true,
+ "md5sum" : "90e363abf0ddf22eefa2c7c5c9391c49",
+ "url" : "{url_base}/images/x86/ubuntu-18-04/x86-ubuntu.img.gz",
+ "source" : "src/x86-ubuntu",
+ "additional_metadata" : {
+ "root_partition": "1"
+ }
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-ubuntu-18.04-img",
+ "documentation" : "A disk image containing Ubuntu 18.04 for x86. This image will run an `m5 readfile` instruction after booting. If no script file is specified an `m5 exit` instruction will be executed.",
+ "architecture" : "X86",
+ "is_zipped" : true,
+ "md5sum" : "90e363abf0ddf22eefa2c7c5c9391c49",
+ "url" : "{url_base}/images/x86/ubuntu-18-04/x86-ubuntu.img.gz",
+ "source" : "src/x86-ubuntu",
+ "additional_metadata" : {
+ "root_partition": "1"
+ }
+ },
+ {
+ "type": "resource",
+ "name" : "riscv-ubuntu-20.04-img",
+ "documentation" : "A disk image containing Ubuntu 20.04 for RISCV which will run an `m5 readfile` instruction after booting. If no script file is specified an `m5 exit` instruction will be exected",
+ "architecture" : "RISCV",
+ "is_zipped" : true,
+ "md5sum" : "b017372639ba13ad9ee9d9283647fa20",
+ "url" : "{url_base}/images/riscv/ubuntu-20-04/riscv-ubuntu.img.gz",
+ "source" : "src/riscv-ubuntu",
+ "additional_metadata" : {
+ "root_partition": "1"
+ }
+ },
+ {
+ "type": "resource",
+ "name" : "riscv-boot-exit-nodisk",
+ "documentation" : "A simple RISCV bootloader with Linux kernel 5.10. The early userspace includes busybox and the m5 binary.",
+ "architecture": "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "8ec185abc97e42b4ab1f0a30fc720e09",
+ "url": "{url_base}/misc/riscv/bbl-busybox-boot-exit",
+ "source" : "src/riscv-boot-exit-nodisk"
+ },
+ {
+ "type" : "group",
+ "name" : "linux-kernel",
+ "contents" : [
+ {
+ "type" : "resource",
+ "name" : "x86-linux-kernel-4.19.83",
+ "documentation" : "The linux kernel (v4.19.83), compiled to X86.",
+ "architecture" : "X86",
+ "is_zipped" : false,
+ "md5sum" : "28228eac2eea81ee3ce36305b7641c18",
+ "url" : "{url_base}/kernels/x86/static/vmlinux-4.19.83",
+ "source" : "src/linux-kernel"
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-linux-kernel-5.4.49",
+ "documentation" : "The linux kernel (v5.4.49), compiled to X86.",
+ "architecture" : "X86",
+ "is_zipped" : false,
+ "md5sum" : "60a53c7d47d7057436bf4b9df707a841",
+ "url" : "{url_base}/kernels/x86/static/vmlinux-5.4.49",
+ "source" : "src/linux-kernel"
+ },
+ {
+ "type" : "resource",
+ "name" : "riscv-bootloader-vmlinux-5.10",
+ "documentation" : "A RISCV bootloader kernel binary with linux 5.10.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "ac29fe5f71c096e6b2044b4e4d623edc",
+ "url" : "{url_base}/kernels/riscv/static/bootloader-vmlinux-5.10",
+ "source" : "src/riscv-fs"
+ },
+ {
+ "type" : "resource",
+ "name" : "riscv-lupio-linux-kernel",
+ "documentation": "A kernel built with LupIO device (https://gitlab.com/luplab/lupio) drivers. Must be used when setting LupIO board workloads. Compataible with the 'riscv-lupio-busybox-img' disk image resource.",
+ "is_zipped" : false,
+ "md5sum" : "f94351edbbb0e7bd9617f7b381635546",
+ "url" : "{url_base}/kernels/riscv/static/lupio-linux",
+ "source" : null
+ }
+ ]
+ },
+ {
+ "type" : "group",
+ "name" : "hello",
+ "contents" : [
+ {
+ "type" : "resource",
+ "name" : "riscv-hello",
+ "documentation" : "A 'Hello World!' binary, compiled to RISCV.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "6d9494d22b90d817e826b0d762fda973",
+ "url" : "{url_base}/test-progs/hello/bin/riscv/linux/hello",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "arm-hello64-static",
+ "documentation" : "A 'Hello World!' binary, statically compiled to ARM 64 bit.",
+ "architecture" : "ARM",
+ "is_zipped" : false,
+ "md5sum" : "71b2cb004fe2cda4556f0b1a38638af6",
+ "url" : "{url_base}/test-progs/hello/bin/arm/linux/hello64-static",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "arm-hello32-static",
+ "documentation" : "A 'Hello World!' binary, statically compiled to ARM 32 bit.",
+ "architecture" : "ARM",
+ "is_zipped" : false,
+ "md5sum" : "15defa57a6c0035590992f8d715e9318",
+ "url" : "{url_base}/test-progs/hello/bin/arm/linux/hello32-static",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "mips-hello",
+ "documentation" : "A 'Hello World!' binary, compiled to MIPS.",
+ "architecture" : "MIPS",
+ "is_zipped" : false,
+ "md5sum" : "c98040d3802b49c37b8d88811cd896d5",
+ "url" : "{url_base}/test-progs/hello/bin/mips/linux/hello",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "sparc-hello",
+ "documentation" : "A 'Hello World!' binary, compiled to SPARC.",
+ "architecture" : "SPARC",
+ "is_zipped" : false,
+ "md5sum" : "b242b62c32dd0e0eb7b79141d2be7707",
+ "url" : "{url_base}/test-progs/hello/bin/sparc/linux/hello",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "power-hello",
+ "documentation" : "A 'Hello World!' binary, compiled to POWER.",
+ "architecture" : "POWER",
+ "is_zipped" : false,
+ "md5sum" : "3402ef20eb11e0a8580b0fde0a692bc3",
+ "url" : "{url_base}/test-progs/hello/bin/power/linux/hello",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-hello64-static",
+ "documentation" : "A 'Hello World!' binary, statically compiled to X86 64 bit.",
+ "architecture" : "X86",
+ "is_zipped" : false,
+ "md5sum" : "dbf120338b37153e3334603970cebd8c",
+ "url" : "{url_base}/test-progs/hello/bin/x86/linux/hello64-static",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-hello32-static",
+ "documentation" : "A 'Hello World!' binary, statically compiled to X86 32 bit.",
+ "architecture" : "X86",
+ "is_zipped" : false,
+ "md5sum" : "d46e559a4272e75a0086b382560d296e",
+ "url" : "{url_base}/test-progs/hello/bin/x86/linux/hello32-static",
+ "source" : "src/simple"
+ },
+ {
+ "type" : "resource",
+ "name" : "x86-hello64-dynamic",
+ "documentation" : "A 'Hello World!' binary, dynamically compiled to X86 64 bit.",
+ "architecture" : "X86",
+ "is_zipped" : false,
+ "md5sum" : "e9b31ab86ce0f95e290ce7661cf7cf88",
+ "url" : "{url_base}/test-progs/hello/bin/x86/linux/hello64-dynamic",
+ "source" : "src/simple"
+ }
+ ]
+ },
+ {
+ "type" : "resource",
+ "name" : "sparc-insttest",
+ "documentation" : "A binary which will run several SPARC ISA instruction tests.",
+ "architecture" : "SPARC",
+ "is_zipped" : false,
+ "md5sum" : "621434719e68377443ea0f2e3a50e4cb",
+ "url" : "{url_base}/test-progs/insttest/bin/sparc/linux/insttest",
+ "source" : "src/insttest"
+ },
+ {
+ "type" : "group",
+ "name" : "asmtest",
+ "contents" : [
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-access",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "f79864adb24b4d9d58973fe296555dc3",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-access",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-breakpoint",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "cf9c2c258bc4ee79f6ab725dcd93c8a3",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-breakpoint",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-csr",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "d184e318ca5583c7459d210af833f67d",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-csr",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-illegal",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "7f5bb9a8dc5b3556c63f24966edf6ad2",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-illegal",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-ma_addr",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "01720cfc720c49af44593fb66e63e06e",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-ma_addr",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-ma_fetch",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "6a8ee354739700aa4da0cf256ae3b623",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-ma_fetch",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-mcsr",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "1894b9678b44a1317bf0fda2bc767443",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-mcsr",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-sbreak",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "50e24f358eeceb443c18fe4e566957b2",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-sbreak",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64mi-p-scall",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "b95617ad90fd92f3f518c626bc1c81fc",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64mi-p-scall",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64samt-ps-sysclone_d",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "84dc170bb877dc516f6127371f813087",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64samt-ps-sysclone_d",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64samt-ps-sysfutex1_d",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "fe859cc6a504d62bc3abbb751b55e416",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64samt-ps-sysfutex1_d",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64samt-ps-sysfutex2_d",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "4a8d53dd89756e6c74ed0925fab72fc4",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64samt-ps-sysfutex2_d",
+ "source" : "src/asmtest"
+ },
+ {
+ "type" : "resource",
+ "name" : "rv64samt-ps-sysfutex3_d",
+ "documentation" : "A RISCV binary used to test a specific RISCV instruction.",
+ "architecture" : "RISCV",
+ "is_zipped" : false,
+ "md5sum" : "ec61b4108d4c6bb904600a588bb367d3",
+ "url" : "{url_base}/test-progs/asmtest/bin/rv64samt-ps-sysfutex3_d",
+ "source" : "src/asmtest"
+ },
+ {
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+ "name" : "rv64samt-ps-sysfutex_d",
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-ps-divuw",
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-ps-rem",
+ "source" : "src/asmtest"
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+ {
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-ps-remu",
+ "source" : "src/asmtest"
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-ps-remw",
+ "source" : "src/asmtest"
+ },
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-div",
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-divu",
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+ },
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+ },
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-mul",
+ "source" : "src/asmtest"
+ },
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-mulh",
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-mulhsu",
+ "source" : "src/asmtest"
+ },
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-mulhu",
+ "source" : "src/asmtest"
+ },
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-mulw",
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+ },
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-remuw",
+ "source" : "src/asmtest"
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+ "url" : "{url_base}/test-progs/asmtest/bin/rv64um-v-remw",
+ "source" : "src/asmtest"
+ }
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+}
+
diff --git a/src/gapbs/README.md b/src/gapbs/README.md
index b2336c0..c8d34a3 100644
--- a/src/gapbs/README.md
+++ b/src/gapbs/README.md
@@ -10,9 +10,9 @@
license: BSD-3-Clause
---
-This document provides instructions to create a GAP Benchmark Suite (GAPBS) disk image, which, along with provided configuration scripts, may be used to run GAPBS within gem5 simulations.
+This document provides instructions to create a GAP Benchmark Suite (GAPBS) disk image, which, along with an example script, may be used to run GAPBS within gem5 simulations. The example script uses a pre-built disk-image.
-A pre-build disk image, for X86, can be found, gzipped, here: <http://dist.gem5.org/dist/v21-1/images/x86/ubuntu-18-04/gapbs.img.gz>.
+A pre-built disk image, for X86, can be found, gzipped, here: <http://dist.gem5.org/dist/v21-1/images/x86/ubuntu-18-04/gapbs.img.gz>.
## Building the Disk Image
@@ -33,36 +33,48 @@
After this process succeeds, the disk image can be found on the `src/gapbs/disk-image/gapbs-image/gapbs`.
-GAPBS disk image can support both real and synthetic graph inputs. The current pre-build disk image contains only one graph input which includes the New York city road map (with 733K nodes) it can be found: <http://users.diag.uniroma1.it/challenge9/download.shtml>.
+GAPBS disk image can support both real and synthetic graph inputs. The current pre-built disk image contains only one graph input which includes the New York city road map (with 733K nodes) it can be found: <http://users.diag.uniroma1.it/challenge9/download.shtml>.
To use other graphs simply copy the graph in the gapbs/ directory and add them to gapbs/gapbs.json.
-## gem5 Configuration Scripts
+## Simulating GAPBS using an example script
-gem5 scripts which configure the system and run the simulation are available in `configs/`.
-The main script `run_gapbs.py` expects following arguments:
+An example script with a pre-configured system is available in the following directory within the gem5 repository:
-* **kernel** : A manditory positional argument. The path to the Linux kernel. GAPBS has been tested with [vmlinux-5.2.3](http://dist.gem5.org/dist/v21-1/kernels/x86/static/vmlinux-5.2.3). See `src/linux-kernel` for information on building a linux kernel for gem5.
+```
+gem5/configs/example/gem5_library/x86-gapbs-benchmarks.py
+```
-* **disk** : A mandatory positional argument. The path to the disk image.
+The example script specifies a system with the following parameters:
-* **cpu\_type** : A mandatory positional argument. The cpu model (`kvm`, `atomic`, `simple`, `o3`).
+* A `SimpleSwitchableProcessor` (`KVM` for startup and `TIMING` for ROI execution). There are 2 CPU cores, each clocked at 3 GHz.
+* 2 Level `MESI_Two_Level` cache with 32 kB L1I and L1D size, and, 256 kB L2 size. The L1 cache(s) has associativity of 8, and, the L2 cache has associativity 16. There are 2 L2 cache banks.
+* The system has 3 GB `SingleChannelDDR4_2400` memory.
+* The script uses `x86-linux-kernel-4.19.83` and `x86-gapbs`, the disk image created from following the instructions in this `README.md`.
-* **num\_cpus** : A mandatory positional argument. The number of cpu cores.
-
-* **mem\_sys** : A mandatory positional argument. The memory model (`classic`, `MI_example`, or `MESI_Two_Level`).
-
-* **benchmark** : A mandatory positional argument. The graph workload (`cc`, `bc`, `bfs`, `tc`, `pr`, `sssp`).
-
-* **synthetic** : A mandatory positional argument. The graph type. If synthetic graph then `1`, otherwise `0` for a real world graph.
-
-* **graph** : A mandatory positional argument. If synthetic, then the size of the graph. Otherwise the name of graph to execute.
-
-Example usage:
+The example script must be run with the `X86` binary. To build:
```sh
-<gem5 X86 binary> configs/run_gapbs.py <kernel> <disk> <cpu_type> <num_cpus> <mem_sys> <benchmark> <synthetic> <graph>
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+scons build/X86/gem5.opt -j<proc>
```
+Once compiled, you may use the example config file to run the GAPBS benchmark programs using the following command:
+
+```sh
+# In the gem5 directory
+build/X86/gem5.opt \
+configs/example/gem5_library/x86-gapbs-benchmarks.py \
+--benchmark <benchmark_program> \
+--synthetic <synthetic> \
+--size <size_or_graph_name>
+```
+
+Description of the three arguments, provided in the above command are:
+* **--benchmark**, which refers to one of 5 benchmark programs, provided in the GAP Benchmark Suite. These include `cc`, `bc`, `tc`, `pr` and `bfs`. For more information on the workloads can be found at <http://gap.cs.berkeley.edu/benchmark.html>.
+* **--synthetic** refers whether to use a synthetic or a real graph. It accepts a boolean value.
+* **--size**, which refers to either the size of a synthetic graph from 1 to 16 nodes, or, a real graph. The real graph included in the pre-built disk-image is `USA-road-d.NY.gr`. Note that `--synthetic True` and `--size USA-road-d.NY.gr` cannot be combined, and, vice versa for real graphs.
+
## Working Status
Working status of these tests for gem5-20 can be found [here](https://www.gem5.org/documentation/benchmark_status/gem5-20#gapbs-tests).
diff --git a/src/gapbs/configs/run_gapbs.py b/src/gapbs/configs/run_gapbs.py
deleted file mode 100644
index 997d12c..0000000
--- a/src/gapbs/configs/run_gapbs.py
+++ /dev/null
@@ -1,159 +0,0 @@
-#Copyright (c) 2020 The Regents of the University of California.
-#All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" Script to run GAP Benchmark suites workloads.
- The workloads have two modes: synthetic and real graphs.
-"""
-
-import m5
-import m5.ticks
-from m5.objects import *
-
-import argparse
-
-from system import *
-
-def parse_arguments():
- parser = argparse.ArgumentParser(description=
- "gem5 config file to run GAPBS")
- parser.add_argument("kernel", type = str, help = "Path to vmlinux")
- parser.add_argument("disk", type = str,
- help = "Path to the disk image containing GAPBS")
- parser.add_argument("cpu_type", type = str, help = "Name of the detailed CPU")
- parser.add_argument("num_cpus", type = str, help = "Number of CPUs")
- parser.add_argument("mem_sys", type = str,
- help = "Memory model, Classic or MI_example")
- parser.add_argument("benchmark", type = str,
- help = "Name of the GAPBS")
- parser.add_argument("synthetic", type = int,
- help = "1 for synthetic graph, 0 for real graph")
- parser.add_argument("graph", type = str,
- help = "synthetic=1: integer number. synthetic=0: graph")
- parser.add_argument("-z", "--allow-listeners", default = False,
- action = "store_true",
- help = "Turn on listeners (e.g. gdb listener port);"
- "The listeners are off by default")
- return parser.parse_args()
-
-
-def writeBenchScript(dir, benchmark_name, size, synthetic):
- """
- This method creates a script in dir which will be eventually
- passed to the simulated system (to run a specific benchmark
- at bootup).
- """
- input_file_name = '{}/run_{}_{}'.format(dir, benchmark_name, size)
- if (synthetic):
- with open(input_file_name,"w") as f:
- f.write('./{} -g {}\n'.format(benchmark_name, size))
- elif(synthetic==0):
- with open(input_file_name,"w") as f:
- # The workloads that are copied to the disk image using Packer
- # should be located in /home/gem5/.
- # Since the command running the workload will be executed with
- # pwd = /home/gem5/gapbs, the path to the copied workload is
- # ../{workload-name}
- f.write('./{} -sf ../{}'.format(benchmark_name, size))
-
- return input_file_name
-
-if __name__ == "__m5_main__":
- args = parse_arguments()
-
-
- kernel = args.kernel
- disk = args.disk
- cpu_type = args.cpu_type
- num_cpus = int(args.num_cpus)
- mem_sys = args.mem_sys
- benchmark_name = args.benchmark
- benchmark_size = args.graph
- synthetic = args.synthetic
- allow_listeners = args.allow_listeners
-
- if (mem_sys == "classic"):
- system = MySystem(kernel, disk, cpu_type, num_cpus)
- elif (mem_sys == "MI_example" or "MESI_Two_Level"):
- system = MyRubySystem(kernel, disk, cpu_type, mem_sys, num_cpus)
-
- # For workitems to work correctly
- # This will cause the simulator to exit simulation when the first work
- # item is reached and when the first work item is finished.
- system.work_begin_exit_count = 1
- system.work_end_exit_count = 1
-
- # Read in the script file passed in via an option.
- # This file gets read and executed by the simulated system after boot.
- # Note: The disk image needs to be configured to do this.
-
- system.readfile = writeBenchScript(m5.options.outdir, benchmark_name,
- benchmark_size, synthetic)
-
- # set up the root SimObject and start the simulation
- root = Root(full_system = True, system = system)
-
- if system.getHostParallel():
- # Required for running kvm on multiple host cores.
- # Uses gem5's parallel event queue feature
- # Note: The simulator is quite picky about this number!
- root.sim_quantum = int(1e9) # 1 ms
-
- if not allow_listeners:
- m5.disableAllListeners()
-
- # instantiate all of the objects we've created above
- m5.instantiate()
-
- print("Running the simulation")
- exit_event = m5.simulate()
-
- if exit_event.getCause() == "work started count reach":
- print("Done booting Linux")
- m5.stats.reset()
- start_tick = m5.curTick()
- start_insts = system.totalInsts()
- # switching to atomic cpu if argument cpu == atomic
- if cpu_type != 'kvm':
- system.switchCpus(system.cpu, system.timingCpu)
- print("Switch to detailed cpu model")
- else:
- print("ROI is not annotated!")
- print('Exiting @ tick {} because {}'
- .format(m5.curTick(), exit_event.getCause()))
- exit()
-
- exit_event = m5.simulate()
-
- if exit_event.getCause() == "work items exit count reached":
- m5.stats.dump()
- m5.stats.reset()
- exit_event = m5.simulate()
- m5.stats.dump()
- m5.stats.reset()
- print('Exiting @ tick {} because {}'
- .format(m5.curTick(), exit_event.getCause()))
diff --git a/src/gapbs/configs/system/MESI_Two_Level.py b/src/gapbs/configs/system/MESI_Two_Level.py
deleted file mode 100644
index a327cc5..0000000
--- a/src/gapbs/configs/system/MESI_Two_Level.py
+++ /dev/null
@@ -1,343 +0,0 @@
-#Copyright (c) 2020 The Regents of the University of California.
-#All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MESI TWO Level protocol
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MESITwoLevelCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
- fatal("This system assumes MESI_Two_Level!")
-
- super(MESITwoLevelCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MESI_Two_Level example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU
- # core. The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in \
- range(self._numL2Caches)] + [DirController(self, \
- system.mem_ranges, mem_ctrls)] + [DMAController(self) for i \
- in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = \
- self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
- cpu.itb.walker.port = self.sequencers[i].in_ports
- cpu.dtb.walker.port = self.sequencers[i].in_ports
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False)
- self.l2_select_num_bits = int(math.log(num_l2Caches , 2))
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.enable_prefetch = False
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.out_port = ruby_system.network.in_port
-
- self.optionalQueue = MessageBuffer()
-
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getBlockSizeBits(system,
- num_l2Caches))
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
- self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
-
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/gapbs/configs/system/MI_example_caches.py b/src/gapbs/configs/system/MI_example_caches.py
deleted file mode 100644
index 758c291..0000000
--- a/src/gapbs/configs/system/MI_example_caches.py
+++ /dev/null
@@ -1,278 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2015 Jason Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Power
-
-""" This file creates a set of Ruby caches, the Ruby network, and a simple
-point-to-point topology.
-See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
-You can change simple_ruby to import from this file instead of from msi_caches
-to use the MI_example protocol instead of MSI.
-
-IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
- also needs to be updated. For now, email Jason <jason@lowepower.com>
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MIExampleSystem(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MI_example':
- fatal("This system assumes MI_example!")
-
- super(MIExampleSystem, self).__init__()
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MI example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # Create one controller for each L1 cache (and the cache mem obj.)
- # Create a single directory controller (Really the memory cntrl)
- self.controllers = \
- [L1Cache(system, self, cpu) for cpu in cpus] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU. In many systems this is more
- # complicated since you have to create sequencers for DMA controllers
- # and other controllers, too.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].cacheMemory,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[0:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = \
- self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu):
- """CPUs are needed to grab the clock domain and system is needed for
- the cache block size.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.cacheMemory = RubyCache(size = '16kB',
- assoc = 8,
- start_index_bit = self.getBlockSizeBits(system))
- self.clk_domain = cpu.clk_domain
- self.send_evictions = self.sendEvicts(cpu)
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromCache = MessageBuffer(ordered = True)
- self.requestFromCache.out_port = ruby_system.network.in_port
- self.responseFromCache = MessageBuffer(ordered = True)
- self.responseFromCache.out_port = ruby_system.network.in_port
- self.forwardToCache = MessageBuffer(ordered = True)
- self.forwardToCache.in_port = ruby_system.network.out_port
- self.responseToCache = MessageBuffer(ordered = True)
- self.responseToCache.in_port = ruby_system.network.out_port
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer(ordered = True)
- self.requestToDir.in_port = ruby_system.network.out_port
- self.dmaRequestToDir = MessageBuffer(ordered = True)
- self.dmaRequestToDir.in_port = ruby_system.network.out_port
-
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.dmaResponseFromDir = MessageBuffer(ordered = True)
- self.dmaResponseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/gapbs/configs/system/MOESI_CMP_directory.py b/src/gapbs/configs/system/MOESI_CMP_directory.py
deleted file mode 100644
index f24022a..0000000
--- a/src/gapbs/configs/system/MOESI_CMP_directory.py
+++ /dev/null
@@ -1,351 +0,0 @@
-#Copyright (c) 2020 The Regents of the University of California.
-#All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MOESI CMP directory
-protocol.
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MOESICMPDirCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
- fatal("This system assumes MOESI_CMP_directory!")
-
- super(MOESICMPDirCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MOESI_CMP_directory example uses 3 virtual networks
- self.number_of_virtual_networks = 3
- self.network.number_of_virtual_networks = 3
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU
- # core. The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in \
- range(self._numL2Caches)] + [DirController(self, \
- system.mem_ranges, mem_ctrls)] + [DMAController(self) for i \
- in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # I/D cache is combined and grab from ctrl
- icache = self.controllers[i].L1Icache,
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_ports
- cpu.dtb.walker.port = self.sequencers[i].in_ports
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getL2StartIdx(system,
- num_l2Caches),
- dataAccessLatency = 20,
- tagAccessLatency = 20)
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getL2StartIdx(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.GlobalRequestFromL2Cache = MessageBuffer()
- self.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
-
- self.GlobalRequestToL2Cache = MessageBuffer()
- self.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.reqToDir = MessageBuffer()
- self.reqToDir.out_port = ruby_system.network.in_port
- self.respToDir = MessageBuffer()
- self.respToDir.out_port = ruby_system.network.in_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/gapbs/configs/system/__init__.py b/src/gapbs/configs/system/__init__.py
deleted file mode 100644
index 1bce258..0000000
--- a/src/gapbs/configs/system/__init__.py
+++ /dev/null
@@ -1,32 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from .system import MySystem
-from .ruby_system import MyRubySystem
-
diff --git a/src/gapbs/configs/system/caches.py b/src/gapbs/configs/system/caches.py
deleted file mode 100644
index 049a695..0000000
--- a/src/gapbs/configs/system/caches.py
+++ /dev/null
@@ -1,143 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-""" Caches with options for a simple gem5 configuration script
-
-This file contains L1 I/D and L2 caches to be used in the simple
-gem5 configuration script.
-"""
-
-from m5.objects import Cache, L2XBar, StridePrefetcher
-
-# Some specific options for caches
-# For all options see src/mem/cache/BaseCache.py
-
-class PrefetchCache(Cache):
-
- def __init__(self):
- super(PrefetchCache, self).__init__()
- self.prefetcher = StridePrefetcher()
-
-class L1Cache(PrefetchCache):
- """Simple L1 Cache with default values"""
-
- assoc = 8
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 16
- tgts_per_mshr = 20
- writeback_clean = True
-
- def __init__(self):
- super(L1Cache, self).__init__()
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU-side port
- This must be defined in a subclass"""
- raise NotImplementedError
-
-class L1ICache(L1Cache):
- """Simple L1 instruction cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1ICache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU icache port"""
- self.cpu_side = cpu.icache_port
-
-class L1DCache(L1Cache):
- """Simple L1 data cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1DCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU dcache port"""
- self.cpu_side = cpu.dcache_port
-
-class MMUCache(Cache):
- # Default parameters
- size = '8kB'
- assoc = 4
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(MMUCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect the CPU itb and dtb to the cache
- Note: This creates a new crossbar
- """
- self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
-class L2Cache(PrefetchCache):
- """Simple L2 Cache with default values"""
-
- # Default parameters
- size = '256kB'
- assoc = 16
- tag_latency = 10
- data_latency = 10
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(L2Cache, self).__init__()
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
diff --git a/src/gapbs/configs/system/fs_tools.py b/src/gapbs/configs/system/fs_tools.py
deleted file mode 100644
index 5e5e2df..0000000
--- a/src/gapbs/configs/system/fs_tools.py
+++ /dev/null
@@ -1,39 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
-
-class CowDisk(IdeDisk):
-
- def __init__(self, filename):
- super(CowDisk, self).__init__()
- self.driveID = 'device0'
- self.image = CowDiskImage(child=RawDiskImage(read_only=True),
- read_only=False)
- self.image.child.image_file = filename
diff --git a/src/gapbs/configs/system/ruby_system.py b/src/gapbs/configs/system/ruby_system.py
deleted file mode 100644
index c2a2b58..0000000
--- a/src/gapbs/configs/system/ruby_system.py
+++ /dev/null
@@ -1,231 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-
-
-class MyRubySystem(System):
-
- def __init__(self, kernel, disk, cpu_type, mem_sys, num_cpus):
- super(MyRubySystem, self).__init__()
-
- self._host_parallel = cpu_type == "kvm"
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- self.initFS(num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(cpu_type, num_cpus)
-
- self.createMemoryControllersDDR3()
-
- # Create the cache hierarchy for the system.
- if mem_sys == 'MI_example':
- from .MI_example_caches import MIExampleSystem
- self.caches = MIExampleSystem()
- elif mem_sys == 'MESI_Two_Level':
- from .MESI_Two_Level import MESITwoLevelCache
- self.caches = MESITwoLevelCache()
- elif mem_sys == 'MOESI_CMP_directory':
- from .MOESI_CMP_directory import MOESICMPDirCache
- self.caches = MOESICMPDirCache()
- self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports],
- self.iobus)
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPU(self, cpu_type, num_cpus):
- if cpu_type == "atomic":
- self.cpu = [AtomicSimpleCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.mem_mode = 'atomic'
- elif cpu_type == "kvm":
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
- elif cpu_type == "o3":
- self.cpu = [DerivO3CPU(cpu_id = i)
- for i in range(num_cpus)]
- self.mem_mode = 'timing'
- elif cpu_type == "simple":
- self.cpu = [TimingSimpleCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.mem_mode = 'timing'
- else:
- m5.fatal("No CPU type {}".format(cpu_type))
-
- for cpu in self.cpu:
- cpu.createThreads()
- cpu.createInterruptController()
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createMemoryControllersDDR3(self):
- self._createMemoryControllers(1, DDR3_1600_8x8)
-
- def _createMemoryControllers(self, num, cls):
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = self.mem_ranges[0]))
- for i in range(num)
- ]
-
- def initFS(self, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # North Bridge
- self.iobus = IOXBar()
-
- # connect the io bus
- # Note: pass in a reference to where Ruby will connect to in the future
- # so the port isn't connected twice.
- self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/gapbs/configs/system/system.py b/src/gapbs/configs/system/system.py
deleted file mode 100644
index dbb11b9..0000000
--- a/src/gapbs/configs/system/system.py
+++ /dev/null
@@ -1,340 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-from .caches import *
-
-class MySystem(System):
-
- def __init__(self, kernel, disk, cpu_type, num_cpus, no_kvm = False):
- super(MySystem, self).__init__()
-
- self._no_kvm = no_kvm
- self._host_parallel = cpu_type == "kvm"
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- # Create the main memory bus
- # This connects to main memory
- self.membus = SystemXBar(width = 64) # 64-byte width
- self.membus.badaddr_responder = BadAddr()
- self.membus.default = Self.badaddr_responder.pio
-
- # Set up the system port for functional access from the simulator
- self.system_port = self.membus.cpu_side_ports
-
- self.initFS(self.membus, num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(cpu_type, num_cpus)
-
- # Create the cache heirarchy for the system.
- self.createCacheHierarchy()
-
- # Set up the interrupt controllers for the system (x86 specific)
- self.setupInterrupts()
-
- self.createMemoryControllersDDR3()
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPU(self, cpu_type, num_cpus):
- # set up a kvm core or an atomic core to boot
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.mem_mode = 'atomic'
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- for cpu in self.cpu:
- cpu.createThreads()
- cpu.createInterruptController()
-
- # set up the detailed cpu or a kvm model with more cores
- if cpu_type == "atomic":
- self.detailedCpu = [AtomicSimpleCPU(cpu_id = i, switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.detailedCpu)
- elif cpu_type == "kvm":
- # Note KVM needs a VM and atomic_noncaching
- self.detailedCpu = [X86KvmCPU(cpu_id = i, switched_out = True)
- for i in range(num_cpus)]
- self.kvm_vm = KvmVM()
- self.createCPUThreads(self.detailedCpu)
- elif cpu_type == "o3":
- self.detailedCpu = [DerivO3CPU(cpu_id = i, switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.detailedCpu)
- elif cpu_type == "simple" or cpu_type == "timing":
- self.detailedCpu = [TimingSimpleCPU(cpu_id = i, switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.detailedCpu)
- else:
- m5.fatal("No CPU type {}".format(cpu_type))
-
- for cpu in self.detailedCpu:
- cpu.createThreads()
- cpu.createInterruptController()
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createCacheHierarchy(self):
- for cpu in self.cpu:
- # Create a memory bus, a coherent crossbar, in this case
- cpu.l2bus = L2XBar()
-
- # Create an L1 instruction and data cache
- cpu.icache = L1ICache()
- cpu.dcache = L1DCache()
- cpu.mmucache = MMUCache()
-
- # Connect the instruction and data caches to the CPU
- cpu.icache.connectCPU(cpu)
- cpu.dcache.connectCPU(cpu)
- cpu.mmucache.connectCPU(cpu)
-
- # Hook the CPU ports up to the l2bus
- cpu.icache.connectBus(cpu.l2bus)
- cpu.dcache.connectBus(cpu.l2bus)
- cpu.mmucache.connectBus(cpu.l2bus)
-
- # Create an L2 cache and connect it to the l2bus
- cpu.l2cache = L2Cache()
- cpu.l2cache.connectCPUSideBus(cpu.l2bus)
-
- # Connect the L2 cache to the L3 bus
- cpu.l2cache.connectMemSideBus(self.membus)
-
- def setupInterrupts(self):
- for cpu in self.cpu:
- # create the interrupt controller CPU and connect to the membus
- cpu.createInterruptController()
-
- # For x86 only, connect interrupts to the memory
- # Note: these are directly connected to the memory bus and
- # not cached
- cpu.interrupts[0].pio = self.membus.mem_side_ports
- cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
- cpu.interrupts[0].int_responder = self.membus.mem_side_ports
-
-
- def createMemoryControllersDDR3(self):
- self._createMemoryControllers(1, DDR3_1600_8x8)
-
- def _createMemoryControllers(self, num, cls):
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = self.mem_ranges[0]),
- port = self.membus.mem_side_ports)
- for i in range(num)
- ]
-
- def initFS(self, membus, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # Constants similar to x86_traits.hh
- IO_address_space_base = 0x8000000000000000
- pci_config_address_space_base = 0xc000000000000000
- interrupts_address_space_base = 0xa000000000000000
- APIC_range_size = 1 << 12;
-
- # North Bridge
- self.iobus = IOXBar()
- self.bridge = Bridge(delay='50ns')
- self.bridge.mem_side_port = self.iobus.cpu_side_ports
- self.bridge.cpu_side_port = membus.mem_side_ports
- # Allow the bridge to pass through:
- # 1) kernel configured PCI device memory map address: address range
- # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
- # 2) the bridge to pass through the IO APIC (two pages, already
- # contained in 1),
- # 3) everything in the IO address range up to the local APIC, and
- # 4) then the entire PCI address space and beyond.
- self.bridge.ranges = \
- [
- AddrRange(0xC0000000, 0xFFFF0000),
- AddrRange(IO_address_space_base,
- interrupts_address_space_base - 1),
- AddrRange(pci_config_address_space_base,
- Addr.max)
- ]
-
- # Create a bridge from the IO bus to the memory bus to allow access
- # to the local APIC (two pages)
- self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
- self.apicbridge.mem_side_port = membus.cpu_side_ports
- self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
- interrupts_address_space_base +
- cpus * APIC_range_size
- - 1)]
-
- # connect the io bus
- self.pc.attachIO(self.iobus)
-
- # Add a tiny cache to the IO bus.
- # This cache is required for the classic memory model for coherence
- self.iocache = Cache(assoc=8,
- tag_latency = 50,
- data_latency = 50,
- response_latency = 50,
- mshrs = 20,
- size = '1kB',
- tgts_per_mshr = 12,
- addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.mem_side_ports
- self.iocache.mem_side = self.membus.cpu_side_ports
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/gpu/halo-finder/Dockerfile b/src/gpu/halo-finder/Dockerfile
index f02483e..e3ddf6b 100644
--- a/src/gpu/halo-finder/Dockerfile
+++ b/src/gpu/halo-finder/Dockerfile
@@ -1,20 +1,22 @@
-FROM gcr.io/gem5-test/gcn-gpu
+FROM gcr.io/gem5-test/gcn-gpu:latest
RUN apt-get update && apt-get -y install libopenmpi-dev libomp-dev
+ENV HCC_AMDGPU_TARGET="gfx801,gfx803"
+
ENV HIPCC_BIN=/opt/rocm/bin
-ENV MPI_INCLUDE=/usr/lib/openmpi/include
+ENV MPI_INCLUDE=/usr/lib/x86_64-linux-gnu/openmpi/include
ENV OPT="-O3 -g -DRCB_UNTHREADED_BUILD -DUSE_SERIAL_COSMO"
-ENV OMP="-fopenmp"
+ENV OMP="-I/usr/lib/llvm-10/include/openmp -L/usr/lib/llvm-10/lib -fopenmp"
ENV HIPCC_FLAGS="-v -ffast_math -DINLINE_FORCE -I${MPI_INCLUDE}"
-ENV HIPCC_FLAGS="-v -I${MPI_INCLUDE} -I/opt/rocm/hip/include -I/opt/rocm/hcc-1.0/include"
+ENV HIPCC_FLAGS="-v -I${MPI_INCLUDE} -I/opt/rocm/hip/include"
ENV HACC_PLATFORM="hip"
ENV HACC_OBJDIR="${HACC_PLATFORM}"
ENV HACC_CFLAGS="$OPT $OMP $HIPCC_FLAGS"
-ENV HACC_CC="${HIPCC_BIN}/hcc -x c -Xclang -std=c99"
+ENV HACC_CC="${HIPCC_BIN}/hipcc -x c -Xclang -std=c99"
ENV HACC_CXXFLAGS="$OPT $OMP $HIPCC_FLAGS"
ENV HACC_CXX="${HIPCC_BIN}/hipcc -Xclang"
@@ -26,7 +28,7 @@
ENV USE_SERIAL_COSMO="1"
ENV HACC_NUM_CUDA_DEV="1"
ENV HACC_MPI_CFLAGS="$OPT $OMP $HIPCC_FLAGS"
-ENV HACC_MPI_CC="${HIPCC_BIN}/hcc -x c -Xclang -std=c99 -Xclang -pthread"
+ENV HACC_MPI_CC="${HIPCC_BIN}/hipcc -x c -Xclang -std=c99 -Xclang -pthread"
ENV HACC_MPI_CXXFLAGS="$OPT $OMP $HIPCC_FLAGS"
ENV HACC_MPI_CXX="${HIPCC_BIN}/hipcc -Xclang -pthread"
diff --git a/src/gpu/halo-finder/README.md b/src/gpu/halo-finder/README.md
index cbfb685..e52b069 100644
--- a/src/gpu/halo-finder/README.md
+++ b/src/gpu/halo-finder/README.md
@@ -33,6 +33,9 @@
In order to test the GPU code in halo-finder, we compile and run ForceTreeTest.
To build the Docker image and the benchmark:
+
+Note: HACC requires a number of environment variables to be set to compile and run correctly. Our Dockerfile sets these flags appropriately for you. This Dockerfile automatically runs when a new docker image is created, including building for both gfx801 and gfx803, which is why our instructions below recommend doing this. If you would prefer not doing this, then you will need to pass in these environment variables using -e.
+
```
cd src/gpu/halo-finder
docker build -t <image_name> .
diff --git a/src/gpu/halo-finder/src/ForceTreeTest.cxx b/src/gpu/halo-finder/src/ForceTreeTest.cxx
index 176fb1f..9a5e4ef 100644
--- a/src/gpu/halo-finder/src/ForceTreeTest.cxx
+++ b/src/gpu/halo-finder/src/ForceTreeTest.cxx
@@ -5,6 +5,7 @@
//newton should match theory prediction
//short range may not due to lack of gauss law
+#include "hip/hip_runtime.h"
#include <cassert>
#include <cmath>
#include <iostream>
@@ -79,13 +80,30 @@
float m_rsm = 0.1;
int Np = nSphere+1;
- POSVEL_T* m_xArr = new POSVEL_T[Np];
- POSVEL_T* m_yArr = new POSVEL_T[Np];
- POSVEL_T* m_zArr = new POSVEL_T[Np];
- POSVEL_T* m_vxArr = new POSVEL_T[Np];
- POSVEL_T* m_vyArr = new POSVEL_T[Np];
- POSVEL_T* m_vzArr = new POSVEL_T[Np];
- POSVEL_T* m_massArr = new POSVEL_T[Np];
+
+ POSVEL_T* m_xArr;
+ hipHostMalloc(&m_xArr, Np*sizeof(POSVEL_T));
+ POSVEL_T* m_yArr;
+ hipHostMalloc(&m_yArr, Np*sizeof(POSVEL_T));
+ POSVEL_T* m_zArr;
+ hipHostMalloc(&m_zArr, Np*sizeof(POSVEL_T));
+ POSVEL_T* m_vxArr;
+ hipHostMalloc(&m_vxArr, Np*sizeof(POSVEL_T));
+ POSVEL_T* m_vyArr;
+ hipHostMalloc(&m_vyArr, Np*sizeof(POSVEL_T));
+ POSVEL_T* m_vzArr;
+ hipHostMalloc(&m_vzArr, Np*sizeof(POSVEL_T));
+ POSVEL_T* m_massArr;
+ hipHostMalloc(&m_massArr, Np*sizeof(POSVEL_T));
+ for(int i = 0; i < Np; i++) {
+ m_xArr[i] = 0;
+ m_yArr[i] = 0;
+ m_zArr[i] = 0;
+ m_vxArr[i] = 0;
+ m_vyArr[i] = 0;
+ m_vzArr[i] = 0;
+ m_massArr[i] = 0;
+ }
FGrid *m_fg = new FGrid();
FGridEval *m_fgore = new FGridEvalFit(m_fg);
@@ -308,13 +326,13 @@
delete m_fgore;
delete m_fg;
- delete [] m_xArr;
- delete [] m_yArr;
- delete [] m_zArr;
- delete [] m_vxArr;
- delete [] m_vyArr;
- delete [] m_vzArr;
- delete [] m_massArr;
+ hipHostFree(m_xArr);
+ hipHostFree(m_yArr);
+ hipHostFree(m_zArr);
+ hipHostFree(m_vxArr);
+ hipHostFree(m_vyArr);
+ hipHostFree(m_vzArr);
+ hipHostFree(m_massArr);
#ifndef USE_SERIAL_COSMO
MPI_Finalize();
diff --git a/src/gpu/halo-finder/src/RCBForceTree.cxx b/src/gpu/halo-finder/src/RCBForceTree.cxx
index 8774902..0c18dd3 100644
--- a/src/gpu/halo-finder/src/RCBForceTree.cxx
+++ b/src/gpu/halo-finder/src/RCBForceTree.cxx
@@ -405,37 +405,47 @@
// static size for the interaction list
#define VMAX ALIGNY(16384)
- nx_v=(POSVEL_T*)malloc(VMAX*sizeof(POSVEL_T)*numThreads);
- ny_v=(POSVEL_T*)malloc(VMAX*sizeof(POSVEL_T)*numThreads);
- nz_v=(POSVEL_T*)malloc(VMAX*sizeof(POSVEL_T)*numThreads);
- nm_v=(POSVEL_T*)malloc(VMAX*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&nx_v, VMAX*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&ny_v, VMAX*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&nz_v, VMAX*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&nm_v, VMAX*sizeof(POSVEL_T)*numThreads);
+ for(int i = 0; i < VMAX*numThreads; i++) {
+ nx_v[i] = 0;
+ ny_v[i] = 0;
+ nz_v[i] = 0;
+ nm_v[i] = 0;
+ }
+
#ifdef __HIPCC__
- hipHostRegister(nx_v,VMAX*sizeof(POSVEL_T)*numThreads,0);
- hipHostRegister(ny_v,VMAX*sizeof(POSVEL_T)*numThreads,0);
- hipHostRegister(nz_v,VMAX*sizeof(POSVEL_T)*numThreads,0);
- hipHostRegister(nm_v,VMAX*sizeof(POSVEL_T)*numThreads,0);
- hipHostRegister(xx,count*sizeof(POSVEL_T),0);
- hipHostRegister(yy,count*sizeof(POSVEL_T),0);
- hipHostRegister(zz,count*sizeof(POSVEL_T),0);
- hipHostRegister(mass,count*sizeof(POSVEL_T),0);
- hipHostRegister(vx,count*sizeof(POSVEL_T),0);
- hipHostRegister(vy,count*sizeof(POSVEL_T),0);
- hipHostRegister(vz,count*sizeof(POSVEL_T),0);
-
int size=ALIGNY(nd);
- hipMalloc(&d_xx,size*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_yy,size*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_zz,size*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_vx,size*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_vy,size*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_vz,size*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_mass,size*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_xx,size*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_yy,size*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_zz,size*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_vx,size*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_vy,size*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_vz,size*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_mass,size*sizeof(POSVEL_T)*numThreads);
+ for(int i = 0; i < size*numThreads; i++) {
+ d_xx[i] = 0;
+ d_yy[i] = 0;
+ d_zz[i] = 0;
+ d_vx[i] = 0;
+ d_vy[i] = 0;
+ d_vz[i] = 0;
+ d_mass[i] = 0;
+ }
- hipMalloc(&d_nx_v,VMAX*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_ny_v,VMAX*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_nz_v,VMAX*sizeof(POSVEL_T)*numThreads);
- hipMalloc(&d_nm_v,VMAX*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_nx_v,VMAX*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_ny_v,VMAX*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_nz_v,VMAX*sizeof(POSVEL_T)*numThreads);
+ hipHostMalloc(&d_nm_v,VMAX*sizeof(POSVEL_T)*numThreads);
+ for(int i = 0; i < VMAX*numThreads; i++) {
+ d_nx_v[i] = 0;
+ d_ny_v[i] = 0;
+ d_nz_v[i] = 0;
+ d_nm_v[i] = 0;
+ }
cudaCheckError();
@@ -545,29 +555,17 @@
delete m_fl;
}
#ifdef __HIPCC__
- hipHostUnregister(xx);
- hipHostUnregister(yy);
- hipHostUnregister(zz);
- hipHostUnregister(mass);
- hipHostUnregister(vx);
- hipHostUnregister(vy);
- hipHostUnregister(vz);
- hipHostUnregister(nx_v);
- hipHostUnregister(ny_v);
- hipHostUnregister(nz_v);
- hipHostUnregister(nm_v);
-
- hipFree(d_xx);
- hipFree(d_yy);
- hipFree(d_zz);
- hipFree(d_vx);
- hipFree(d_vy);
- hipFree(d_vz);
- hipFree(d_mass);
- hipFree(d_nx_v);
- hipFree(d_ny_v);
- hipFree(d_nz_v);
- hipFree(d_nm_v);
+ hipHostFree(d_xx);
+ hipHostFree(d_yy);
+ hipHostFree(d_zz);
+ hipHostFree(d_vx);
+ hipHostFree(d_vy);
+ hipHostFree(d_vz);
+ hipHostFree(d_mass);
+ hipHostFree(d_nx_v);
+ hipHostFree(d_ny_v);
+ hipHostFree(d_nz_v);
+ hipHostFree(d_nm_v);
cudaCheckError();
for(int i=0;i<numThreads;i++) {
@@ -580,10 +578,10 @@
free(stream_v);
#endif
- free(nx_v);
- free(ny_v);
- free(nz_v);
- free(nm_v);
+ hipHostFree(nx_v);
+ hipHostFree(ny_v);
+ hipHostFree(nz_v);
+ hipHostFree(nm_v);
#ifdef __HIPCC__
//nvtxRangeEnd(r0);
#endif
@@ -859,9 +857,13 @@
POSVEL_T zzj[TILEX];
POSVEL_T massj[TILEX];
+ // Consolidate variables to help fit within the register limit
+ int x_idx = hipBlockIdx_x*hipBlockDim_x+hipThreadIdx_x;
+ int y_idx = hipBlockIdx_y*hipBlockDim_y+hipThreadIdx_y;
+
//loop over interior region and calculate forces.
//for each tile i
- for(int i=hipBlockIdx_y*hipBlockDim_y+hipThreadIdx_y;i<count/TILEY;i+=hipBlockDim_y*hipGridDim_y) //1 ISETP
+ for(int i=y_idx;i<count/TILEY;i+=hipBlockDim_y*hipGridDim_y) //1 ISETP
{
POSVEL_T xi[TILEY]={0}; //TILEY MOV
POSVEL_T yi[TILEY]={0}; //TILEY MOV
@@ -871,7 +873,7 @@
loadTile<false,false,TILEY>(i,count,xx,yy,zz,NULL,xxi,yyi,zzi,NULL);
//for each tile j
- for (int j=hipBlockIdx_x*hipBlockDim_x+hipThreadIdx_x;j<count1/TILEX;j+=hipBlockDim_x*hipGridDim_x) //1 ISETP
+ for (int j=x_idx;j<count1/TILEX;j+=hipBlockDim_x*hipGridDim_x) //1 ISETP
{
//load tile j, bounds check is not needed
loadTile<false,true,TILEX>(j,count1,xx1,yy1,zz1,mass1,xxj,yyj,zzj,massj);
@@ -881,7 +883,7 @@
}
//process remaining elements at the end, use TILEX=1
- for (int j=count1/TILEX*TILEX+hipBlockIdx_x*hipBlockDim_x+hipThreadIdx_x;j<count1;j+=hipBlockDim_x*hipGridDim_x) //1 ISETP
+ for (int j=count1/TILEX*TILEX+x_idx;j<count1;j+=hipBlockDim_x*hipGridDim_x) //1 ISETP
{
//load tile j, bounds check is needed, mass is needed
loadTile<true,true,1>(j,count1,xx1,yy1,zz1,mass1,xxj,yyj,zzj,massj);
@@ -900,17 +902,19 @@
#if 1
//process ramining elements in set TILEY=1
//for each tile i
- for(int i=count/TILEY*TILEY+hipBlockIdx_y*hipBlockDim_y+hipThreadIdx_y;i<count;i+=hipBlockDim_y*hipGridDim_y) //1 ISETP
+ for(int i=y_idx;i<count - count/TILEY*TILEY;i+=hipBlockDim_y*hipGridDim_y) //1 ISETP
{
+ // Taken out of the loop condition to help fit within the register limit
+ int k = i + count/TILEY*TILEY;
POSVEL_T xi[1]={0}; //1 MOV
POSVEL_T yi[1]={0}; //1 MOV
POSVEL_T zi[1]={0}; //1 MOV
//load xxi, yyi, zzi tiles, mass is not needed, bounds check is needed
- loadTile<true,false,1>(i,count,xx,yy,zz,NULL,xxi,yyi,zzi,NULL);
+ loadTile<true,false,1>(k,count,xx,yy,zz,NULL,xxi,yyi,zzi,NULL);
//for each tile j
- for (int j=hipBlockIdx_x*hipBlockDim_x+hipThreadIdx_x;j<count1/TILEX;j+=hipBlockDim_x*hipGridDim_x) //1 ISETP
+ for (int j=x_idx;j<count1/TILEX;j+=hipBlockDim_x*hipGridDim_x) //1 ISETP
{
//load tile j, bounds check is not needed
loadTile<false,true,TILEX>(j,count1,xx1,yy1,zz1,mass1,xxj,yyj,zzj,massj);
@@ -920,7 +924,7 @@
}
//process remaining elements at the end, use TILEX=1
- for (int j=count1/TILEX*TILEX+hipBlockIdx_x*hipBlockDim_x+hipThreadIdx_x;j<count1;j+=hipBlockDim_x*hipGridDim_x) //1 ISETP
+ for (int j=count1/TILEX*TILEX+x_idx;j<count1;j+=hipBlockDim_x*hipGridDim_x) //1 ISETP
{
//load tile j, bounds check is needed, mass is needed
loadTile<true,true,1>(j,count1,xx1,yy1,zz1,mass1,xxj,yyj,zzj,massj);
@@ -929,7 +933,7 @@
computeForces<1,1>(xxi,yyi,zzi,xxj,yyj,zzj,massj,xi,yi,zi,ma0,ma1,ma2,ma3,ma4,ma5,mp_rsm2,fsrrmax2);
}
- applyForce<true,1>(i,count,fcoeff,xi,yi,zi,vx,vy,vz);
+ applyForce<true,1>(k,count,fcoeff,xi,yi,zi,vx,vy,vz);
}
#endif
@@ -998,10 +1002,11 @@
checkCudaPtr(vy,"vy");
checkCudaPtr(vz,"vz");
#endif
+
hipLaunchKernelGGL(Step10_cuda_kernel, dim3(blocks), dim3(threads), 0, stream, count,count1,xx,yy,zz,mass,xx1,yy1,zz1,mass1, vx, vy, vz, fsrrmax2, rsm2, fcoeff);
cudaCheckError();
- //hipDeviceSynchronize();
+ hipStreamSynchronize(stream);
//exit(0);
#else
@@ -1051,7 +1056,7 @@
}
}
-#pragma unroll (4)
+#pragma unroll 4
for ( j = 0; j < is; j++ )
{
i = idx[j];
@@ -1062,7 +1067,7 @@
i0 = id [i]; id [i] = id [j]; id [j] = i0;
}
-#pragma unroll (4)
+#pragma unroll 4
for ( j = 0; j < is; j++ )
{
i = idx[j];
@@ -1500,7 +1505,7 @@
hipMemcpyAsync(d_nm,nm,sizeof(POSVEL_T)*SIZE,hipMemcpyHostToDevice,stream);
hipEventRecord(event,stream); //mark when transfers have finished
cudaCheckError();
- hipDeviceSynchronize();
+ hipStreamSynchronize(stream);
hipMemcpyAsync(d_xxl,xx+off,sizeof(POSVEL_T)*cnt,hipMemcpyHostToDevice,stream);
@@ -1511,13 +1516,13 @@
hipMemcpyAsync(d_vyl,vy+off,sizeof(POSVEL_T)*cnt,hipMemcpyHostToDevice,stream);
hipMemcpyAsync(d_vzl,vz+off,sizeof(POSVEL_T)*cnt,hipMemcpyHostToDevice,stream);
cudaCheckError();
- hipDeviceSynchronize();
+ hipStreamSynchronize(stream);
#endif
// Process the interaction list...
#ifdef __HIPCC__
::nbody1(cnt, SIZE, d_xxl, d_yyl, d_zzl, d_massl, d_nx, d_ny, d_nz, d_nm, d_vxl, d_vyl, d_vzl, m_fl, m_fcoeff, fsrrmax, rsm, stream);
- hipDeviceSynchronize();
+ hipStreamSynchronize(stream);
#else
::nbody1(cnt, SIZE, xx + off, yy + off, zz + off, mass + off, nx, ny, nz, nm, vx + off, vy + off, vz + off, m_fl, m_fcoeff, fsrrmax, rsm);
#endif
@@ -1528,7 +1533,7 @@
hipMemcpyAsync(vy+off,d_vyl,sizeof(POSVEL_T)*cnt,hipMemcpyDeviceToHost,stream);
hipMemcpyAsync(vz+off,d_vzl,sizeof(POSVEL_T)*cnt,hipMemcpyDeviceToHost,stream);
cudaCheckError();
- hipDeviceSynchronize();
+ hipStreamSynchronize(stream);
#endif
}
diff --git a/src/gpu/heterosync/README.md b/src/gpu/heterosync/README.md
index bba6547..c7c3d51 100644
--- a/src/gpu/heterosync/README.md
+++ b/src/gpu/heterosync/README.md
@@ -28,6 +28,14 @@
GCN3-based dGPU. There are other targets (release) that build for GPU types
that are currently unsupported in gem5.
+## Running HeterSync on GCN3_X86/gem5.opt
+
+HeteroSync has multiple applications that can be run (see below). For example, to run sleepMutex with 10 ld/st per thread, 16 WGs, and 4 iterations of the critical section:
+
+```
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n 3 -c bin/allSyncPrims-1kernel --options="sleepMutex 10 16 4"
+```
+
## Pre-built binary
<http://dist.gem5.org/dist/v21-1/test-progs/heterosync/gcn3/allSyncPrims-1kernel>
@@ -49,7 +57,7 @@
3. Fetch-and-Add (FA) Mutex Lock (similar to Ticket/Queue-style Locks): To make their spin lock fair and have a deterministic number of atomic accesses per operation they also implement this queue-style spin lock. Every TB uses an atomic to get a "ticket" for when they'll get the lock. The TBs poll the “current ticket” location until their turn arrives (when it does they acquire the lock). FAMutex uses backoff in the polling section of this lock to reduce contention.
4. Ring Buffer-based Sleeping Mutex Lock: Each TB places itself on the end of the buffer and repeatedly checks if is now at the front of the buffer. To unlock they increment the head pointer. In the original paper they found that performance is bad for this one because it requires more reads and writes to the head pointer are serialized.
- Centralized Semaphores:
- 1. Spin Lock Semaphore: To approximate the "perform OP if > 0" feature of semaphores (on CPUs) they use atomicExch's to block the TB until the exchange returns true. Requires more reads and writes on a GPU than a mutex. Each TB sets the semaphore to the appropriate new values in the post and wait phases depending on the current capacity of the semaphore.
+ 1. Spin Lock Semaphore: To approximate the "perform OP if > 0" feature of semaphores (on CPUs) they use atomicExch's to block the TB until the exchange returns true. Requires more reads and writes on a GPU than a mutex. Each TB sets the semaphore to the appropriate new values in the post and wait phases depending on the current capacity of the semaphore.
2. Spin Lock Semaphore with Backoff: As with the mutexes, they add a linear backoff to decrease contention. The backoff is only in the wait() phase because usually more TBs are waiting, not posting.
- Barriers:
1. Atomic Barrier: a two-stage atomic counter barrier. There are several versions of this barrier: a tree barrier and a second version that exchanges data locally on a CU before joining the global tree barrier.
@@ -70,91 +78,51 @@
The usage of the microbenchmarks is as follows:
-./allSyncPrims-1kernel <syncPrim> <numLdSt> <numTBs> <numCSIters>
+./allSyncPrims-1kernel <syncPrim> <numLdSt> <numTBs> <numCSIters>
-<syncPrim> is a string that differs for each synchronization primitive to be run:
+where <syncPrim> is a string that differs for each synchronization primitive to be run:
// Barriers use hybrid local-global synchronization
- - atomicTreeBarrUniq - atomic tree barrier
- - atomicTreeBarrUniqLocalExch - atomic tree barrier with local exchange
- - lfTreeBarrUniq - lock-free tree barrier
- - lfTreeBarrUniqLocalExch - lock-free tree barrier with local exchange
+ * atomicTreeBarrUniq: atomic tree barrier
+ * atomicTreeBarrUniqLocalExch: atomic tree barrier with local exchange
+ * lfTreeBarrUniq: lock*free tree barrier
+ * lfTreeBarrUniqLocalExch: lock*free tree barrier with local exchange
// global synchronization versions
- - spinMutex - spin lock mutex
- - spinMutexEBO - spin lock mutex with exponential backoff
- - sleepMutex - decentralized ticket lock
- - faMutex - centralized ticket lock (aka, fetch-and-add mutex)
- - spinSem1 - spin lock semaphore, semaphore size 1
- - spinSem2 - spin lock semaphore, semaphore size 2
- - spinSem10 - spin lock semaphore, semaphore size 10
- - spinSem120 - spin lock semaphore, semaphore size 120
- - spinSemEBO1 - spin lock semaphore with exponential backoff, semaphore size 1
- - spinSemEBO2 - spin lock semaphore with exponential backoff, semaphore size 2
- - spinSemEBO10 - spin lock semaphore with exponential backoff, semaphore size 10
- - spinSemEBO120 - spin lock semaphore with exponential backoff, semaphore size 120
+ * spinMutex: spin lock mutex
+ * spinMutexEBO: spin lock mutex with exponential backoff
+ * sleepMutex: decentralized ticket lock
+ * faMutex: centralized ticket lock (aka, fetch*and*add mutex)
+ * spinSem1: spin lock semaphore, semaphore size 1
+ * spinSem2: spin lock semaphore, semaphore size 2
+ * spinSem10: spin lock semaphore, semaphore size 10
+ * spinSem120: spin lock semaphore, semaphore size 120
+ * spinSemEBO1: spin lock semaphore with exponential backoff, semaphore size 1
+ * spinSemEBO2: spin lock semaphore with exponential backoff, semaphore size 2
+ * spinSemEBO10: spin lock semaphore with exponential backoff, semaphore size 10
+ * spinSemEBO120: spin lock semaphore with exponential backoff, semaphore size 120
// local synchronization versions
- - spinMutexUniq - local spin lock mutex
- - spinMutexEBOUniq - local spin lock mutex with exponential backoff
- - sleepMutexUniq - local decentralized ticket lock
- - faMutexUniq - local centralized ticket lock
- - spinSemUniq1 - local spin lock semaphore, semaphore size 1
- - spinSemUniq2 - local spin lock semaphore, semaphore size 2
- - spinSemUniq10 - local spin lock semaphore, semaphore size 10
- - spinSemUniq120 - local spin lock semaphore, semaphore size 120
- - spinSemEBOUniq1 - local spin lock semaphore with exponential backoff, semaphore size 1
- - spinSemEBOUniq2 - local spin lock semaphore with exponential backoff, semaphore size 2
- - spinSemEBOUniq10 - local spin lock semaphore with exponential backoff, semaphore size 10
- - spinSemEBOUniq120 - local spin lock semaphore with exponential backoff, semaphore size 120
+ * spinMutexUniq: local spin lock mutex
+ * spinMutexEBOUniq: local spin lock mutex with exponential backoff
+ * sleepMutexUniq: local decentralized ticket lock
+ * faMutexUniq: local centralized ticket lock
+ * spinSemUniq1: local spin lock semaphore, semaphore size 1
+ * spinSemUniq2: local spin lock semaphore, semaphore size 2
+ * spinSemUniq10: local spin lock semaphore, semaphore size 10
+ * spinSemUniq120: local spin lock semaphore, semaphore size 120
+ * spinSemEBOUniq1: local spin lock semaphore with exponential backoff, semaphore size 1
+ * spinSemEBOUniq2: local spin lock semaphore with exponential backoff, semaphore size 2
+ * spinSemEBOUniq10: local spin lock semaphore with exponential backoff, semaphore size 10
+ * spinSemEBOUniq120: local spin lock semaphore with exponential backoff, semaphore size 120
-<numLdSt> is a positive integer representing how many loads and stores each thread will perform. For the mutexes and semaphores, these accesses are all performed in the critical section. For the barriers, these accesses use barriers to ensure that multiple threads are not accessing the same data.
+<numLdSt> is a positive integer representing how many loads and stores each thread will perform. For the mutexes and semaphores, these accesses are all performed in the critical section. For the barriers, these accesses use barriers to ensure that multiple threads are not accessing the same data.
-<numTBs> is a positive integer representing the number of thread blocks (TBs) to execute. For many of the microbenchmarks (especially the barriers), this number needs to be divisible by the number of SMs on the GPU.
+<numTBs> is a positive integer representing the number of thread blocks (TBs) to execute. For many of the microbenchmarks (especially the barriers), this number needs to be divisible by the number of SMs on the GPU.
-<numCSIters> is a positive integer representing the number of iterations of the critical section.
-
-IISWC '17 VERSION
------------------
-
-The version used in our IISWC '17 paper assumes a unified address space between the CPU and GPU. Thus, it does not require any copies. Moreover, this version is based on CUDA SDK 3.1 and HIP version 1.6, as this is the last version of CUDA that is fully supported by GPGPU-Sim and gem5, respectively, as of the release. Later versions of CUDA and HIP allow additional C++ features, which may simplify the code or allow other optimizations. Finally, this version is designed to run in the DeNovo ecosystem, which simulates a unified address space with multiple CPU cores and GPU CUs using a combination of Simics, GEMS, Garnet, and GPGPU-Sim. In this ecosystem, we assume a SC-for-DRF style memory consistency model. SC-for-DRF's ordering requirements are enforced by the epilogues and atomic operations. We assume that the epilogues will self-invalidate all valid data in the local (L1) caches and flush per-CU/core store buffers to write through or obtain ownership for dirty data.
-
-Similarly, to enforce the appropriate ordering requirements, we assume that the CUDA and HIP atomic operations have specific semantics:
-
-Atomic | Reprogrammed? | Load Acquire | Store Release | Unpaired |
-atomicAdd | | | | X (LD, ST) |
-atomicSub | | | | X (LD, ST) |
-atomicExch | X | | X (ST) | |
-atomicMin | | | | X (LD, ST) |
-atomicMax | | | | X (LD, ST) |
-atomicInc | | | X (ST) | X (LD) |
-atomicDec | | | X (ST) | X (LD) |
-atomicCAS | | X (LD) | | X (ST) |
-atomicAnd | X | | | X (LD, ST) |
-atomicOr | X | | | X (LD, ST) |
-atomicXor | X | X (LD) | | |
-
-If your ecosystem does not make the same assumptions, then you will need to add the appropriate fences (e.g., CUDA's __threadfence() and __threadfence_block()) to ensure the proper ordering of requests in the memory system. In the case of the HIP implementation, you may be able to use some OpenCL atomics with the desired orderings, but we left it as is to ensure portability and correctness with future versions of HIP that may not support this feature.
-
-Reprogrammed Atomics:
-
-In addition to the above assumptions about semantics for a given atomic, we have also reprogrammed some of the CUDA atomics to provide certain functionality we needed that CUDA doesn't provide:
-
-- atomicAnd() was reprogrammed to have the same functionality as an atomicInc() but without store release semantics (i.e., atomicInc has store release semantics, atomicAnd does not). We chose atomicAnd() for this because it was not used in any of our applications. This change was necessary because atomicInc() sometimes needs store release semantics.
-- atomicXor() was reprogrammed to do an atomic load (instead of an atomic RMW).
-- atomicOr() was reprogrammed to do an (unpaired) atomic store (instead of an atomic RMW). We chose atomicOr for the symmetry with atomicXor and because no applications used it.
-- atomicExch() was not reprogrammed in the simulator, but we have re-purposed it assuming that the value returned by the atomicExch() is never returned or used in the program. This allows us to treat atomicExch() as if it were an atomic store. Thus, the programmer should consider an atomicExch() to be an atomic store. All of the applications we have encountered thus far already did this. In the simulator, we account for the read on the timing and functional sides.
-
-Instruction-Centric vs. Data-Centric:
-
-Common programming languages like C++ and OpenCL, which use a data-centric approach. These languages identify atomic accesses by “tagging” a variable with the atomic qualifier. These languages use an instruction-centric method for identifying which atomic accesses can/should use relaxed atomics instead of SC atomics; the accesses that can be relaxed have “memory_order_relaxed” appended to their accesses. Since CUDA does not provide support for the same framework as C++ and OpenCL, we had to make a design decision about how to identify atomic accesses and how to identify which of those atomic accesses can use relaxed atomics vs. SC atomics. We chose to use an instruction-centric method for identifying atomic vs. non-atomic accesses. In this method, we designate certain CUDA atomic instructions as being load acquires, store releases, or unpaired (as denoted above). Moreover, note that CUDA does not have direct support for atomic loads or stores. HIP does support these, but only with OpenCL commands.
-
-CUDA UVM VERSION
-----------------
-
-The CUDA UVM version is based on CUDA SDK 6.0, and uses CUDA's unified virtual memory to avoid making explicit copies of some of the arrays and structures. Unlike the IISWC '17 version, this version does not make any assumptions about ordering atomics provide. Nor does it require epilogues. Instead, it adds the appropriate CUDA fence commands around atomic accesses to ensure the SC-for-DRF ordering is provided. This version has been tested on a Pascal P100 GPU, but has not been tested as rigorously as the IISWC '17 version.
+<numCSIters> is a positive integer representing the number of iterations of the critical section.
HIP UVM VERSION
----------------
-The HIP UVM version is based on HIP 1.6, and uses HIP's unified virtual memory to avoid making explicit copies of some of the arrays and structures. Unlike the IISWC '17 version, this version does not make any assumptions about ordering atomics provide. Nor does it require epilogues. Instead, it adds the appropriate HIP fence commands around atomic accesses to ensure the SC-for-DRF ordering is provided. This version has been tested on a Vega 56 GPU, but has not been tested as rigorously as the IISWC '17 version.
+The HIP UVM version is based on HIP 4.0, and uses HIP's unified virtual memory to avoid making explicit copies of some of the arrays and structures. Unlike the IISWC '17 version, this version does not make any assumptions about ordering atomics provide. Nor does it require epilogues. Instead, it adds the appropriate HIP fence commands around atomic accesses to ensure the SC-for-DRF ordering is provided. This version has been tested on a Vega 20 GPU, but has not been tested as rigorously as the IISWC '17 version.
CITATION
--------
diff --git a/src/gpu/lulesh/Makefile b/src/gpu/lulesh/Makefile
index 64bdc4f..09bd0fb 100755
--- a/src/gpu/lulesh/Makefile
+++ b/src/gpu/lulesh/Makefile
@@ -1,7 +1,8 @@
-BIN_DIR?= ./bin
+BIN_DIR ?= ./bin
+HIP_PATH ?= /opt/rocm/hip
all: $(BIN_DIR)
- hipcc src/lulesh.hip.cc -o $(BIN_DIR)/lulesh --amdgpu-target=gfx801
+ $(HIP_PATH)/bin/hipcc src/lulesh.hip.cc -o $(BIN_DIR)/lulesh --amdgpu-target=gfx801,gfx803
$(BIN_DIR):
mkdir -p $(BIN_DIR)
diff --git a/src/gpu/lulesh/src/lulesh.hip.cc b/src/gpu/lulesh/src/lulesh.hip.cc
index 2026f6c..726f845 100644
--- a/src/gpu/lulesh/src/lulesh.hip.cc
+++ b/src/gpu/lulesh/src/lulesh.hip.cc
@@ -804,7 +804,7 @@
template<typename T>
void freshenGPU(std::vector<T>&cpu,T **gpu,int& stale) {
if (stale!=GPU_STALE) return;
- if (!(*gpu)) {HIP( hipMalloc(gpu,sizeof(T)*cpu.size()) );}
+ if (!(*gpu)) {HIP( hipHostMalloc(gpu,sizeof(T)*cpu.size()) );}
HIP( hipMemcpy(*gpu,&cpu[0],sizeof(T)*cpu.size(),hipMemcpyHostToDevice) );
stale=ALL_FRESH;
}
@@ -1458,9 +1458,9 @@
{
Real_t *fx_elem,*fy_elem,*fz_elem;
- HIP( hipMalloc(&fx_elem,numElem*8*sizeof(Real_t)) );
- HIP( hipMalloc(&fy_elem,numElem*8*sizeof(Real_t)) );
- HIP( hipMalloc(&fz_elem,numElem*8*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&fx_elem,numElem*8*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&fy_elem,numElem*8*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&fz_elem,numElem*8*sizeof(Real_t)) );
dim3 dimBlock=dim3(BLOCKSIZE,1,1);
dim3 dimGrid=dim3(PAD_DIV(numElem,dimBlock.x),1,1);
@@ -2425,9 +2425,9 @@
Index_t numElem = mesh.numElem();
Real_t *fx_elem,*fy_elem,*fz_elem;
- HIP( hipMalloc(&fx_elem,numElem*8*sizeof(Real_t)) );
- HIP( hipMalloc(&fy_elem,numElem*8*sizeof(Real_t)) );
- HIP( hipMalloc(&fz_elem,numElem*8*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&fx_elem,numElem*8*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&fy_elem,numElem*8*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&fz_elem,numElem*8*sizeof(Real_t)) );
dim3 dimBlock=dim3(256,1,1);
dim3 dimGrid=dim3(PAD_DIV(numElem*8,dimBlock.x),1,1);
@@ -2521,12 +2521,12 @@
Real_t *dvdx,*dvdy,*dvdz;
Real_t *x8n,*y8n,*z8n;
- HIP( hipMalloc(&dvdx,sizeof(Real_t)*numElem8) );
- HIP( hipMalloc(&dvdy,sizeof(Real_t)*numElem8) );
- HIP( hipMalloc(&dvdz,sizeof(Real_t)*numElem8) );
- HIP( hipMalloc(&x8n,sizeof(Real_t)*numElem8) );
- HIP( hipMalloc(&y8n,sizeof(Real_t)*numElem8) );
- HIP( hipMalloc(&z8n,sizeof(Real_t)*numElem8) );
+ HIP( hipHostMalloc(&dvdx,sizeof(Real_t)*numElem8) );
+ HIP( hipHostMalloc(&dvdy,sizeof(Real_t)*numElem8) );
+ HIP( hipHostMalloc(&dvdz,sizeof(Real_t)*numElem8) );
+ HIP( hipHostMalloc(&x8n,sizeof(Real_t)*numElem8) );
+ HIP( hipHostMalloc(&y8n,sizeof(Real_t)*numElem8) );
+ HIP( hipHostMalloc(&z8n,sizeof(Real_t)*numElem8) );
dim3 dimBlock=dim3(256,1,1);
dim3 dimGrid=dim3(PAD_DIV(numElem*8,dimBlock.x),1,1);
@@ -2641,10 +2641,10 @@
Real_t *sigxx, *sigyy, *sigzz, *determ;
int badvol;
- HIP( hipMalloc(&sigxx,numElem*sizeof(Real_t)) );
- HIP( hipMalloc(&sigyy,numElem*sizeof(Real_t)) );
- HIP( hipMalloc(&sigzz,numElem*sizeof(Real_t)) );
- HIP( hipMalloc(&determ,numElem*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&sigxx,numElem*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&sigyy,numElem*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&sigzz,numElem*sizeof(Real_t)) );
+ HIP( hipHostMalloc(&determ,numElem*sizeof(Real_t)) );
/* Sum contributions to total stress tensor */
InitStressTermsForElems(numElem, sigxx, sigyy, sigzz, 0);
@@ -4463,7 +4463,7 @@
dim3 dimBlock=dim3(BLOCKSIZE,1,1);
dim3 dimGrid=dim3(PAD_DIV(length,dimBlock.x),1,1);
- HIP( hipMalloc(&pHalfStep,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&pHalfStep,sizeof(Real_t)*length) );
hipLaunchKernelGGL((CalcEnergyForElemsPart1_kernel), dim3(dimGrid), dim3(dimBlock), 0, 0, length,emin,e_old,delvc,p_old,q_old,work,e_new);
HIP_DEBUGSYNC;
@@ -4750,20 +4750,20 @@
Real_t *compression,*compHalfStep;
Real_t *qq,*ql,*work,*p_new,*e_new,*q_new,*bvc,*pbvc;
- HIP( hipMalloc(&e_old,sizeof(Real_t)*length) );
- HIP( hipMalloc(&delvc,sizeof(Real_t)*length) );
- HIP( hipMalloc(&p_old,sizeof(Real_t)*length) );
- HIP( hipMalloc(&q_old,sizeof(Real_t)*length) );
- HIP( hipMalloc(&compression,sizeof(Real_t)*length) );
- HIP( hipMalloc(&compHalfStep,sizeof(Real_t)*length) );
- HIP( hipMalloc(&qq,sizeof(Real_t)*length) );
- HIP( hipMalloc(&ql,sizeof(Real_t)*length) );
- HIP( hipMalloc(&work,sizeof(Real_t)*length) );
- HIP( hipMalloc(&p_new,sizeof(Real_t)*length) );
- HIP( hipMalloc(&e_new,sizeof(Real_t)*length) );
- HIP( hipMalloc(&q_new,sizeof(Real_t)*length) );
- HIP( hipMalloc(&bvc,sizeof(Real_t)*length) );
- HIP( hipMalloc(&pbvc,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&e_old,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&delvc,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&p_old,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&q_old,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&compression,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&compHalfStep,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&qq,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&ql,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&work,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&p_new,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&e_new,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&q_new,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&bvc,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&pbvc,sizeof(Real_t)*length) );
dim3 dimBlock=dim3(BLOCKSIZE,1,1);
dim3 dimGrid=dim3(PAD_DIV(length,dimBlock.x),1,1);
@@ -4967,7 +4967,7 @@
Real_t eosvmax = mesh.eosvmax() ;
Real_t *vnewc;
- HIP( hipMalloc(&vnewc,sizeof(Real_t)*length) );
+ HIP( hipHostMalloc(&vnewc,sizeof(Real_t)*length) );
dim3 dimBlock=dim3(BLOCKSIZE,1,1);
dim3 dimGrid=dim3(PAD_DIV(length,dimBlock.x),1,1);
@@ -5197,7 +5197,7 @@
dim3 dimGrid=dim3(PAD_DIV(length,dimBlock.x),1,1);
Real_t *dev_mindtcourant;
- HIP( hipMalloc(&dev_mindtcourant,sizeof(Real_t)*dimGrid.x) );
+ HIP( hipHostMalloc(&dev_mindtcourant,sizeof(Real_t)*dimGrid.x) );
hipLaunchKernelGGL((CalcCourantConstraintForElems_kernel), dim3(dimGrid), dim3(dimBlock), 0, 0, length,qqc2,
meshGPU.m_matElemlist,meshGPU.m_ss,meshGPU.m_vdov,meshGPU.m_arealg,
@@ -5316,7 +5316,7 @@
dim3 dimGrid=dim3(PAD_DIV(length,dimBlock.x),1,1);
Real_t *dev_mindthydro;
- HIP( hipMalloc(&dev_mindthydro,sizeof(Real_t)*dimGrid.x) );
+ HIP( hipHostMalloc(&dev_mindthydro,sizeof(Real_t)*dimGrid.x) );
hipLaunchKernelGGL((CalcHydroConstraintForElems_kernel), dim3(dimGrid), dim3(dimBlock), 0, 0, length,dvovmax,
meshGPU.m_matElemlist,meshGPU.m_vdov,
diff --git a/src/gpu/lulesh/x.asc.golden b/src/gpu/lulesh/x.asc.golden
new file mode 100644
index 0000000..8a6cfa4
--- /dev/null
+++ b/src/gpu/lulesh/x.asc.golden
@@ -0,0 +1,91125 @@
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diff --git a/src/gpu/pannotia/README.md b/src/gpu/pannotia/README.md
new file mode 100644
index 0000000..dca4bed
--- /dev/null
+++ b/src/gpu/pannotia/README.md
@@ -0,0 +1,12 @@
+---
+title: Pannotia Tests
+tags:
+ - x86
+ - amdgpu
+layout: default
+permalink: resources/pannotia/
+shortdoc: >
+ Resources to build a disk image for each of the GCN3 Pannotia workloads.
+---
+
+This folder and its subfolders contain each of the 9 Pannotia benchmarks (there are 6 folders because Color, and PageRank, SSSP each have 2 versions). All of these benchmarks have been ported from the prior CUDA and OpenCL variants to HIP, and validated on a Vega-class AMD GPU. See each application's README for details on how to compile and run them in gem5 using the GCN3 GPU model.
diff --git a/src/gpu/pannotia/bc/BC.cpp b/src/gpu/pannotia/bc/BC.cpp
new file mode 100644
index 0000000..df676d9
--- /dev/null
+++ b/src/gpu/pannotia/bc/BC.cpp
@@ -0,0 +1,322 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+//#include <sys/time.h>
+#include <algorithm>
+#include "BC.h"
+#include "../graph_parser/util.h"
+#include "kernel.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+#include <gem5/m5ops.h>
+#endif
+
+#ifdef GEM5_FUSION
+#define MAX_ITERS 150
+#else
+#include <stdint.h>
+#define MAX_ITERS INT32_MAX
+#endif
+
+void print_vector(int *vector, int num);
+void print_vectorf(float *vector, int num);
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+
+ int num_nodes;
+ int num_edges;
+ bool directed = 1;
+
+ hipError_t err;
+
+ if (argc == 2) {
+ tmpchar = argv[1]; //graph inputfile
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ // Parse graph and store it in a CSR format
+ csr_array *csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
+
+ // Allocate the bc host array
+ float *bc_h = (float *)malloc(num_nodes * sizeof(float));
+ if (!bc_h) fprintf(stderr, "malloc failed bc_h\n");
+
+ // Create device-side buffers
+ float *bc_d, *sigma_d, *rho_d;
+ int *dist_d, *stop_d;
+ int *row_d, *col_d, *row_trans_d, *col_trans_d;
+
+ // Create betweenness centrality buffers
+ err = hipMalloc(&bc_d, num_nodes * sizeof(float));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc bc_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&dist_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc dist_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&sigma_d, num_nodes * sizeof(float));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc sigma_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&rho_d, num_nodes * sizeof(float));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc rho_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Create termination variable buffer
+ err = hipMalloc(&stop_d, sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc stop_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Create graph buffers
+ err = hipMalloc(&row_d, (num_nodes + 1) * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc row_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&row_trans_d, (num_nodes + 1) * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc row_trans_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_trans_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_trans_d %s\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ //double timer1, timer2;
+ //double timer3, timer4;
+
+ //timer1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ // Copy data to device-side buffers
+ err = hipMemcpy(row_d, csr->row_array, (num_nodes + 1) * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Copy data to device-side buffers
+ err = hipMemcpy(row_trans_d, csr->row_array_t, (num_nodes + 1) * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy row_trans_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_trans_d, csr->col_array_t, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_trans_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ //timer3 = gettime();
+
+ // Set up kernel dimensions
+ int local_worksize = 128;
+ dim3 threads(local_worksize, 1, 1);
+ int num_blocks = (num_nodes + local_worksize - 1) / local_worksize;
+ dim3 grid(num_blocks, 1, 1);
+
+ // Initialization
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(clean_bc), dim3(grid), dim3(threads ), 0, 0, bc_d, num_nodes);
+
+ // Main computation loop
+ for (int i = 0; i < num_nodes && i < MAX_ITERS; i++) {
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(clean_1d_array), dim3(grid), dim3(threads ), 0, 0, i, dist_d, sigma_d, rho_d,
+ num_nodes);
+
+ // Depth of the traversal
+ int dist = 0;
+ // Termination variable
+ int stop = 1;
+
+ // Traverse the graph from the source node i
+ do {
+ stop = 0;
+
+ // Copy the termination variable to the device
+ hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
+
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(bfs_kernel), dim3(grid), dim3(threads ), 0, 0, row_d, col_d, dist_d, rho_d, stop_d,
+ num_nodes, num_edges, dist);
+
+ // Copy back the termination variable from the device
+ hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
+
+ // Another level
+ dist++;
+
+ } while (stop);
+
+ hipDeviceSynchronize();
+
+ // Traverse back from the deepest part of the tree
+ while (dist) {
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(backtrack_kernel), dim3(grid), dim3(threads ), 0, 0, row_trans_d, col_trans_d,
+ dist_d, rho_d, sigma_d,
+ num_nodes, num_edges, dist, i,
+ bc_d);
+
+ // Back one level
+ dist--;
+ }
+ hipDeviceSynchronize();
+ fprintf(stdout, "Completed iteration %d\n", i);
+ }
+ hipDeviceSynchronize();
+ //timer4 = gettime();
+
+ // Copy back the results for the bc array
+ err = hipMemcpy(bc_h, bc_d, num_nodes * sizeof(float), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read buffer bc_d (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+ //timer2 = gettime();
+
+ //printf("kernel + memcopy time = %lf ms\n", (timer4 - timer3) * 1000);
+ //printf("kernel execution time = %lf ms\n", (timer2 - timer1) * 1000);
+
+#if 1
+ //dump the results to the file
+ print_vectorf(bc_h, num_nodes);
+#endif
+
+ // Clean up the host-side buffers
+ free(bc_h);
+ free(csr->row_array);
+ free(csr->col_array);
+ free(csr->data_array);
+ free(csr->row_array_t);
+ free(csr->col_array_t);
+ free(csr->data_array_t);
+ free(csr);
+
+ // Clean up the device-side buffers
+ hipFree(bc_d);
+ hipFree(dist_d);
+ hipFree(sigma_d);
+ hipFree(rho_d);
+ hipFree(stop_d);
+ hipFree(row_d);
+ hipFree(col_d);
+ hipFree(row_trans_d);
+ hipFree(col_trans_d);
+
+ return 0;
+}
+
+void print_vector(int *vector, int num)
+{
+ for (int i = 0; i < num; i++)
+ printf("%d: %d \n", i + 1, vector[i]);
+ printf("\n");
+}
+
+void print_vectorf(float *vector, int num)
+{
+
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++) {
+ fprintf(fp, "%f\n", vector[i]);
+ }
+
+ fclose(fp);
+
+}
diff --git a/src/gpu/pannotia/bc/BC.h b/src/gpu/pannotia/bc/BC.h
new file mode 100644
index 0000000..0abdb12
--- /dev/null
+++ b/src/gpu/pannotia/bc/BC.h
@@ -0,0 +1,230 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+typedef struct csr_array_t {
+
+ int *row_array;
+ int *col_array;
+ int *data_array;
+
+ int *row_array_t;
+ int *col_array_t;
+ int *data_array_t;
+
+} csr_array;
+
+
+typedef struct cooedgetuple {
+ int row;
+ int col;
+ int val;
+} CooTuple;
+
+bool compare(
+ CooTuple elem1,
+ CooTuple elem2)
+{
+ if (elem1.row < elem2.row)
+ return true;
+ return false;
+}
+
+void transform(CooTuple *tuple_array, int num_edges, int *row_array, int *col_array, int *data_array)
+{
+
+ int row_cnt = 0;
+ int prev = -1;
+ int idx;
+
+ for (idx = 0; idx < num_edges; idx++) {
+ int curr = tuple_array[idx].row;
+ if (curr != prev) {
+ row_array[row_cnt++] = idx;
+ prev = curr;
+ }
+
+ col_array[idx] = tuple_array[idx].col;
+ data_array[idx] = tuple_array[idx].val;
+
+ }
+ row_array[row_cnt] = idx;
+}
+
+csr_array * parseCOO(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed)
+{
+ int cnt = 0;
+ int cnt1 = 0;
+ unsigned int lineno = 0;
+ char sp[2], a, p;
+ char * line = (char *)malloc(8192 * sizeof(char));
+ int num_nodes = 0, num_edges = 0;
+
+ FILE *fptr;
+ CooTuple *tuple_array = NULL;
+ CooTuple *tuple_array_t = NULL;
+
+ fptr = fopen(tmpchar, "r");
+ if (!fptr) {
+ fprintf(stderr, "Error when opennning file: %s\n", tmpchar);
+ perror("ERROR: ");
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+
+ while (fgets(line, 8192, fptr)) {
+ int head, tail, weight;
+ switch (line[0]) {
+ case 'c':
+ break;
+ case 'p':
+ sscanf(line, "%c %s %d %d", &p, sp, p_num_nodes, p_num_edges);
+
+ if (!directed) {
+ *p_num_edges = *p_num_edges * 2;
+ printf("This is an undirected graph\n");
+ } else {
+ printf("This is a directed graph\n");
+ }
+
+ num_nodes = *p_num_nodes;
+ num_edges = *p_num_edges;
+
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", num_nodes, num_edges);
+
+ tuple_array = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ if (!tuple_array) printf("malloc failed\n");
+ tuple_array_t = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ if (!tuple_array_t) printf("malloc failed\n");
+
+ break;
+
+ case 'a':
+ sscanf(line, "%c %d %d %d", &a, &head, &tail, &weight);
+
+ if (tail == head) printf("reporting self loop\n");
+
+ CooTuple temp, temp1;
+
+ temp.row = head - 1;
+ temp.col = tail - 1;
+ temp.val = weight;
+
+ temp1.row = tail - 1;
+ temp1.col = head - 1;
+ temp1.val = weight;
+
+ tuple_array[cnt++] = temp;
+ tuple_array_t[cnt1++] = temp1;
+
+ if (!directed) {
+
+ temp.row = tail - 1;
+ temp.col = head - 1;
+ temp.val = weight;
+
+ temp1.row = head - 1;
+ temp1.col = tail - 1;
+ temp1.val = weight;
+
+ tuple_array[cnt++] = temp;
+ tuple_array_t[cnt1++] = temp1;
+
+ }
+
+ break;
+ default:
+ fprintf(stderr, "exiting loop\n");
+ break;
+ }
+ lineno++;
+ }
+
+ std::stable_sort(tuple_array, tuple_array + num_edges, compare);
+ std::stable_sort(tuple_array_t, tuple_array_t + num_edges, compare);
+
+ int *row_array = (int *)malloc((num_nodes + 1) * sizeof(int));
+ int *col_array = (int *)malloc(num_edges * sizeof(int));
+ int *data_array = (int *)malloc(num_edges * sizeof(int));
+
+ int *row_array_t = (int *)malloc((num_nodes + 1) * sizeof(int));
+ int *col_array_t = (int *)malloc(num_edges * sizeof(int));
+ int *data_array_t = (int *)malloc(num_edges * sizeof(int));
+
+ transform(tuple_array, num_edges, row_array, col_array, data_array);
+ transform(tuple_array_t, num_edges, row_array_t, col_array_t, data_array_t);
+
+ fclose(fptr);
+ free(tuple_array);
+ free(tuple_array_t);
+
+ csr_array *csr = (csr_array *)malloc(sizeof(csr_array));
+
+ csr -> row_array = row_array;
+ csr -> col_array = col_array;
+ csr -> data_array = data_array;
+
+ csr -> row_array_t = row_array_t;
+ csr -> col_array_t = col_array_t;
+ csr -> data_array_t = data_array_t;
+
+ free(line);
+
+ return csr;
+}
+
diff --git a/src/gpu/pannotia/bc/Makefile b/src/gpu/pannotia/bc/Makefile
new file mode 100644
index 0000000..6158bac
--- /dev/null
+++ b/src/gpu/pannotia/bc/Makefile
@@ -0,0 +1,11 @@
+default:
+ make -f Makefile.default
+
+clean:
+ make -f Makefile.default clean
+
+gem5-fusion:
+ make -f Makefile.gem5-fusion
+
+clean-gem5-fusion:
+ make -f Makefile.gem5-fusion clean
diff --git a/src/gpu/pannotia/bc/Makefile.default b/src/gpu/pannotia/bc/Makefile.default
new file mode 100644
index 0000000..e1053c0
--- /dev/null
+++ b/src/gpu/pannotia/bc/Makefile.default
@@ -0,0 +1,24 @@
+CPPSRC = ../graph_parser/util.cpp
+CPPSRC = BC.cpp
+EXECUTABLE = bc_hip
+# BC has a compilation error in host code with ROCm 4.0, so O2 and O3 do not
+# pass even on real GPUs
+OPTS = -O1
+
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): $(CPPSRC) ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) $(OPTS) --amdgpu-target=gfx801,gfx803,gfx906 $(CXXFLAGS) ../graph_parser/util.cpp $(CPPSRC) -o $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: bc clean
diff --git a/src/gpu/pannotia/bc/Makefile.gem5-fusion b/src/gpu/pannotia/bc/Makefile.gem5-fusion
new file mode 100644
index 0000000..bd1bf14
--- /dev/null
+++ b/src/gpu/pannotia/bc/Makefile.gem5-fusion
@@ -0,0 +1,28 @@
+CPPSRC = BC.cpp
+EXECUTABLE = bc.gem5
+# BC has a compilation error in host code with ROCm 4.0, so O2 and O3 do not
+# pass even on real GPUs
+OPTS = -O1
+
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+# these are needed for m5ops
+GEM5_PATH ?= /path/to/gem5
+CFLAGS += -I$(GEM5_PATH)/include -I../graph_parser
+LDFLAGS += -L$(GEM5_PATH)/util/m5/build/x86/out -lm5
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): $(CPPSRC) ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) $(OPTS) --amdgpu-target=gfx801,gfx803 $(CXXFLAGS) ../graph_parser/util.cpp $(CPPSRC) -DGEM5_FUSION -o $(BIN_DIR)/$(EXECUTABLE) $(CFLAGS) $(LDFLAGS)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: bc clean
diff --git a/src/gpu/pannotia/bc/README.md b/src/gpu/pannotia/bc/README.md
new file mode 100644
index 0000000..60499b3
--- /dev/null
+++ b/src/gpu/pannotia/bc/README.md
@@ -0,0 +1,49 @@
+---
+title: Pannotia BC Test
+tags:
+ - x86
+ - amdgpu
+layout: default
+permalink: resources/pannotia/bc
+shortdoc: >
+ Resources to build a disk image with the GCN3 Pannotia BC workload.
+---
+
+Betweenness Centrality (BC) is a graph analytics application that is part of the Pannotia benchmark suite. It is used to calculate betweenness centrality scores for all the vertices in a graph. The provided version is for use with the gpu-compute model of gem5. Thus, it has been ported from the prior CUDA and OpenCL variants to HIP, and validated on a Vega-class AMD GPU.
+
+Compiling BC, compiling the GCN3_X86/Vega_X86 versions of gem5, and running BC on gem5 is dependent on the gcn-gpu docker image, `util/dockerfiles/gcn-gpu/Dockerfile` on the [gem5 stable branch](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable).
+
+## Compilation and Running
+
+To compile BC:
+
+```
+cd src/gpu/pannotia/bc
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu make gem5-fusion
+```
+
+If you use the Makefile.default file instead, the Makefile will generate code designed to run on the real GPU instead. Moreover, note that Makefile.gem5-fusion requires you to set the GEM5_ROOT variable (either on the command line or by modifying the Makefile), because the Pannotia applications have been updated to use [m5ops](https://www.gem5.org/documentation/general_docs/m5ops/). By default, the Makefile builds for gfx801 and gfx803, and is placed in the src/gpu/pannotia/bc/bin folder.
+
+## Compiling GCN3_X86/gem5.opt
+
+BC is a GPU application, which requires that gem5 is built with the GCN3_X86 (or Vega_X86, although this has been less heavily tested) architecture. The test is run with the GCN3_X86 gem5 variant, compiled using the gcn-gpu docker image:
+
+```
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest scons build/GCN3_X86/gem5.opt -j <num cores>
+```
+
+## Running BC on GCN3_X86/gem5.opt
+
+# Assuming gem5 and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/bc/bin -c bc.gem5 --options="1k_128k.gr"
+```
+
+Note that the datasets from the original Pannotia suite have been uploaded to: <http://dist.gem5.org/dist/develop/datasets/pannotia>. We recommend you start with the 1k_128k.gr input (<http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr>), as this is the smallest input designed to run with BC.
+
+## Pre-built binary
+
+A pre-built binary will be added soon.
diff --git a/src/gpu/pannotia/bc/kernel.h b/src/gpu/pannotia/bc/kernel.h
new file mode 100644
index 0000000..442f007
--- /dev/null
+++ b/src/gpu/pannotia/bc/kernel.h
@@ -0,0 +1,241 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#ifndef KERNEL_H_
+#define KERNEL_H_
+
+#include "hip/hip_runtime.h"
+
+/**
+ * @brief Breadth-first traversal
+ * @param row CSR pointer array
+ * @param col CSR column array
+ * @param d Distance array
+ * @param rho Rho array
+ * @param p Dependency array
+ * @param cont Termination variable
+ * @param num_nodes Termination variable
+ * @param num_edges Termination variable
+ * @param dist Current traversal layer
+ */
+
+__global__ void
+bfs_kernel(int *row, int *col, int *d, float *rho, int *cont,
+ const int num_nodes, const int num_edges, const int dist)
+{
+ int tid = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
+
+ //navigate the current layer
+ if (tid < num_nodes && d[tid] == dist) {
+
+ //get the starting and ending pointers
+ //of the neighbor list
+
+ int start = row[tid];
+ int end;
+ if (tid + 1 < num_nodes)
+ end = row[tid + 1];
+ else
+ end = num_edges;
+
+ //navigate through the neighbor list
+ for (int edge = start; edge < end; edge++) {
+ int w = col[edge];
+ if (d[w] < 0) {
+ *cont = 1;
+ //traverse another layer
+ d[w] = dist + 1;
+ }
+ //transfer the rho value to the neighbor
+ if (d[w] == (dist + 1)) {
+ atomicAdd(&rho[w], rho[tid]);
+ }
+ }
+ }
+}
+
+/**
+ * @brief Back traversal
+ * @param row CSR pointer array
+ * @param col CSR column array
+ * @param d Distance array
+ * @param rho Rho array
+ * @param sigma Sigma array
+ * @param p Dependency array
+ * @param cont Termination variable
+ * @param num_nodes Termination variable
+ * @param num_edges Termination variable
+ * @param dist Current traversal layer
+ * @param s Source vertex
+ * @param bc Betweeness Centrality array
+ */
+
+__global__ void
+backtrack_kernel(int *row, int *col, int *d, float *rho, float *sigma,
+ const int num_nodes, const int num_edges, const int dist,
+ const int s, float* bc)
+{
+ int tid = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
+
+ // Navigate the current layer
+ if (tid < num_nodes && d[tid] == dist - 1) {
+
+ int start = row[tid];
+ int end;
+ if (tid + 1 < num_nodes)
+ end = row[tid + 1];
+ else
+ end = num_edges;
+
+ // Get the starting and ending pointers
+ // of the neighbor list in the reverse graph
+ for (int edge = start; edge < end; edge++) {
+ int w = col[edge];
+ // Update the sigma value traversing back
+ if (d[w] == dist - 2)
+ atomicAdd(&sigma[w], rho[w] / rho[tid] * (1 + sigma[tid]));
+ }
+
+ // Update the BC value
+ if (tid != s)
+ bc[tid] = bc[tid] + sigma[tid];
+ }
+
+}
+
+/**
+ * @brief back_sum_kernel (not used)
+ * @param s Source vertex
+ * @param dist Current traversal layer
+ * @param d Distance array
+ * @param sigma Sigma array
+ * @param bc Betweeness Centrality array
+ * @param num_nodes Termination variable
+ * @param num_edges Termination variable
+ */
+__global__ void
+back_sum_kernel(const int s, const int dist, int *d, float *sigma, float *bc,
+ const int num_nodes)
+{
+ int tid = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ // If it is not the source
+ if (s != tid && d[tid] == dist - 1) {
+ bc[tid] = bc[tid] + sigma[tid];
+ }
+ }
+}
+
+/**
+ * @brief array set 1D
+ * @param s Source vertex
+ * @param dist_array Distance array
+ * @param sigma Sigma array
+ * @param rho Rho array
+ * @param num_nodes Termination variable
+ */
+__global__ void
+clean_1d_array(const int source, int *dist_array, float *sigma, float *rho,
+ const int num_nodes)
+{
+ int tid = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+
+ sigma[tid] = 0;
+
+ if (tid == source) {
+ // If source vertex rho = 1, dist = 0
+ rho[tid] = 1;
+ dist_array[tid] = 0;
+ } else {
+ // If other vertices rho = 0, dist = -1
+ rho[tid] = 0;
+ dist_array[tid] = -1;
+ }
+ }
+}
+
+/**
+ * @brief array set 2D
+ * @param p Dependency array
+ * @param num_nodes Number of vertices
+ */
+__global__ void clean_2d_array(int *p, const int num_nodes)
+{
+ int tid = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
+
+ if (tid < num_nodes * num_nodes)
+ p[tid] = 0;
+}
+
+/**
+ * @brief clean BC
+ * @param bc_d Betweeness Centrality array
+ * @param num_nodes Number of vertices
+ */
+__global__ void clean_bc(float *bc_d, const int num_nodes)
+{
+ int tid = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
+
+ if (tid < num_nodes)
+ bc_d[tid] = 0;
+}
+
+#endif // KERNEL_H_
diff --git a/src/gpu/pannotia/buildall.sh b/src/gpu/pannotia/buildall.sh
new file mode 100644
index 0000000..78192d2
--- /dev/null
+++ b/src/gpu/pannotia/buildall.sh
@@ -0,0 +1,72 @@
+#!/bin/bash
+
+extraparams=""
+buildparams=""
+if [ ! -z "$1" ]
+then
+ extraparams="$1"
+ buildparams="gem5-fusion"
+fi
+
+function savebin {
+ if [ "$2" == "" ]
+ then
+ backupbench="$1"
+ else
+ backupbench="gem5_fusion_$1"
+ fi
+ if [ -e "$backupbench" ]
+ then
+ echo "Saving bin $backupbench"
+ mv $backupbench $backupbench.bak
+ fi
+}
+
+function restorebin {
+ if [ "$2" == "" ]
+ then
+ backupbench="$1"
+ else
+ backupbench="gem5_fusion_$1"
+ fi
+ if [ -e "$backupbench.bak" ]
+ then
+ echo "Restoring bin $backupbench"
+ mv $backupbench.bak $backupbench
+ fi
+}
+
+for bench in bc color fw mis pagerank sssp
+do
+ echo $bench
+ pushd . >& /dev/null
+ cd $bench
+ make clean; make clean-gem5-fusion
+ make $buildparams $extraparams
+ if [ "$bench" == "color" ]
+ then
+ savebin "color_max" $buildparams
+ make clean; make clean-gem5-fusion
+ make $buildparams VARIANT=MAXMIN $extraparams
+ restorebin "color_max" $buildparams
+ elif [ "$bench" == "fw" ]
+ then
+ savebin "fw" $buildparams
+ make clean; make clean-gem5-fusion
+ make $buildparams VARIANT=BLOCK $extraparams
+ restorebin "fw" $buildparams
+ elif [ "$bench" == "pagerank" ]
+ then
+ savebin "pagerank" $buildparams
+ make clean; make clean-gem5-fusion
+ make $buildparams VARIANT=SPMV $extraparams
+ restorebin "pagerank" $buildparams
+ elif [ "$bench" == "sssp" ]
+ then
+ savebin "sssp" $buildparams
+ make clean; make clean-gem5-fusion
+ make $buildparams VARIANT=ELL $extraparams
+ restorebin "sssp" $buildparams
+ fi
+ popd >& /dev/null
+done
diff --git a/src/gpu/pannotia/cleanall.sh b/src/gpu/pannotia/cleanall.sh
new file mode 100644
index 0000000..256c4d3
--- /dev/null
+++ b/src/gpu/pannotia/cleanall.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+for bench in bc color fw mis pagerank sssp
+do
+ echo $bench
+ pushd . >& /dev/null
+ cd $bench
+ make clean; make clean-gem5-fusion
+ popd >& /dev/null
+done
diff --git a/src/gpu/pannotia/color/Makefile b/src/gpu/pannotia/color/Makefile
new file mode 100644
index 0000000..6158bac
--- /dev/null
+++ b/src/gpu/pannotia/color/Makefile
@@ -0,0 +1,11 @@
+default:
+ make -f Makefile.default
+
+clean:
+ make -f Makefile.default clean
+
+gem5-fusion:
+ make -f Makefile.gem5-fusion
+
+clean-gem5-fusion:
+ make -f Makefile.gem5-fusion clean
diff --git a/src/gpu/pannotia/color/Makefile.default b/src/gpu/pannotia/color/Makefile.default
new file mode 100644
index 0000000..cdd6192
--- /dev/null
+++ b/src/gpu/pannotia/color/Makefile.default
@@ -0,0 +1,27 @@
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+BASEEXE = color
+VARIANT ?= MAX
+ifeq ($(VARIANT),MAX)
+ EXECUTABLE = $(BASEEXE)_max
+ CPPFILES += coloring_max.cpp
+else ifeq ($(VARIANT),MAXMIN)
+ EXECUTABLE = $(BASEEXE)_maxmin
+ CPPFILES += coloring_maxmin.cpp
+endif
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): $(CPPFILES) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) -O3 --amdgpu-target=gfx801,gfx803,gfx906 $(CXXFLAGS) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(CPPFILES) -o $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: color clean
diff --git a/src/gpu/pannotia/color/Makefile.gem5-fusion b/src/gpu/pannotia/color/Makefile.gem5-fusion
new file mode 100644
index 0000000..f8f4fcc
--- /dev/null
+++ b/src/gpu/pannotia/color/Makefile.gem5-fusion
@@ -0,0 +1,32 @@
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+# these are needed for m5ops
+GEM5_PATH ?= /path/to/gem5
+CFLAGS += -I$(GEM5_PATH)/include -I/../graph_parser
+LDFLAGS += -L$(GEM5_PATH)/util/m5/build/x86/out -lm5
+
+BASEEXE = color
+VARIANT ?= MAX
+ifeq ($(VARIANT),MAX)
+ EXECUTABLE = $(BASEEXE)_max.gem5
+ CPPFILES += coloring_max.cpp
+else ifeq ($(VARIANT),MAXMIN)
+ EXECUTABLE = $(BASEEXE)_maxmin.gem5
+ CPPFILES += coloring_maxmin.cpp
+endif
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): $(CPPFILES) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) -O3 --amdgpu-target=gfx801,gfx803 $(CXXFLAGS) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(CPPFILES) -DGEM5_FUSION -o $(BIN_DIR)/$(EXECUTABLE) $(CFLAGS) $(LDFLAGS)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: color clean
diff --git a/src/gpu/pannotia/color/README.md b/src/gpu/pannotia/color/README.md
new file mode 100644
index 0000000..bc425bf
--- /dev/null
+++ b/src/gpu/pannotia/color/README.md
@@ -0,0 +1,68 @@
+---
+title: Pannotia Color Test
+tags:
+ - x86
+ - amdgpu
+layout: default
+permalink: resources/pannotia/bc
+shortdoc: >
+ Resources to build a disk image with the GCN3 Pannotia Color workload.
+---
+
+Graph Coloring (CLR) is a graph analytics application that is part of the Pannotia benchmark suite. It is used to label the vertices of a graph with colors such that no two adjacent vertices share the same color. The provided version is for use with the gpu-compute model of gem5. Thus, it has been ported from the prior CUDA and OpenCL variants to HIP, and validated on a Vega-class AMD GPU.
+
+Compiling both CLR variants, compiling the GCN3_X86/Vega_X86 versions of gem5, and running both CLR variants on gem5 is dependent on the gcn-gpu docker image, `util/dockerfiles/gcn-gpu/Dockerfile` on the [gem5 stable branch](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable).
+
+## Compilation and Running
+
+To compile Color:
+
+Color has two variants: max and maxmin. To compile the "max" variant:
+
+```
+cd src/gpu/pannotia/clr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu make gem5-fusion
+```
+
+To compile the "maxmin" variant:
+
+```
+cd src/gpu/pannotia/clr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu bash -c "export VARIANT=MAXMIN ; make gem5-fusion"
+```
+
+If you use the Makefile.default file instead, the Makefile will generate code designed to run on the real GPU instead. Moreover, note that Makefile.gem5-fusion requires you to set the GEM5_ROOT variable (either on the command line or by modifying the Makefile), because the Pannotia applications have been updated to use [m5ops](https://www.gem5.org/documentation/general_docs/m5ops/). By default, for both variants the Makefile builds for gfx801 and gfx803, and the binaries are placed in the src/gpu/pannotia/clr/bin folder. Moreover, by default the VARIANT variable Color's Makefile assumes the max variant is being used, hence why this variable does not need to be set for compiling it.
+
+## Compiling GCN3_X86/gem5.opt
+
+Color is a GPU application, which requires that gem5 is built with the GCN3_X86 (or Vega_X86, although this has been less heavily tested) architecture. The test is run with the GCN3_X86 gem5 variant, compiled using the gcn-gpu docker image:
+
+```
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest scons build/GCN3_X86/gem5.opt -j <num cores>
+```
+
+## Running Color on GCN3_X86/gem5.opt
+
+The following command shows how to run the CLR max version:
+
+# Assuming gem5 and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/clr/bin -c color_max.gem5 --options="1k_128k.gr 0"
+```
+
+To run the CLR maxmin version:
+
+# Assuming gem5, pannotia (input graphs, see below), and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/clr/bin -c color_maxmin.gem5 --options="1k_128k.gr 0"
+```
+
+Note that the datasets from the original Pannotia suite have been uploaded to: <http://dist.gem5.org/dist/develop/datasets/pannotia>. We recommend you start with the 1k_128k.gr input (<http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr>), as this is the smallest input that can be run with CLR. Note that 1k_128k is not designed for Color specifically though -- the above link has larger graphs designed to run with Color that you should consider using for larger experiments.
+
+## Pre-built binary
+
+A pre-built binary will be added soon.
diff --git a/src/gpu/pannotia/color/coloring_max.cpp b/src/gpu/pannotia/color/coloring_max.cpp
new file mode 100644
index 0000000..b85245e
--- /dev/null
+++ b/src/gpu/pannotia/color/coloring_max.cpp
@@ -0,0 +1,303 @@
+/************************************************************************************\
+ * *
+ * Copyright © 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+//#include <sys/time.h>
+#include "../graph_parser/parse.h"
+#include "../graph_parser/util.h"
+#include "kernel_max.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+#include <gem5/m5ops.h>
+#endif
+
+#define RANGE 2048
+
+void print_vector(int *vector, int num);
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+
+ int num_nodes;
+ int num_edges;
+ int file_format = 1;
+ bool directed = 0;
+
+ hipError_t err = hipSuccess;
+
+ if (argc == 3) {
+ tmpchar = argv[1]; //graph inputfile
+ file_format = atoi(argv[2]); //graph format
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ srand(7);
+
+ // Allocate the CSR structure
+ csr_array *csr;
+
+ // Parse graph file and store into a CSR format
+ if (file_format == 1)
+ csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
+ else if (file_format == 0)
+ csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
+ else {
+ printf("reserve for future");
+ exit(1);
+ }
+
+ // Allocate the vertex value array
+ int *node_value = (int *)malloc(num_nodes * sizeof(int));
+ if (!node_value) fprintf(stderr, "node_value malloc failed\n");
+ // Allocate the color array
+ int *color = (int *)malloc(num_nodes * sizeof(int));
+ if (!color) fprintf(stderr, "color malloc failed\n");
+
+ // Initialize all the colors to -1
+ // Randomize the value for each vertex
+ for (int i = 0; i < num_nodes; i++) {
+ color[i] = -1;
+ node_value[i] = rand() % RANGE;
+ }
+
+ int *row_d;
+ int *col_d;
+ int *max_d;
+
+ int *color_d;
+ int *node_value_d;
+ int *stop_d;
+
+ // Create device-side buffers for the graph
+ err = hipMalloc(&row_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_d (size:%d): %s\n", num_edges , hipGetErrorString(err));
+ return -1;
+ }
+
+ // Termination variable
+ err = hipMalloc(&stop_d, sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc stop_d (size:%d) => %s\n", 1 , hipGetErrorString(err));
+ return -1;
+ }
+
+ // Create device-side buffers for color
+ err = hipMalloc(&color_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc color_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&node_value_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc node_value_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&max_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc max_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+
+ // Copy data to device-side buffers
+// double timer1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ err = hipMemcpy(color_d, color, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy color_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(max_d, color, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy max_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(node_value_d, node_value, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy node_value_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ int block_size = 256;
+ int num_blocks = (num_nodes + block_size - 1) / block_size;
+
+ // Set up kernel dimensions
+ dim3 threads(block_size, 1, 1);
+ dim3 grid(num_blocks, 1, 1);
+
+ int stop = 1;
+ int graph_color = 1;
+
+ // Main computation loop
+// double timer3 = gettime();
+
+ while (stop) {
+
+ stop = 0;
+
+ // Copy the termination variable to the device
+ err = hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: write stop_d: %s\n", hipGetErrorString(err));
+ }
+
+ // Launch the color kernel 1
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(color1), dim3(grid), dim3(threads ), 0, 0, row_d, col_d, node_value_d, color_d,
+ stop_d, max_d, graph_color, num_nodes,
+ num_edges);
+
+ // Launch the color kernel 2
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(color2), dim3(grid), dim3(threads ), 0, 0, node_value_d, color_d, max_d, graph_color,
+ num_nodes, num_edges);
+
+ err = hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read stop_d: %s\n", hipGetErrorString(err));
+ }
+
+ // Increment the color for the next iter
+ graph_color++;
+
+ }
+ hipDeviceSynchronize();
+
+// double timer4 = gettime();
+
+ // Copy back the color array
+ err = hipMemcpy(color, color_d, num_nodes * sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ printf("ERROR: hipMemcpy(): %s\n", hipGetErrorString(err));
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+// double timer2 = gettime();
+
+ // Print out color and timing statistics
+ printf("total number of colors used: %d\n", graph_color);
+// printf("kernel time = %lf ms\n", (timer4 - timer3) * 1000);
+// printf("kernel + memcpy time = %lf ms\n", (timer2 - timer1) * 1000);
+
+#if 1
+ // Dump the color array into an output file
+ print_vector(color, num_nodes);
+#endif
+
+ // Free host-side buffers
+ free(node_value);
+ free(color);
+ csr->freeArrays();
+ free(csr);
+
+ // Free CUDA buffers
+ hipFree(row_d);
+ hipFree(col_d);
+ hipFree(max_d);
+ hipFree(color_d);
+ hipFree(node_value_d);
+ hipFree(stop_d);
+
+ return 0;
+
+}
+
+void print_vector(int *vector, int num)
+{
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++)
+ fprintf(fp, "%d: %d\n", i + 1, vector[i]);
+
+ fclose(fp);
+}
diff --git a/src/gpu/pannotia/color/coloring_maxmin.cpp b/src/gpu/pannotia/color/coloring_maxmin.cpp
new file mode 100644
index 0000000..7e7cd51
--- /dev/null
+++ b/src/gpu/pannotia/color/coloring_maxmin.cpp
@@ -0,0 +1,306 @@
+/************************************************************************************\
+ * *
+ * Copyright © 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+#include "../graph_parser/parse.h"
+#include "../graph_parser/util.h"
+#include "kernel_maxmin.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+#include <gem5/m5ops.h>
+#endif
+
+#define RANGE 2048
+
+void print_vector(int *vector, int num);
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+
+ int num_nodes;
+ int num_edges;
+ int file_format = 1;
+ bool directed = 0;
+
+ hipError_t err = hipSuccess;
+
+ if (argc == 3) {
+ tmpchar = argv[1]; //graph inputfile
+ file_format = atoi(argv[2]); //graph format
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ srand(7);
+
+ // Allocate the CSR structure
+ csr_array *csr;
+
+ // Parse graph file and store into a CSR format
+ if (file_format == 1)
+ csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
+ else if (file_format == 0)
+ csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
+ else {
+ printf("reserve for future");
+ exit(1);
+ }
+
+ // Allocate the vertex value array
+ int *node_value = (int *)malloc(num_nodes * sizeof(int));
+ if (!node_value) fprintf(stderr, "node_value malloc failed\n");
+ // Allocate the color array
+ int *color = (int *)malloc(num_nodes * sizeof(int));
+ if (!color) fprintf(stderr, "color malloc failed\n");
+
+ // Initialize all the colors to -1
+ // Randomize the value for each vertex
+ for (int i = 0; i < num_nodes; i++) {
+ color[i] = -1;
+ node_value[i] = rand() % RANGE;
+ }
+
+ int *row_d;
+ int *col_d;
+ int *max_d;
+ int *min_d;
+
+ int *color_d;
+ int *node_value_d;
+ int *stop_d;
+
+ // Create device-side buffers for the graph
+ err = hipMalloc(&row_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_d (size:%d): %s\n", num_edges , hipGetErrorString(err));
+ return -1;
+ }
+
+ // Termination variable
+ err = hipMalloc(&stop_d, sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc stop_d (size:%d) => %s\n", 1 , hipGetErrorString(err));
+ return -1;
+ }
+
+ // Create device-side buffers for color
+ err = hipMalloc(&color_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc color_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&node_value_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc node_value_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&max_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc max_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&min_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc min_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+
+ // Copy data to device-side buffers
+ double timer1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ err = hipMemcpy(color_d, color, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy color_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(node_value_d, node_value, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy node_value_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ int block_size = 256;
+ int num_blocks = (num_nodes + block_size - 1) / block_size;
+
+ // Set up kernel dimensions
+ dim3 threads(block_size, 1, 1);
+ dim3 grid(num_blocks, 1, 1);
+
+ int stop = 1;
+ int graph_color = 1;
+
+ // Initialize arrays
+ hipLaunchKernelGGL(ini, dim3(grid), dim3(threads ), 0, 0, max_d, min_d, num_nodes);
+
+ // Main computation loop
+ double timer3 = gettime();
+
+ while (stop) {
+
+ stop = 0;
+
+ // Copy the termination variable to the device
+ err = hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: write stop_d: %s\n", hipGetErrorString(err));
+ }
+
+ // Launch the color kernel 1
+ hipLaunchKernelGGL(color1, dim3(grid), dim3(threads ), 0, 0, row_d, col_d, node_value_d, color_d,
+ stop_d, max_d, min_d, graph_color,
+ num_nodes, num_edges);
+
+ // Launch the color kernel 2
+ hipLaunchKernelGGL(color2, dim3(grid), dim3(threads ), 0, 0, node_value_d, color_d, max_d, min_d,
+ graph_color, num_nodes, num_edges);
+
+ err = hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read stop_d: %s\n", hipGetErrorString(err));
+ }
+
+ // Update the color label for the next iter
+ graph_color = graph_color + 2;
+
+ }
+ hipDeviceSynchronize();
+
+ double timer4 = gettime();
+
+ // Copy back the color array
+ err = hipMemcpy(color, color_d, num_nodes * sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ printf("ERROR: hipMemcpy(): %s\n", hipGetErrorString(err));
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+ double timer2 = gettime();
+
+ // Print out color and timing statistics
+ printf("total number of colors used: %d\n", graph_color);
+ printf("kernel time = %lf ms\n", (timer4 - timer3) * 1000);
+ printf("kernel + memcpy time = %lf ms\n", (timer2 - timer1) * 1000);
+
+#if 1
+ // Dump the color array into an output file
+ print_vector(color, num_nodes);
+#endif
+
+ // Free host-side buffers
+ free(node_value);
+ free(color);
+ csr->freeArrays();
+ free(csr);
+
+ // Free CUDA buffers
+ hipFree(row_d);
+ hipFree(col_d);
+ hipFree(max_d);
+ hipFree(color_d);
+ hipFree(node_value_d);
+ hipFree(stop_d);
+
+ return 0;
+
+}
+
+void print_vector(int *vector, int num)
+{
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++)
+ fprintf(fp, "%d: %d\n", i + 1, vector[i]);
+
+ fclose(fp);
+}
diff --git a/src/gpu/pannotia/color/kernel_max.h b/src/gpu/pannotia/color/kernel_max.h
new file mode 100644
index 0000000..f560a29
--- /dev/null
+++ b/src/gpu/pannotia/color/kernel_max.h
@@ -0,0 +1,139 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#ifndef KERNEL_MAX_H
+#define KERNEL_MAX_H
+
+#include "hip/hip_runtime.h"
+
+/**
+ * @brief color kernel 1
+ * @param row CSR pointer array
+ * @param col CSR column array
+ * @param node_value Vertex value array
+ * @param color_array Color value array
+ * @param stop Termination variable
+ * @param max_d Max array
+ * @param color Current color label
+ * @param num_nodes Number of vertices
+ * @param num_edges Number of edges
+ */
+__global__ void color1(int *row, int *col, int *node_value, int *color_array,
+ int *stop, int *max_d, const int color,
+ const int num_nodes, const int num_edges)
+{
+ // Get my thread workitem id
+ int tid = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ // If the vertex is still not colored
+ if (color_array[tid] == -1) {
+
+ // Get the start and end pointer of the neighbor list
+ int start = row[tid];
+ int end;
+ if (tid + 1 < num_nodes)
+ end = row[tid + 1];
+ else
+ end = num_edges;
+
+ int maximum = -1;
+ // Navigate the neighbor list
+ for (int edge = start; edge < end; edge++) {
+ // Determine if the vertex value is the maximum in the neighborhood
+ if (color_array[col[edge]] == -1 && start != end - 1) {
+ *stop = 1;
+ if (node_value[col[edge]] > maximum)
+ maximum = node_value[col[edge]];
+ }
+ }
+ // Assign maximum the max array
+ max_d[tid] = maximum;
+ }
+ }
+}
+
+
+/**
+ * @brief color kernel 2
+ * @param node_value Vertex value array
+ * @param color_array Color value array
+ * @param max_d Max array
+ * @param color Current color label
+ * @param num_nodes Number of vertices
+ * @param num_edges Number of edges
+ */
+__global__ void color2(int *node_value, int *color_array, int *max_d,
+ const int color, const int num_nodes,
+ const int num_edges)
+{
+ // Get my workitem id
+ int tid = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ // If the vertex is still not colored
+ if (color_array[tid] == -1) {
+ if (node_value[tid] >= max_d[tid])
+ // Assign a color
+ color_array[tid] = color;
+ }
+ }
+
+}
+
+#endif // KERNEL_MAX_H
diff --git a/src/gpu/pannotia/color/kernel_maxmin.h b/src/gpu/pannotia/color/kernel_maxmin.h
new file mode 100644
index 0000000..eb93f80
--- /dev/null
+++ b/src/gpu/pannotia/color/kernel_maxmin.h
@@ -0,0 +1,167 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#ifndef KERNEL_MAXMIN_H
+#define KERNEL_MAXMIN_H
+
+#include "hip/hip_runtime.h"
+
+#define BIG_NUM 999999
+
+/**
+ * @brief color kernel 1
+ * @param row CSR pointer array
+ * @param col CSR column array
+ * @param node_value Vertex value array
+ * @param color_array Color value array
+ * @param stop Termination variable
+ * @param max_d Max array
+ * @param max_d Min array
+ * @param color Current color label
+ * @param num_nodes Number of vertices
+ * @param num_edges Number of edges
+ */
+__global__ void color1(int *row, int *col, int *node_value, int *color_array,
+ int *stop, int *max_d, int *min_d, const int color,
+ const int num_nodes, const int num_edges)
+{
+ // Get my workitem id
+ int tid = blockIdx.x * blockDim.x + threadIdx.x;
+
+ if (tid < num_nodes) {
+ // If the vertex is not colored
+ if (color_array[tid] == -1) {
+
+ // Get the start and end pointers for the neighbor list
+ int start = row[tid];
+ int end;
+ if (tid + 1 < num_nodes)
+ end = row[tid + 1];
+ else
+ end = num_edges;
+
+ int maximum = -1;
+ int minimum = BIG_NUM;
+ // Navigate the neighborlist
+ for (int edge = start; edge < end; edge++) {
+ if (color_array[col[edge]] == -1 && start != end - 1) {
+ *stop = 1;
+ // Determine if the vertex value is the maximum/minimum in the neighborhood
+ if (node_value[col[edge]] > maximum)
+ maximum = node_value[col[edge]];
+ if (node_value[col[edge]] < minimum)
+ minimum = node_value[col[edge]];
+ }
+ }
+ // Assign the maximum/miminum value to max/min array
+ max_d[tid] = maximum;
+ min_d[tid] = minimum;
+ }
+ }
+}
+
+/**
+ * @brief color kernel 2
+ * @param node_value Vertex value array
+ * @param color_array Color value array
+ * @param max_d Max array
+ * @param min_d Min array
+ * @param color Current color label
+ * @param num_nodes Number of vertices
+ * @param num_edges Number of edges
+ */
+__global__ void color2(int *node_value, int *color_array, int *max_d,
+ int *min_d, const int color, const int num_nodes,
+ const int num_edges)
+{
+ // Get my workitem id
+ int tid = blockIdx.x * blockDim.x + threadIdx.x;
+
+ if (tid < num_nodes) {
+ // If the vertex is still not colored
+ if (color_array[tid] == -1) {
+ // Assign a color
+ if (node_value[tid] >= max_d[tid])
+ color_array[tid] = color;
+ if (node_value[tid] <= min_d[tid])
+ color_array[tid] = color + 1;
+ }
+ }
+
+}
+
+/**
+ * @brief init kernel
+ * @param max_d Max array
+ * @param min_d Min array
+ * @param num_nodes Number of vertices
+ */
+__global__ void ini(int *max_d, int *min_d, const int num_nodes)
+{
+ // Get my workitem id
+ int tid = blockIdx.x * blockDim.x + threadIdx.x;
+
+ // Initialize max: -1 and min: Big_num
+ if (tid < num_nodes) {
+ max_d[tid] = -1;
+ min_d[tid] = BIG_NUM;
+ }
+
+}
+
+#endif
diff --git a/src/gpu/pannotia/fw/Floyd-Warshall.cpp b/src/gpu/pannotia/fw/Floyd-Warshall.cpp
new file mode 100644
index 0000000..75befaa
--- /dev/null
+++ b/src/gpu/pannotia/fw/Floyd-Warshall.cpp
@@ -0,0 +1,237 @@
+/************************************************************************************\
+ * *
+ * Copyright © 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+//#include <sys/time.h>
+//#include <omp.h>
+#include "../graph_parser/util.h"
+#include "kernel.h"
+#include "parse.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+#include <gem5/m5ops.h>
+#endif
+
+#ifdef GEM5_FUSION
+#define MAX_ITERS 192
+#else
+#include <stdint.h>
+#define MAX_ITERS INT32_MAX
+#endif
+
+#define BIGNUM 999999
+#define TRUE 1
+#define FALSE 0
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+ bool verify_results = false;
+
+ int num_nodes;
+ int num_edges;
+
+ hipError_t err = hipSuccess;
+
+ // Get program input
+ if (argc >= 2) {
+ tmpchar = argv[1]; // Graph input file
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ if (argc >= 3) {
+ if (atoi(argv[2]) == 1) {
+ verify_results = true;
+ }
+ }
+
+ // Parse the adjacency matrix
+ int *adjmatrix = parse_graph_file(&num_nodes, &num_edges, tmpchar);
+ int dim = num_nodes;
+
+ // Initialize the distance matrix
+ int *distmatrix = (int *)malloc(dim * dim * sizeof(int));
+ if (!distmatrix) fprintf(stderr, "malloc failed - distmatrix\n");
+
+ // Initialize the result matrix
+ int *result = (int *)malloc(dim * dim * sizeof(int));
+ if (!result) fprintf(stderr, "malloc failed - result\n");
+
+ // TODO: Now only supports integer weights
+ // Setup the input matrix
+ for (int i = 0 ; i < dim; i++) {
+ for (int j = 0 ; j < dim; j++) {
+ if (i == j) {
+ // Diagonal
+ distmatrix[i * dim + j] = 0;
+ } else if (adjmatrix[i * dim + j] == -1) {
+ // Without edge
+ distmatrix[i * dim + j] = BIGNUM;
+ } else {
+ // With edge
+ distmatrix[i * dim + j] = adjmatrix[i * dim + j];
+ }
+ }
+ }
+
+ int *dist_d;
+ int *next_d;
+
+ // Create device-side FW buffers
+ err = hipMalloc(&dist_d, dim * dim * sizeof(int));
+ if (err != hipSuccess) {
+ printf("ERROR: hipMalloc dist_d (size:%d) => %d\n", dim * dim , err);
+ return -1;
+ }
+ err = hipMalloc(&next_d, dim * dim * sizeof(int));
+ if (err != hipSuccess) {
+ printf("ERROR: hipMalloc next_d (size:%d) => %d\n", dim * dim , err);
+ return -1;
+ }
+
+ //double timer1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ // Copy the dist matrix to the device
+ err = hipMemcpy(dist_d, distmatrix, dim * dim * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy feature_d (size:%d) => %d\n", dim * dim, err);
+ return -1;
+ }
+
+ // Work dimension
+ dim3 threads(16, 16, 1);
+ dim3 grid(num_nodes / 16, num_nodes / 16, 1);
+
+ //double timer3 = gettime();
+ // Main computation loop
+ for (int k = 1; k < dim && k < MAX_ITERS; k++) {
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(floydwarshall), dim3(grid), dim3(threads), 0, 0, dist_d, next_d, dim, k);
+ }
+ hipDeviceSynchronize();
+
+ //double timer4 = gettime();
+ err = hipMemcpy(result, dist_d, dim * dim * sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read back dist_d %d failed\n", err);
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+ //double timer2 = gettime();
+
+ //printf("kernel time = %lf ms\n", (timer4 - timer3) * 1000);
+ //printf("kernel + memcpy time = %lf ms\n", (timer2 - timer1) * 1000);
+
+ if (verify_results) {
+ // Below is the verification part
+ // Calculate on the CPU
+ int *dist = distmatrix;
+ for (int k = 0; k < dim; k++) {
+ for (int i = 0; i < dim; i++) {
+ for (int j = 0; j < dim; j++) {
+ if (dist[i * dim + k] + dist[k * dim + j] < dist[i * dim + j]) {
+ dist[i * dim + j] = dist[i * dim + k] + dist[k * dim + j];
+ }
+ }
+ }
+ }
+
+ // Compare results
+ bool check_flag = 0;
+ for (int i = 0; i < dim; i++) {
+ for (int j = 0; j < dim; j++) {
+ if (dist[i * dim + j] != result[i * dim + j]) {
+ fprintf(stderr, "mismatch at (%d, %d)\n", i, j);
+ check_flag = 1;
+ }
+ }
+ }
+ // If there is mismatch, report
+ if (check_flag) {
+ fprintf(stdout, "WARNING: Produced incorrect results!\n");
+ } else {
+ printf("Results are correct!\n");
+ }
+ }
+
+ printf("Finishing Floyd-Warshall\n");
+
+ // Free host-side buffers
+ free(adjmatrix);
+ free(result);
+ free(distmatrix);
+
+ // Free CUDA buffers
+ hipFree(dist_d);
+ hipFree(next_d);
+
+ return 0;
+}
diff --git a/src/gpu/pannotia/fw/Makefile b/src/gpu/pannotia/fw/Makefile
new file mode 100644
index 0000000..6158bac
--- /dev/null
+++ b/src/gpu/pannotia/fw/Makefile
@@ -0,0 +1,11 @@
+default:
+ make -f Makefile.default
+
+clean:
+ make -f Makefile.default clean
+
+gem5-fusion:
+ make -f Makefile.gem5-fusion
+
+clean-gem5-fusion:
+ make -f Makefile.gem5-fusion clean
diff --git a/src/gpu/pannotia/fw/Makefile.default b/src/gpu/pannotia/fw/Makefile.default
new file mode 100644
index 0000000..20c40e7
--- /dev/null
+++ b/src/gpu/pannotia/fw/Makefile.default
@@ -0,0 +1,19 @@
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+EXECUTABLE = fw_hip
+OPTS = -O3
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): Floyd-Warshall.cpp parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) $(OPTS) --amdgpu-target=gfx801,gfx803,gfx906 $(CXXFLAGS) parse.cpp ../graph_parser/util.cpp Floyd-Warshall.cpp -o $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: fw clean
diff --git a/src/gpu/pannotia/fw/Makefile.gem5-fusion b/src/gpu/pannotia/fw/Makefile.gem5-fusion
new file mode 100644
index 0000000..801c46f
--- /dev/null
+++ b/src/gpu/pannotia/fw/Makefile.gem5-fusion
@@ -0,0 +1,23 @@
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+# these are needed for m5ops
+# TODO: Need some sort of explicit PATH? Read in?
+GEM5_PATH ?= /nobackup/sinclair/gem5
+CFLAGS += -I$(GEM5_PATH)/include
+LDFLAGS += -L$(GEM5_PATH)/util/m5/build/x86/out -lm5
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/fw_hip.gem5
+
+$(BIN_DIR)/fw_hip.gem5: Floyd-Warshall.cpp parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) -O3 --amdgpu-target=gfx801,gfx803 $(CXXFLAGS) parse.cpp ../graph_parser/util.cpp Floyd-Warshall.cpp -DGEM5_FUSION -o $(BIN_DIR)/fw_hip.gem5 $(CFLAGS) $(LDFLAGS)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: fw clean
diff --git a/src/gpu/pannotia/fw/README.md b/src/gpu/pannotia/fw/README.md
new file mode 100644
index 0000000..39424bb
--- /dev/null
+++ b/src/gpu/pannotia/fw/README.md
@@ -0,0 +1,49 @@
+---
+title: Pannotia FW Test
+tags:
+ - x86
+ - amdgpu
+layout: default
+permalink: resources/pannotia/fw
+shortdoc: >
+ Resources to build a disk image with the GCN3 Pannotia FW workload.
+---
+
+Floyd-Warshall (FW) is a graph analytics application that is part of the Pannotia benchmark suite. It is a classical dynamic-programming algorithm designed to solve the all-pairs shortest path (APSP) problem. The provided version is for use with the gpu-compute model of gem5. Thus, it has been ported from the prior CUDA and OpenCL variants to HIP, and validated on a Vega-class AMD GPU.
+
+Compiling FW, compiling the GCN3_X86/Vega_X86 versions of gem5, and running FW on gem5 is dependent on the gcn-gpu docker image, `util/dockerfiles/gcn-gpu/Dockerfile` on the [gem5 stable branch](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable).
+
+## Compilation and Running
+
+To compile FW:
+
+```
+cd src/gpu/pannotia/fw
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu make gem5-fusion
+```
+
+If you use the Makefile.default file instead, the Makefile will generate code designed to run on the real GPU instead. Moreover, note that Makefile.gem5-fusion requires you to set the GEM5_ROOT variable (either on the command line or by modifying the Makefile), because the Pannotia applications have been updated to use [m5ops](https://www.gem5.org/documentation/general_docs/m5ops/). By default, the Makefile builds for gfx801 and gfx803, and is placed in the src/gpu/pannotia/fw/bin folder.
+
+## Compiling GCN3_X86/gem5.opt
+
+FW is a GPU application, which requires that gem5 is built with the GCN3_X86 (or Vega_X86, although this has been less heavily tested) architecture. The test is run with the GCN3_X86 gem5 variant, compiled using the gcn-gpu docker image:
+
+```
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest scons build/GCN3_X86/gem5.opt -j <num cores>
+```
+
+## Running FW on GCN3_X86/gem5.opt
+
+# Assuming gem5 and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/fw/bin -c fw_hip.gem5 --options="1k_128k.gr"
+```
+
+Note that the datasets from the original Pannotia suite have been uploaded to: <http://dist.gem5.org/dist/develop/datasets/pannotia>. We recommend you start with the 1k_128k.gr input (<http://dist.gem5.org/dist/develop/datasets/pannotia/fw/1k_128k.gr>), as this is the smallest input that can be run with FW. Note that 1k_128k is not designed for FW specifically though -- the above link has larger graphs designed to run with FW that you should consider using for larger experiments.
+
+## Pre-built binary
+
+A pre-built binary will be added soon.
diff --git a/src/gpu/pannotia/fw/kernel.h b/src/gpu/pannotia/fw/kernel.h
new file mode 100644
index 0000000..3474a2f
--- /dev/null
+++ b/src/gpu/pannotia/fw/kernel.h
@@ -0,0 +1,88 @@
+/************************************************************************************\
+ * *
+ * Copyright © 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#ifndef KERNEL_H
+#define KERNEL_H
+
+#include "hip/hip_runtime.h"
+
+/**
+ * @brief naive floyd warshal kernel
+ * @param dist Distance array
+ * @param next Next array
+ * @param dim Dimension of the 2-D matrix
+ * @param k Current iteration number
+ */
+__global__ void
+floydwarshall(int *dist, int *next, int dim, int k)
+{
+ // Get my workitem id x_dim
+ int i = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+ // Get my workitem id y_dim
+ int j = hipBlockDim_y * hipBlockIdx_y + hipThreadIdx_y;
+
+ if (i < dim && j < dim) {
+ // if (dist i -> k + k -> j) update the dist i-> j
+ if (dist[i * dim + k] + dist[k * dim + j] < dist[i * dim + j]) {
+ dist[i * dim + j] = dist[i * dim + k] + dist[k * dim + j];
+ next[i * dim + j] = k;
+ }
+ }
+}
+
+#endif // KERNEL_H
diff --git a/src/gpu/pannotia/fw/parse.cpp b/src/gpu/pannotia/fw/parse.cpp
new file mode 100644
index 0000000..eab11ea
--- /dev/null
+++ b/src/gpu/pannotia/fw/parse.cpp
@@ -0,0 +1,89 @@
+
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+// Test value
+bool test_value(int* array, int dim, int i, int j)
+{
+
+ // TODO: Current does not support multiple edges between two vertices
+ if (array[i * dim + j] != -1) {
+ // fprintf(stderr, "Possibly duplicate records at (%d, %d)\n", i, j);
+ return 0;
+ } else
+ return 1;
+}
+
+// Set value (i, j) = value
+void set_value(int* array, int dim, int i, int j, int value)
+{
+ array[i * dim + j] = value;
+}
+
+int* parse_graph_file(int *num_nodes, int *num_edges, char* tmpchar)
+{
+
+ int *adjmatrix;
+ int cnt = 0;
+ unsigned int lineno = 0;
+ char line[128], sp[2], a, p;
+
+ FILE *fptr;
+
+ fptr = fopen(tmpchar, "r");
+
+ if (!fptr) {
+ fprintf(stderr, "Error when opening file: %s\n", tmpchar);
+ perror("fopen Error:");
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+
+ while (fgets(line, 100, fptr)) {
+ int head, tail, weight;
+ long long unsigned size;
+ switch (line[0]) {
+ case 'c':
+ break;
+ case 'p':
+ sscanf(line, "%c %s %d %d", &p, sp, num_nodes, num_edges);
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", *num_nodes, *num_edges);
+ size = (long long unsigned)(*num_nodes + 1) * (long long unsigned)(*num_nodes + 1);
+ if (size > UINT_MAX) {
+ fclose(fptr);
+ fprintf(stderr, "ERROR: Too many nodes, huge adjacency matrix\n");
+ exit(0);
+ }
+ adjmatrix = (int *)malloc(size * sizeof(int));
+ memset(adjmatrix, -1 , size * sizeof(int));
+ break;
+ case 'a':
+ sscanf(line, "%c %d %d %d", &a, &head, &tail, &weight);
+ if (tail == head) printf("reporting self loop\n");
+ if (test_value(adjmatrix, *num_nodes + 1, head, tail)) {
+ set_value(adjmatrix, *num_nodes + 1, head, tail, weight);
+ cnt++;
+ }
+
+#ifdef VERBOSE
+ printf("Adding edge: %d ==> %d ( %d )\n", head, tail, weight);
+#endif
+ break;
+ default:
+ fprintf(stderr, "exiting loop\n");
+ break;
+ }
+ lineno++;
+ }
+
+ *num_edges = cnt;
+ printf("Actual added edges: %d\n", cnt);
+
+ fclose(fptr);
+
+ return adjmatrix;
+
+}
diff --git a/src/gpu/pannotia/fw/parse.h b/src/gpu/pannotia/fw/parse.h
new file mode 100644
index 0000000..01001e2
--- /dev/null
+++ b/src/gpu/pannotia/fw/parse.h
@@ -0,0 +1,6 @@
+#ifndef __FW_PARSE_H__
+#define __FW_PARSE_H__
+
+int* parse_graph_file(int *num_nodes, int *num_edges, char* tmpchar);
+
+#endif
diff --git a/src/gpu/pannotia/graph_parser/parse.cpp b/src/gpu/pannotia/graph_parser/parse.cpp
new file mode 100644
index 0000000..80fb6f4
--- /dev/null
+++ b/src/gpu/pannotia/graph_parser/parse.cpp
@@ -0,0 +1,882 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "parse.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include <string.h>
+#include <algorithm>
+#include <sys/time.h>
+#include "util.h"
+
+bool doCompare(CooTuple elem1, CooTuple elem2)
+{
+ if (elem1.row < elem2.row) {
+ return true;
+ }
+ return false;
+}
+
+ell_array *csr2ell(csr_array *csr, int num_nodes, int num_edges, int fill)
+{
+ int size, maxheight = 0;
+ for (int i = 0; i < num_nodes; i++) {
+ size = csr->row_array[i + 1] - csr->row_array[i];
+ if (size > maxheight)
+ maxheight = size;
+ }
+
+ ell_array *ell = (ell_array *)malloc(sizeof(ell_array));
+ if (!ell) printf("malloc failed");
+
+ ell->max_height = maxheight;
+ ell->num_nodes = num_nodes;
+
+ ell->col_array = (int*)malloc(sizeof(int) * maxheight * num_nodes);
+ ell->data_array = (int*)malloc(sizeof(int) * maxheight * num_nodes);
+
+
+ for (int i = 0; i < maxheight * num_nodes; i++) {
+ ell->col_array[i] = 0;
+ ell->data_array[i] = fill;
+ }
+
+ for (int i = 0; i < num_nodes; i++) {
+ int start = csr->row_array[i];
+ int end = csr->row_array[i + 1];
+ int lastcolid = 0;
+ for (int j = start; j < end; j++) {
+ int colid = csr->col_array[j];
+ int data = csr->data_array[j];
+ ell->col_array[i + (j - start) * num_nodes] = colid;
+ ell->data_array[i + (j - start) * num_nodes] = data;
+ lastcolid = colid;
+ }
+ for (int j = end; j < start + maxheight; j++) {
+ ell->col_array[i + (j - start) * num_nodes] = lastcolid;
+ ell->data_array[i + (j - start) * num_nodes] = fill;
+ }
+ }
+
+ return ell;
+
+}
+
+csr_array *parseMetis(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed)
+{
+
+ int cnt = 0;
+ unsigned int lineno = 0;
+ char *line = (char *)malloc(8192);
+ int num_edges = 0, num_nodes = 0;
+
+ FILE *fptr;
+ CooTuple *tuple_array = NULL;
+
+ fptr = fopen(tmpchar, "r");
+ if (!fptr) {
+ fprintf(stderr, "Error when opening file: %s\n", tmpchar);
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+
+ while (fgets(line, 8192, fptr)) {
+ int head, tail, weight = 0;
+ CooTuple temp;
+
+ if (line[0] == '%') continue; // skip comment lines
+
+ if (lineno == 0) { //the first line
+
+ sscanf(line, "%d %d", p_num_nodes, p_num_edges);
+ if (!directed) {
+ *p_num_edges = *p_num_edges * 2;
+ printf("This is an undirected graph\n");
+ } else {
+ printf("This is a directed graph\n");
+ }
+ num_nodes = *p_num_nodes;
+ num_edges = *p_num_edges;
+
+
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", num_nodes, num_edges);
+ tuple_array = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ } else if (lineno > 0) { //from the second line
+
+ char *pch;
+ pch = strtok(line , " ,.-");
+ while (pch != NULL) {
+ head = lineno;
+ tail = atoi(pch);
+ if (tail <= 0) break;
+
+ if (tail == head) printf("reporting self loop: %d, %d\n", lineno + 1, lineno);
+
+ temp.row = head - 1;
+ temp.col = tail - 1;
+ temp.val = weight;
+
+ tuple_array[cnt++] = temp;
+
+ pch = strtok(NULL, " ,.-");
+
+ }
+ }
+
+#ifdef VERBOSE
+ printf("Adding edge: %d ==> %d ( %d )\n", head, tail, weight);
+#endif
+
+ lineno++;
+
+ }
+
+ // Metis files are stored in row-order, so sorting is unnecessary
+ // std::stable_sort(tuple_array, tuple_array + num_edges, doCompare);
+
+#ifdef VERBOSE
+ for (int i = 0 ; i < num_edges; i++) {
+ printf("%d: %d, %d, %d\n", i, tuple_array[i].row, tuple_array[i].col, tuple_array[i].val);
+ }
+#endif
+
+ int *row_array = (int *)malloc((num_nodes + 1) * sizeof(int));
+ int *col_array = (int *)malloc(num_edges * sizeof(int));
+ int *data_array = (int *)malloc(num_edges * sizeof(int));
+
+ int row_cnt = 0;
+ int prev = -1;
+ int idx;
+ for (idx = 0; idx < num_edges; idx++) {
+ int curr = tuple_array[idx].row;
+ if (curr != prev) {
+ row_array[row_cnt++] = idx;
+ prev = curr;
+ }
+ col_array[idx] = tuple_array[idx].col;
+ data_array[idx] = tuple_array[idx].val;
+
+ }
+ row_array[row_cnt] = idx;
+
+ csr_array *csr = (csr_array *)malloc(sizeof(csr_array));
+ memset(csr, 0, sizeof(csr_array));
+ csr->row_array = row_array;
+ csr->col_array = col_array;
+ csr->data_array = data_array;
+
+ fclose(fptr);
+ free(tuple_array);
+ free(line);
+
+ return csr;
+
+}
+
+
+csr_array *parseCOO(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed)
+{
+ int cnt = 0;
+ unsigned int lineno = 0;
+ char line[128], sp[2], a, p;
+ int num_nodes = 0, num_edges = 0;
+
+ FILE *fptr;
+ CooTuple *tuple_array = NULL;
+
+ fptr = fopen(tmpchar, "r");
+ if (!fptr) {
+ fprintf(stderr, "Error when opening file: %s\n", tmpchar);
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+
+ while (fgets(line, 100, fptr)) {
+ int head, tail, weight;
+ switch (line[0]) {
+ case 'c':
+ break;
+ case 'p':
+ sscanf(line, "%c %s %d %d", &p, sp, p_num_nodes, p_num_edges);
+
+ if (!directed) {
+ *p_num_edges = *p_num_edges * 2;
+ printf("This is an undirected graph\n");
+ } else {
+ printf("This is a directed graph\n");
+ }
+
+ num_nodes = *p_num_nodes;
+ num_edges = *p_num_edges;
+
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", num_nodes, num_edges);
+ tuple_array = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ break;
+
+ case 'a':
+ sscanf(line, "%c %d %d %d", &a, &head, &tail, &weight);
+ if (tail == head) printf("reporting self loop\n");
+ CooTuple temp;
+ temp.row = head - 1;
+ temp.col = tail - 1;
+ temp.val = weight;
+ tuple_array[cnt++] = temp;
+ if (!directed) {
+ temp.row = tail - 1;
+ temp.col = head - 1;
+ temp.val = weight;
+ tuple_array[cnt++] = temp;
+ }
+
+#ifdef VERBOSE
+ printf("Adding edge: %d ==> %d ( %d )\n", head, tail, weight);
+#endif
+ break;
+ default:
+ fprintf(stderr, "exiting loop\n");
+ break;
+ }
+ lineno++;
+ }
+
+ std::stable_sort(tuple_array, tuple_array + num_edges, doCompare);
+
+#ifdef VERBOSE
+ for (int i = 0 ; i < num_edges; i++) {
+ printf("%d: %d, %d, %d\n", i, tuple_array[i].row, tuple_array[i].col, tuple_array[i].val);
+ }
+#endif
+
+ int *row_array = (int *)malloc((num_nodes + 1) * sizeof(int));
+ int *col_array = (int *)malloc(num_edges * sizeof(int));
+ int *data_array = (int *)malloc(num_edges * sizeof(int));
+
+ int row_cnt = 0;
+ int prev = -1;
+ int idx;
+ for (idx = 0; idx < num_edges; idx++) {
+ int curr = tuple_array[idx].row;
+ if (curr != prev) {
+ row_array[row_cnt++] = idx;
+ prev = curr;
+ }
+
+ col_array[idx] = tuple_array[idx].col;
+ data_array[idx] = tuple_array[idx].val;
+ }
+
+ row_array[row_cnt] = idx;
+
+ fclose(fptr);
+ free(tuple_array);
+
+ csr_array *csr = (csr_array *)malloc(sizeof(csr_array));
+ memset(csr, 0, sizeof(csr_array));
+ csr->row_array = row_array;
+ csr->col_array = col_array;
+ csr->data_array = data_array;
+
+ return csr;
+
+}
+
+// Parse Metis file with double edges
+double_edges *parseMetis_doubleEdge(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed)
+{
+ int cnt = 0;
+ unsigned int lineno = 0;
+ char line[4096];
+ int num_edges = 0, num_nodes = 0;
+ FILE *fptr;
+ CooTuple *tuple_array = NULL;
+
+ fptr = fopen(tmpchar, "r");
+ if (!fptr) {
+ fprintf(stderr, "Error when opening file: %s\n", tmpchar);
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+
+ while (fgets(line, 4096, fptr)) {
+ int head, tail, weight = 0;
+ CooTuple temp;
+
+ if (line[0] == '%') continue; // skip comment lines
+
+ if (lineno == 0) { //the first line
+
+ sscanf(line, "%d %d", p_num_nodes, p_num_edges);
+ if (!directed) {
+ *p_num_edges = *p_num_edges * 2;
+ printf("This is an undirected graph\n");
+ } else {
+ printf("This is a directed graph\n");
+ }
+
+ num_nodes = *p_num_nodes;
+ num_edges = *p_num_edges;
+
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", num_nodes, num_edges);
+ tuple_array = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ if (!tuple_array) printf("xxxxxxxx\n");
+
+ } else if (lineno > 0) { //from the second line
+ char *pch;
+ pch = strtok(line , " ,.-");
+ while (pch != NULL) {
+ head = lineno;
+ tail = atoi(pch);
+ if (tail <= 0) break;
+
+ if (tail == head) printf("reporting self loop: %d, %d\n", lineno + 1, lineno);
+
+ temp.row = head - 1;
+ temp.col = tail - 1;
+ temp.val = weight;
+
+ tuple_array[cnt++] = temp;
+
+ pch = strtok(NULL, " ,.-");
+ }
+ }
+
+#ifdef VERBOSE
+ printf("Adding edge: %d ==> %d ( %d )\n", head, tail, weight);
+#endif
+
+ lineno++;
+ }
+
+ // Metis files are stored in row-order, so sorting is unnecessary
+ // std::stable_sort(tuple_array, tuple_array + num_edges, doCompare);
+
+#ifdef VERBOSE
+ for (int i = 0 ; i < num_edges; i++) {
+ printf("%d: %d, %d, %d\n", i, tuple_array[i].row, tuple_array[i].col, tuple_array[i].val);
+ }
+#endif
+
+ int *edge_array1 = (int *)malloc(num_edges * sizeof(int));
+ int *edge_array2 = (int *)malloc(num_edges * sizeof(int));
+
+ for (int i = 0; i < num_edges; i++) {
+ edge_array1[i] = tuple_array[i].row;
+ edge_array2[i] = tuple_array[i].col;
+ }
+
+ fclose(fptr);
+ free(tuple_array);
+
+ double_edges *de = (double_edges *)malloc(sizeof(double_edges));
+ de->edge_array1 = edge_array1;
+ de->edge_array2 = edge_array2;
+
+ return de;
+
+}
+
+// Parse COO file with double edges
+double_edges *parseCOO_doubleEdge(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed)
+{
+ int cnt = 0;
+ unsigned int lineno = 0;
+ char line[128], sp[2], a, p;
+ int num_nodes = 0, num_edges = 0;
+
+ FILE *fptr;
+ CooTuple *tuple_array = NULL;
+
+ fptr = fopen(tmpchar, "r");
+ if (!fptr) {
+ fprintf(stderr, "Error when opening file: %s\n", tmpchar);
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+
+ while (fgets(line, 100, fptr)) {
+ int head, tail, weight;
+ switch (line[0]) {
+ case 'c':
+ break;
+ case 'p':
+ sscanf(line, "%c %s %d %d", &p, sp, p_num_nodes, p_num_edges);
+
+ if (!directed) {
+ *p_num_edges = *p_num_edges * 2;
+ printf("This is an undirected graph\n");
+ } else {
+ printf("This is a directed graph\n");
+ }
+
+ num_nodes = *p_num_nodes;
+ num_edges = *p_num_edges;
+
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", num_nodes, num_edges);
+ tuple_array = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ break;
+ case 'a':
+ sscanf(line, "%c %d %d %d", &a, &head, &tail, &weight);
+ if (tail == head) printf("reporting self loop\n");
+ CooTuple temp;
+ temp.row = head - 1;
+ temp.col = tail - 1;
+ temp.val = weight;
+ tuple_array[cnt++] = temp;
+ if (!directed) {
+ temp.row = tail - 1;
+ temp.col = head - 1;
+ temp.val = weight;
+ tuple_array[cnt++] = temp;
+ }
+
+#ifdef VERBOSE
+ printf("Adding edge: %d ==> %d ( %d )\n", head, tail, weight);
+#endif
+ break;
+ default:
+ fprintf(stderr, "exiting loop\n");
+ break;
+
+ }
+ lineno++;
+ }
+
+ std::stable_sort(tuple_array, tuple_array + num_edges, doCompare);
+
+#ifdef VERBOSE
+ for (int i = 0 ; i < num_edges; i++) {
+ printf("%d: %d, %d, %d\n", i, tuple_array[i].row, tuple_array[i].col, tuple_array[i].val);
+ }
+#endif
+
+ int *edge_array1 = (int *)malloc(num_edges * sizeof(int));
+ int *edge_array2 = (int *)malloc(num_edges * sizeof(int));
+
+ for (int i = 0; i < num_edges; i++) {
+ edge_array1[i] = tuple_array[i].row;
+ edge_array2[i] = tuple_array[i].col;
+ }
+
+ fclose(fptr);
+ free(tuple_array);
+
+ double_edges *de = (double_edges *)malloc(sizeof(double_edges));
+ de->edge_array1 = edge_array1;
+ de->edge_array2 = edge_array2;
+
+ return de;
+}
+
+// Parse matrix market file
+csr_array *parseMM(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed, bool weight_flag)
+{
+ int cnt = 0;
+ unsigned int lineno = 0;
+ char line[128];
+ int num_nodes = 0, num_edges = 0, num_nodes2 = 0;
+
+ FILE *fptr;
+ CooTuple *tuple_array = NULL;
+
+ fptr = fopen(tmpchar, "r");
+ if (!fptr) {
+ fprintf(stderr, "Error when opening file: %s\n", tmpchar);
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+
+ while (fgets(line, 100, fptr)) {
+ int head, tail, weight;
+ if (line[0] == '%') continue;
+ if (lineno == 0) {
+ sscanf(line, "%d %d %d", p_num_nodes, &num_nodes2, p_num_edges);
+ if (!directed) {
+ *p_num_edges = *p_num_edges * 2;
+ printf("This is an undirected graph\n");
+ } else {
+ printf("This is a directed graph\n");
+ }
+
+ num_nodes = *p_num_nodes;
+ num_edges = *p_num_edges;
+
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", num_nodes, num_edges);
+ tuple_array = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ if (!tuple_array) {
+ printf("tuple array not allocated succesfully\n");
+ exit(1);
+ }
+
+ }
+ if (lineno > 0) {
+
+ if (weight_flag) {
+ sscanf(line, "%d %d %d", &head, &tail, &weight);
+ } else {
+ sscanf(line, "%d %d", &head, &tail);
+ printf("(%d, %d)\n", head, tail);
+ weight = 0;
+ }
+
+ if (tail == head) {
+ printf("reporting self loop\n");
+ continue;
+ };
+
+ CooTuple temp;
+ temp.row = head - 1;
+ temp.col = tail - 1;
+ temp.val = weight;
+ tuple_array[cnt++] = temp;
+
+ if (!directed) {
+ temp.row = tail - 1;
+ temp.col = head - 1;
+ temp.val = weight;
+ tuple_array[cnt++] = temp;
+ }
+
+#ifdef VERBOSE
+ printf("Adding edge: %d ==> %d ( %d )\n", head, tail, weight);
+#endif
+ }
+ lineno++;
+ }
+
+ std::stable_sort(tuple_array, tuple_array + num_edges, doCompare);
+
+#ifdef VERBOSE
+ for (int i = 0 ; i < num_edges; i++) {
+ printf("%d: %d, %d, %d\n", i, tuple_array[i].row, tuple_array[i].col, tuple_array[i].val);
+ }
+#endif
+
+ int *row_array = (int *)malloc((num_nodes + 1) * sizeof(int));
+ int *col_array = (int *)malloc(num_edges * sizeof(int));
+ int *data_array = (int *)malloc(num_edges * sizeof(int));
+
+ int row_cnt = 0;
+ int prev = -1;
+ int idx;
+ for (idx = 0; idx < num_edges; idx++) {
+ int curr = tuple_array[idx].row;
+ if (curr != prev) {
+ row_array[row_cnt++] = idx;
+ prev = curr;
+ }
+
+ col_array[idx] = tuple_array[idx].col;
+ data_array[idx] = tuple_array[idx].val;
+ }
+ row_array[row_cnt] = idx;
+
+ fclose(fptr);
+ free(tuple_array);
+
+ csr_array *csr = (csr_array *)malloc(sizeof(csr_array));
+ memset(csr, 0, sizeof(csr_array));
+ csr->row_array = row_array;
+ csr->col_array = col_array;
+ csr->data_array = data_array;
+
+ return csr;
+}
+
+// Parse Metis file with transpose
+csr_array *parseMetis_transpose(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed)
+{
+ int cnt = 0;
+ unsigned int lineno = 0;
+ char *line = (char *)malloc(8192);
+ int num_edges = 0, num_nodes = 0;
+ int *col_cnt = NULL;
+
+ FILE *fptr;
+ CooTuple *tuple_array = NULL;
+
+ fptr = fopen(tmpchar, "r");
+ if (!fptr) {
+ fprintf(stderr, "Error when opening file: %s\n", tmpchar);
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+ while (fgets(line, 8192, fptr)) {
+ int head, tail, weight = 0;
+ CooTuple temp;
+
+ if (line[0] == '%') continue; // skip comment lines
+
+ if (lineno == 0) { //the first line
+
+ sscanf(line, "%d %d", p_num_nodes, p_num_edges);
+
+ col_cnt = (int *)malloc(*p_num_nodes * sizeof(int));
+ if (!col_cnt) {
+ printf("memory allocation failed for col_cnt\n");
+ exit(1);
+ }
+ memset(col_cnt, 0, *p_num_nodes * sizeof(int));
+
+ if (!directed) {
+ *p_num_edges = *p_num_edges * 2;
+ printf("This is an undirected graph\n");
+ } else {
+ printf("This is a directed graph\n");
+ }
+ num_nodes = *p_num_nodes;
+ num_edges = *p_num_edges;
+
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", num_nodes, num_edges);
+ tuple_array = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ } else if (lineno > 0) { //from the second line
+ char *pch;
+ pch = strtok(line , " ,.-");
+ while (pch != NULL) {
+ head = lineno;
+ tail = atoi(pch);
+ if (tail <= 0) {
+ break;
+ }
+
+ if (tail == head) printf("reporting self loop: %d, %d\n", lineno + 1, lineno);
+
+ if (directed) {
+ temp.row = tail - 1;
+ temp.col = head - 1;
+ } else {
+ // Undirected matrices are symmetric, so there is no need
+ // to transpose and then re-sort the edges
+ temp.row = head - 1;
+ temp.col = tail - 1;
+ }
+ temp.val = weight;
+
+ col_cnt[head - 1]++;
+ if (cnt >= num_edges) {
+ fprintf(stderr, "Error when opening file: %s.\n" \
+ " Check if graph is undirected Metis format\n", tmpchar);
+ exit(1);
+ }
+ tuple_array[cnt++] = temp;
+
+ pch = strtok(NULL, " ,.-");
+ }
+ }
+#ifdef VERBOSE
+ printf("Adding edge: %d ==> %d ( %d )\n", head, tail, weight);
+#endif
+ lineno++;
+ }
+
+ if (directed) {
+ // Metis files are stored in row-order, so transposed, directed
+ // matrices must be re-sorted!
+ std::stable_sort(tuple_array, tuple_array + num_edges, doCompare);
+ }
+
+#ifdef VERBOSE
+ for (int i = 0 ; i < num_edges; i++) {
+ printf("%d: %d, %d, %d\n", i, tuple_array[i].row, tuple_array[i].col, tuple_array[i].val);
+ }
+#endif
+
+ int *row_array = (int *)malloc((num_nodes + 1) * sizeof(int));
+ int *col_array = (int *)malloc(num_edges * sizeof(int));
+ int *data_array = (int *)malloc(num_edges * sizeof(int));
+
+ int row_cnt = 0;
+ int prev = -1;
+ int idx;
+ for (idx = 0; idx < num_edges; idx++) {
+ int curr = tuple_array[idx].row;
+ if (curr != prev) {
+ row_array[row_cnt++] = idx;
+ prev = curr;
+ }
+ col_array[idx] = tuple_array[idx].col;
+ data_array[idx] = tuple_array[idx].val;
+ }
+ row_array[row_cnt] = idx;
+
+ csr_array *csr = (csr_array *)malloc(sizeof(csr_array));
+ memset(csr, 0, sizeof(csr_array));
+ csr->row_array = row_array;
+ csr->col_array = col_array;
+ csr->data_array = data_array;
+ csr->col_cnt = col_cnt;
+
+ fclose(fptr);
+ free(tuple_array);
+
+ return csr;
+}
+
+// Parse COO file with transpose
+csr_array *parseCOO_transpose(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed)
+{
+ int cnt = 0;
+ unsigned int lineno = 0;
+ char line[128], sp[2], a, p;
+ int num_nodes = 0, num_edges = 0;
+
+ FILE *fptr;
+ CooTuple *tuple_array = NULL;
+
+ fptr = fopen(tmpchar, "r");
+ if (!fptr) {
+ fprintf(stderr, "Error when opening file: %s\n", tmpchar);
+ exit(1);
+ }
+
+ printf("Opening file: %s\n", tmpchar);
+
+ while (fgets(line, 100, fptr)) {
+ int head, tail, weight;
+ switch (line[0]) {
+ case 'c':
+ break;
+ case 'p':
+ fflush(stdout);
+
+ sscanf(line, "%c %s %d %d", &p, sp, p_num_nodes, p_num_edges);
+
+ if (!directed) {
+ *p_num_edges = *p_num_edges * 2;
+ printf("This is an undirected graph\n");
+ } else {
+ printf("This is a directed graph\n");
+ }
+
+ num_nodes = *p_num_nodes;
+ num_edges = *p_num_edges;
+
+ printf("Read from file: num_nodes = %d, num_edges = %d\n", num_nodes, num_edges);
+ tuple_array = (CooTuple *)malloc(sizeof(CooTuple) * num_edges);
+ break;
+
+ case 'a':
+ sscanf(line, "%c %d %d %d", &a, &head, &tail, &weight);
+ if (tail == head) printf("reporting self loop\n");
+ CooTuple temp;
+ temp.val = weight;
+ temp.row = tail - 1;
+ temp.col = head - 1;
+ tuple_array[cnt++] = temp;
+ if (!directed) {
+ temp.val = weight;
+ temp.row = tail - 1;
+ temp.col = head - 1;
+ tuple_array[cnt++] = temp;
+ }
+
+#ifdef VERBOSE
+ printf("Adding edge: %d ==> %d ( %d )\n", head, tail, weight);
+#endif
+ break;
+ default:
+ fprintf(stderr, "exiting loop\n");
+ break;
+ }
+ lineno++;
+ }
+
+ std::stable_sort(tuple_array, tuple_array + num_edges, doCompare);
+
+#ifdef VERBOSE
+ for (int i = 0 ; i < num_edges; i++) {
+ printf("%d: %d, %d, %d\n", i, tuple_array[i].row, tuple_array[i].col, tuple_array[i].val);
+ }
+#endif
+
+ int *row_array = (int *)malloc((num_nodes + 1) * sizeof(int));
+ int *col_array = (int *)malloc(num_edges * sizeof(int));
+ int *data_array = (int *)malloc(num_edges * sizeof(int));
+
+ int row_cnt = 0;
+ int prev = -1;
+ int idx;
+ for (idx = 0; idx < num_edges; idx++) {
+ int curr = tuple_array[idx].row;
+ if (curr != prev) {
+ row_array[row_cnt++] = idx;
+ prev = curr;
+ }
+ col_array[idx] = tuple_array[idx].col;
+ data_array[idx] = tuple_array[idx].val;
+ }
+ while (row_cnt <= num_nodes) {
+ row_array[row_cnt++] = idx;
+ }
+
+ csr_array *csr = (csr_array *)malloc(sizeof(csr_array));
+ memset(csr, 0, sizeof(csr_array));
+ csr->row_array = row_array;
+ csr->col_array = col_array;
+ csr->data_array = data_array;
+
+ fclose(fptr);
+ free(tuple_array);
+
+ return csr;
+}
+
diff --git a/src/gpu/pannotia/graph_parser/parse.h b/src/gpu/pannotia/graph_parser/parse.h
new file mode 100644
index 0000000..e6273ac
--- /dev/null
+++ b/src/gpu/pannotia/graph_parser/parse.h
@@ -0,0 +1,114 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include <stdlib.h>
+
+typedef struct csr_arrays_t {
+ int *row_array;
+ int *col_array;
+ int *data_array;
+ int *col_cnt;
+
+ void freeArrays() {
+ if (row_array) {
+ free(row_array);
+ row_array = NULL;
+ }
+ if (col_array) {
+ free(col_array);
+ col_array = NULL;
+ }
+ if (data_array) {
+ free(data_array);
+ data_array = NULL;
+ }
+ if (col_cnt) {
+ free(col_cnt);
+ col_cnt = NULL;
+ }
+ }
+} csr_array;
+
+typedef struct ell_arrays_t {
+ int max_height;
+ int num_nodes;
+ int *col_array;
+ int *data_array;
+ int *col_cnt;
+} ell_array;
+
+typedef struct double_edges_t {
+ int *edge_array1;
+ int *edge_array2;
+} double_edges;
+
+typedef struct cooedgetuple {
+ int row;
+ int col;
+ int val;
+} CooTuple;
+
+csr_array *parseCOO(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed);
+csr_array *parseMetis(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed);
+csr_array *parseMM(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed, bool weight_flag);
+ell_array *csr2ell(csr_array *csr, int num_nodes, int num_edges, int fill);
+
+double_edges *parseCOO_doubleEdge(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed);
+double_edges *parseMetis_doubleEdge(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed);
+
+csr_array *parseCOO_transpose(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed);
+csr_array *parseMetis_transpose(char* tmpchar, int *p_num_nodes, int *p_num_edges, bool directed);
diff --git a/src/gpu/pannotia/graph_parser/util.cpp b/src/gpu/pannotia/graph_parser/util.cpp
new file mode 100644
index 0000000..93105ad
--- /dev/null
+++ b/src/gpu/pannotia/graph_parser/util.cpp
@@ -0,0 +1,67 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include <sys/time.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+double gettime() {
+ struct timeval t;
+ gettimeofday(&t,NULL);
+ return t.tv_sec+t.tv_usec*1e-6;
+}
diff --git a/src/gpu/pannotia/graph_parser/util.h b/src/gpu/pannotia/graph_parser/util.h
new file mode 100644
index 0000000..b05ae2f
--- /dev/null
+++ b/src/gpu/pannotia/graph_parser/util.h
@@ -0,0 +1,58 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+double gettime();
diff --git a/src/gpu/pannotia/mis/Makefile b/src/gpu/pannotia/mis/Makefile
new file mode 100644
index 0000000..6158bac
--- /dev/null
+++ b/src/gpu/pannotia/mis/Makefile
@@ -0,0 +1,11 @@
+default:
+ make -f Makefile.default
+
+clean:
+ make -f Makefile.default clean
+
+gem5-fusion:
+ make -f Makefile.gem5-fusion
+
+clean-gem5-fusion:
+ make -f Makefile.gem5-fusion clean
diff --git a/src/gpu/pannotia/mis/Makefile.default b/src/gpu/pannotia/mis/Makefile.default
new file mode 100644
index 0000000..be38085
--- /dev/null
+++ b/src/gpu/pannotia/mis/Makefile.default
@@ -0,0 +1,20 @@
+EXECUTABLE = mis_hip
+OPTS = -O3
+
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): mis.cpp ../graph_parser/parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) $(OPTS) --amdgpu-target=gfx801,gfx803,gfx906 $(CXXFLAGS) mis.cpp ../graph_parser/parse.cpp ../graph_parser/util.cpp -o $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: mis clean
diff --git a/src/gpu/pannotia/mis/Makefile.gem5-fusion b/src/gpu/pannotia/mis/Makefile.gem5-fusion
new file mode 100644
index 0000000..70ea0ed
--- /dev/null
+++ b/src/gpu/pannotia/mis/Makefile.gem5-fusion
@@ -0,0 +1,26 @@
+EXECUTABLE = mis_hip.gem5
+OPTS = -O3
+
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+# these are needed for m5ops
+# TODO: Need some sort of explicit PATH? Read in?
+GEM5_PATH ?= /nobackup/sinclair/gem5
+CFLAGS += -I$(GEM5_PATH)/include -I../graph_parser
+LDFLAGS += -L$(GEM5_PATH)/util/m5/build/x86/out -lm5
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): mis.cpp ../graph_parser/parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) $(OPTS) --amdgpu-target=gfx801,gfx803 $(CXXFLAGS) mis.cpp ../graph_parser/parse.cpp ../graph_parser/util.cpp -DGEM5_FUSION -o $(BIN_DIR)/$(EXECUTABLE) $(CFLAGS) $(LDFLAGS)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: mis clean
diff --git a/src/gpu/pannotia/mis/README.md b/src/gpu/pannotia/mis/README.md
new file mode 100644
index 0000000..e587055
--- /dev/null
+++ b/src/gpu/pannotia/mis/README.md
@@ -0,0 +1,49 @@
+---
+title: Pannotia MIS Test
+tags:
+ - x86
+ - amdgpu
+layout: default
+permalink: resources/pannotia/mis
+shortdoc: >
+ Resources to build a disk image with the GCN3 Pannotia MIS workload.
+---
+
+Maximal Independent Set (mis) is a graph analytics application that is part of the Pannotia benchmark suite. It is designed to find a maximal subset of vertices in a graph such that no two are adjacent. The provided version is for use with the gpu-compute model of gem5. Thus, it has been ported from the prior CUDA and OpenCL variants to HIP, and validated on a Vega-class AMD GPU.
+
+Compiling MIS, compiling the GCN3_X86/Vega_X86 versions of gem5, and running MIS on gem5 is dependent on the gcn-gpu docker image, `util/dockerfiles/gcn-gpu/Dockerfile` on the [gem5 stable branch](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable).
+
+## Compilation and Running
+
+To compile MIS:
+
+```
+cd src/gpu/pannotia/mis
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu make gem5-fusion
+```
+
+If you use the Makefile.default file instead, the Makefile will generate code designed to run on the real GPU instead. Moreover, note that Makefile.gem5-fusion requires you to set the GEM5_ROOT variable (either on the command line or by modifying the Makefile), because the Pannotia applications have been updated to use [m5ops](https://www.gem5.org/documentation/general_docs/m5ops/). By default, the Makefile builds for gfx801 and gfx803, and is placed in the src/gpu/pannotia/mis/bin folder.
+
+## Compiling GCN3_X86/gem5.opt
+
+MIS is a GPU application, which requires that gem5 is built with the GCN3_X86 (or Vega_X86, although this has been less heavily tested) architecture. The test is run with the GCN3_X86 gem5 variant, compiled using the gcn-gpu docker image:
+
+```
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest scons build/GCN3_X86/gem5.opt -j <num cores>
+```
+
+## Running MIS on GCN3_X86/gem5.opt
+
+# Assuming gem5 and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/mis/bin -c mis.gem5 --options="1k_128k.gr 0"
+```
+
+Note that the datasets from the original Pannotia suite have been uploaded to: <http://dist.gem5.org/dist/develop/datasets/pannotia>. We recommend you start with the 1k_128k.gr input (<http://dist.gem5.org/dist/develop/datasets/pannotia/mis/1k_128k.gr>), as this is the smallest input that can be run with MIS. Note that 1k_128k is not designed for MIS specifically though -- the above link has larger graphs designed to run with MIS that you should consider using for larger experiments.
+
+## Pre-built binary
+
+A pre-built binary will be added soon.
diff --git a/src/gpu/pannotia/mis/kernel.h b/src/gpu/pannotia/mis/kernel.h
new file mode 100644
index 0000000..19d0eae
--- /dev/null
+++ b/src/gpu/pannotia/mis/kernel.h
@@ -0,0 +1,199 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#ifndef KERNEL_H
+#define KERNEL_H
+
+#include "hip/hip_runtime.h"
+
+#define BIGNUM 99999999
+
+/**
+* init kernel
+* @param s_array set array
+* @param c_array status array
+* @param cu_array status update array
+* @param num_nodes number of vertices
+* @param num_edges number of edges
+*/
+__global__ void
+init(int *s_array, int *c_array, int *cu_array, int num_nodes, int num_edges)
+{
+ // Get my workitem id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+ if (tid < num_nodes) {
+ // Set the status array: not processed
+ c_array[tid] = -1;
+ cu_array[tid] = -1;
+ s_array[tid] = 0;
+ }
+}
+
+/**
+* mis1 kernel
+* @param row csr pointer array
+* @param col csr column index array
+* @param node_value node value array
+* @param s_array set array
+* @param c_array node status array
+* @param min_array node value array
+* @param stop node value array
+* @param num_nodes number of vertices
+* @param num_edges number of edges
+*/
+__global__ void
+mis1(int *row, int *col, int *node_value, int *s_array, int *c_array,
+ int *min_array, int *stop, int num_nodes, int num_edges)
+{
+ // Get workitem id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+ if (tid < num_nodes) {
+ // If the vertex is not processed
+ if (c_array[tid] == -1) {
+ *stop = 1;
+ // Get the start and end pointers
+ int start = row[tid];
+ int end;
+ if (tid + 1 < num_nodes) {
+ end = row[tid + 1];
+ } else {
+ end = num_edges;
+ }
+
+ // Navigate the neighbor list and find the min
+ int min = BIGNUM;
+ for (int edge = start; edge < end; edge++) {
+ if (c_array[col[edge]] == -1) {
+ if (node_value[col[edge]] < min) {
+ min = node_value[col[edge]];
+ }
+ }
+ }
+ min_array[tid] = min;
+ }
+ }
+}
+
+/**
+* mis2 kernel
+* @param row csr pointer array
+* @param col csr column index array
+* @param node_value node value array
+* @param s_array set array
+* @param c_array status array
+* @param cu_array status update array
+* @param min_array node value array
+* @param num_nodes number of vertices
+* @param num_edges number of edges
+*/
+__global__ void
+mis2(int *row, int *col, int *node_value, int *s_array, int *c_array,
+ int *cu_array, int *min_array, int num_nodes, int num_edges)
+{
+ // Get my workitem id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ if (node_value[tid] <= min_array[tid] && c_array[tid] == -1) {
+ // -1: Not processed -2: Inactive 2: Independent set
+ // Put the item into the independent set
+ s_array[tid] = 2;
+
+ // Get the start and end pointers
+ int start = row[tid];
+ int end;
+
+ if (tid + 1 < num_nodes) {
+ end = row[tid + 1];
+ } else {
+ end = num_edges;
+ }
+
+ // Set the status to inactive
+ c_array[tid] = -2;
+
+ // Mark all the neighbors inactive
+ for (int edge = start; edge < end; edge++) {
+ if (c_array[col[edge]] == -1) {
+ //use status update array to avoid race
+ cu_array[col[edge]] = -2;
+ }
+ }
+ }
+ }
+}
+
+/**
+* mis3 kernel
+* @param cu_array status update array
+* @param c_array status array
+* @param num_nodes number of vertices
+*/
+__global__ void
+mis3(int *cu_array, int *c_array, int num_nodes)
+{
+ //get my workitem id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ //set the status array
+ if (tid < num_nodes && cu_array[tid] == -2) {
+ c_array[tid] = cu_array[tid];
+ }
+}
+
+#endif // KERNEL_H
diff --git a/src/gpu/pannotia/mis/mis.cpp b/src/gpu/pannotia/mis/mis.cpp
new file mode 100644
index 0000000..a6a04fb
--- /dev/null
+++ b/src/gpu/pannotia/mis/mis.cpp
@@ -0,0 +1,334 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+//#include <sys/time.h>
+#include <algorithm>
+#include "../graph_parser/parse.h"
+#include "../graph_parser/util.h"
+#include "kernel.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+#include <gem5/m5ops.h>
+#endif
+
+#define RANGE 2048
+
+void dump2file(int *adjmatrix, int num_nodes);
+void print_vector(int *vector, int num);
+void print_vectorf(float *vector, int num);
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+
+ int num_nodes;
+ int num_edges;
+ int file_format = 1;
+ bool directed = 0;
+
+ hipError_t err = hipSuccess;
+
+ // Input arguments
+ if (argc == 3) {
+ tmpchar = argv[1]; // Graph inputfile
+ file_format = atoi(argv[2]); // Choose file format
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ srand(7);
+
+ // Allocate the csr array
+ csr_array *csr;
+
+ // Parse the graph into the csr structure
+ if (file_format == 1) {
+ csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
+ } else if (file_format == 0) {
+ csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
+ } else {
+ fprintf(stderr, "reserve for future");
+ exit(1);
+ }
+
+ // Allocate the node value array
+ int *node_value = (int *)malloc(num_nodes * sizeof(int));
+ if (!node_value) fprintf(stderr, "malloc failed node_value\n");
+
+ // Allocate the set array
+ int *s_array = (int *)malloc(num_nodes * sizeof(int));
+ if (!s_array) fprintf(stderr, "malloc failed node_value\n");
+
+ // Randomize the node values
+ for (int i = 0; i < num_nodes; i++) {
+ node_value[i] = rand() % RANGE;
+ }
+
+ // Create device side buffers
+ int *row_d;
+ int *col_d;
+
+ int *c_array_d;
+ int *c_array_u_d;
+ int *s_array_d;
+ int *node_value_d;
+ int *min_array_d;
+ int *stop_d;
+
+ // Allocate the device-side buffers for the graph
+ err = hipMalloc(&row_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_d (size:%d) => %s\n", num_edges , hipGetErrorString(err));
+ return -1;
+ }
+
+ // Termination variable
+ err = hipMalloc(&stop_d, sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc stop_d (size:%d) => %s\n", 1, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Allocate the device-side buffers for mis
+ err = hipMalloc(&min_array_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc min_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&c_array_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc c_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&c_array_u_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc c_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&s_array_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc s_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&node_value_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc node_value_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
+ return -1;
+ }
+
+// double time1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ // Copy data to device-side buffers
+ err = hipMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(node_value_d, node_value, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy feature_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Work dimensions
+ int block_size = 128;
+ int num_blocks = (num_nodes + block_size - 1) / block_size;
+
+ dim3 threads(block_size, 1, 1);
+ dim3 grid(num_blocks, 1, 1);
+
+ // Launch the initialization kernel
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(init), dim3(grid), dim3(threads), 0, 0, s_array_d, c_array_d, c_array_u_d,
+ num_nodes, num_edges);
+ hipDeviceSynchronize();
+ err = hipGetLastError();
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: init kernel (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Termination variable
+ int stop = 1;
+ int iterations = 0;
+ while (stop) {
+ stop = 0;
+
+ // Copy the termination variable to the device
+ err = hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: write stop_d variable (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Launch mis1
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(mis1), dim3(grid), dim3(threads), 0, 0, row_d, col_d, node_value_d, s_array_d,
+ c_array_d, min_array_d, stop_d, num_nodes,
+ num_edges);
+
+ // Launch mis2
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(mis2), dim3(grid), dim3(threads), 0, 0, row_d, col_d, node_value_d, s_array_d,
+ c_array_d, c_array_u_d, min_array_d, num_nodes,
+ num_edges);
+
+ // Launch mis3
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(mis3), dim3(grid), dim3(threads), 0, 0, c_array_u_d, c_array_d, num_nodes);
+
+ // Copy the termination variable back
+ err = hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read stop_d variable (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ iterations++;
+ }
+
+ hipDeviceSynchronize();
+
+ err = hipMemcpy(s_array, s_array_d, num_nodes * sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy s_array_d failed (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+// double time2 = gettime();
+
+ // Print out the timing characterisitics
+ printf("number of iterations: %d\n", iterations);
+// printf("kernel + memcpy time %f ms\n", (time2 - time1) * 1000);
+
+#if 1
+ // Print the set array
+ print_vector(s_array, num_nodes);
+#endif
+
+ // Clean up the host-side arrays
+ free(node_value);
+ free(s_array);
+ csr->freeArrays();
+ free(csr);
+
+ // Clean up the device-side arrays
+ hipFree(row_d);
+ hipFree(col_d);
+ hipFree(c_array_d);
+ hipFree(s_array_d);
+ hipFree(node_value_d);
+ hipFree(min_array_d);
+ hipFree(stop_d);
+
+ return 0;
+}
+
+void print_vector(int *vector, int num)
+{
+
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++) {
+ fprintf(fp, "%d\n", vector[i]);
+ }
+
+ fclose(fp);
+
+}
+
+void print_vectorf(float *vector, int num)
+{
+
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++) {
+ fprintf(fp, "%f\n", vector[i]);
+ }
+
+ fclose(fp);
+
+}
diff --git a/src/gpu/pannotia/pagerank/Makefile b/src/gpu/pannotia/pagerank/Makefile
new file mode 100644
index 0000000..6158bac
--- /dev/null
+++ b/src/gpu/pannotia/pagerank/Makefile
@@ -0,0 +1,11 @@
+default:
+ make -f Makefile.default
+
+clean:
+ make -f Makefile.default clean
+
+gem5-fusion:
+ make -f Makefile.gem5-fusion
+
+clean-gem5-fusion:
+ make -f Makefile.gem5-fusion clean
diff --git a/src/gpu/pannotia/pagerank/Makefile.default b/src/gpu/pannotia/pagerank/Makefile.default
new file mode 100644
index 0000000..486579b
--- /dev/null
+++ b/src/gpu/pannotia/pagerank/Makefile.default
@@ -0,0 +1,28 @@
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+OPTS = -O3
+
+BASEEXE = pagerank
+VARIANT ?= DEFAULT
+ifeq ($(VARIANT),DEFAULT)
+ EXECUTABLE = $(BASEEXE)
+ CPPFILES += pagerank.cpp
+else ifeq ($(VARIANT),SPMV)
+ EXECUTABLE = $(BASEEXE)_spmv
+ CPPFILES += pagerank_spmv.cpp
+endif
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): $(CPPFILES) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) $(OPTS) --amdgpu-target=gfx801,gfx803,gfx906 $(CXXFLAGS) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(CPPFILES) -o $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: pagerank clean
diff --git a/src/gpu/pannotia/pagerank/Makefile.gem5-fusion b/src/gpu/pannotia/pagerank/Makefile.gem5-fusion
new file mode 100644
index 0000000..f3e5f26
--- /dev/null
+++ b/src/gpu/pannotia/pagerank/Makefile.gem5-fusion
@@ -0,0 +1,34 @@
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+OPTS = -O3
+
+# these are needed for m5ops
+# TODO: Need some sort of explicit PATH? Read in?
+GEM5_PATH ?= /nobackup/sinclair/gem5
+CFLAGS += -I$(GEM5_PATH)/include -I/../graph_parser
+LDFLAGS += -L$(GEM5_PATH)/util/m5/build/x86/out -lm5
+
+BASEEXE = pagerank
+VARIANT ?= DEFAULT
+ifeq ($(VARIANT),DEFAULT)
+ EXECUTABLE = $(BASEEXE).gem5
+ CPPFILES += pagerank.cpp
+else ifeq ($(VARIANT),SPMV)
+ EXECUTABLE = $(BASEEXE)_spmv.gem5
+ CPPFILES += pagerank_spmv.cpp
+endif
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): $(CPPFILES) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) $(OPTS) --amdgpu-target=gfx801,gfx803 $(CXXFLAGS) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(CPPFILES) -DGEM5_FUSION -o $(BIN_DIR)/$(EXECUTABLE) $(CFLAGS) $(LDFLAGS)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: pagerank clean
diff --git a/src/gpu/pannotia/pagerank/README.md b/src/gpu/pannotia/pagerank/README.md
new file mode 100644
index 0000000..c3c4f5e
--- /dev/null
+++ b/src/gpu/pannotia/pagerank/README.md
@@ -0,0 +1,66 @@
+---
+title: Pannotia PageRank Test
+tags:
+ - x86
+ - amdgpu
+layout: default
+permalink: resources/pannotia/pagerank
+shortdoc: >
+ Resources to build a disk image with the GCN3 Pannotia PageRank workload.
+---
+
+PageRank (PR) is a graph analytics application that is part of the Pannotia benchmark suite. It is an algorithm designed to calculate probability distributions representing the likelihood that a person randomly clicking on links arrives at any particular page. The provided version is for use with the gpu-compute model of gem5. Thus, it has been ported from the prior CUDA and OpenCL variants to HIP, and validated on a Vega-class AMD GPU.
+
+Compiling both PageRank variants, compiling the GCN3_X86/Vega_X86 versions of gem5, and running both PageRank variants on gem5 is dependent on the gcn-gpu docker image, `util/dockerfiles/gcn-gpu/Dockerfile` on the [gem5 stable branch](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable).
+
+## Compilation and Running
+
+PR has two variants: default and spmv. To compile the "default" variant:
+
+```
+cd src/gpu/pannotia/pagerank
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu make gem5-fusion
+```
+
+To compile the "spmv" variant:
+
+```
+cd src/gpu/pannotia/pagerank
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu bash -c "export VARIANT=SPMV ; make gem5-fusion"
+```
+
+If you use the Makefile.default file instead, the Makefile will generate code designed to run on the real GPU instead. Moreover, note that Makefile.gem5-fusion requires you to set the GEM5_ROOT variable (either on the command line or by modifying the Makefile), because the Pannotia applications have been updated to use [m5ops](https://www.gem5.org/documentation/general_docs/m5ops/). By default, for both variants the Makefile builds for gfx801 and gfx803, and the binaries are placed in the src/gpu/pannotia/pagerank/bin folder. Moreover, by default the VARIANT variable PageRank's Makefile assumes the csr variant is being used, hence why this variable does not need to be set for compiling it.
+
+## Compiling GCN3_X86/gem5.opt
+
+PageRank is a GPU application, which requires that gem5 is built with the GCN3_X86 (or Vega_X86, although this has been less heavily tested) architecture. The test is run with the GCN3_X86 gem5 variant, compiled using the gcn-gpu docker image:
+
+```
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest scons build/GCN3_X86/gem5.opt -j <num cores>
+```
+
+## Running PageRank on GCN3_X86/gem5.opt
+
+The following command shows how to run the PageRank default version:
+
+# Assuming gem5 and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/pagerank/coAuthorsDBLP.graph
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/pagerank/bin -c pagerank.gem5 --options="coAuthorsDBLP.graph 1"
+```
+
+To run the PageRank spmv version:
+
+# Assuming gem5, pannotia (input graphs, see below), and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/pagerank/coAuthorsDBLP.graph
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/pagerank/bin -c pagerank_spmv.gem5 --options="coAuthorsDBLP.graph 1"
+```
+
+Note that the datasets from the original Pannotia suite have been uploaded to: <http://dist.gem5.org/dist/develop/datasets/pannotia>. We recommend you start with the coAuthorsDBLP input for PR.
+
+## Pre-built binary
+
+A pre-built binary will be added soon.
diff --git a/src/gpu/pannotia/pagerank/kernel.h b/src/gpu/pannotia/pagerank/kernel.h
new file mode 100644
index 0000000..f2407aa
--- /dev/null
+++ b/src/gpu/pannotia/pagerank/kernel.h
@@ -0,0 +1,145 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#ifndef KERNEL_H
+#define KERNEL_H
+
+#include "hip/hip_runtime.h"
+
+/**
+ * @brief pagerank 1
+ * @param row csr pointer array
+ * @param col csr column array
+ * @param data weight array
+ * @param page_rank1 pagerank array 1
+ * @param page_rank2 pagerank array 2
+ * @param num_nodes number of vertices
+ * @param num_edges number of edges
+ */
+__global__ void
+pagerank1(int *row, int *col, int *data, float *page_rank1, float *page_rank2,
+ const int num_nodes, const int num_edges)
+{
+ // Get my workitem id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ // Get the starting and ending pointers of the neighborlist
+ int start = row[tid];
+ int end;
+ if (tid + 1 < num_nodes) {
+ end = row[tid + 1];
+ } else {
+ end = num_edges;
+ }
+
+ int nid;
+ // Navigate the neighbor list
+ for (int edge = start; edge < end; edge++) {
+ nid = col[edge];
+ // Transfer the PageRank value to neighbors
+ atomicAdd(&page_rank2[nid], page_rank1[tid] / (float)(end - start));
+ }
+ }
+}
+
+/**
+ * @brief pagerank 2
+ * @param row csr pointer array
+ * @param col csr column array
+ * @param data weight array
+ * @param page_rank1 pagerank array 1
+ * @param page_rank2 pagerank array 2
+ * @param num_nodes number of vertices
+ * @param num_edges number of edges
+ */
+__global__ void
+pagerank2(int *row, int *col, int *data, float *page_rank1, float *page_rank2,
+ const int num_nodes, const int num_edges)
+{
+ // Get my workitem id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ // Update pagerank value with the damping factor
+ if (tid < num_nodes) {
+ page_rank1[tid] = 0.15 / (float)num_nodes + 0.85 * page_rank2[tid];
+ page_rank2[tid] = 0.0f;
+ }
+}
+
+/**
+ * @brief inibuffer
+ * @param row csr pointer array
+ * @param page_rank1 pagerank array 1
+ * @param page_rank2 pagerank array 2
+ * @param num_nodes number of vertices
+ */
+__global__ void
+inibuffer(int *row, float *page_rank1, float *page_rank2, const int num_nodes,
+ const int num_edges)
+{
+ // Get my thread id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ page_rank1[tid] = 1 / (float)num_nodes;
+ page_rank2[tid] = 0.0f;
+ }
+}
+
+#endif // KERNEL_H
diff --git a/src/gpu/pannotia/pagerank/kernel_spmv.h b/src/gpu/pannotia/pagerank/kernel_spmv.h
new file mode 100644
index 0000000..af956c6
--- /dev/null
+++ b/src/gpu/pannotia/pagerank/kernel_spmv.h
@@ -0,0 +1,163 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#ifndef KERNEL_SPMV_H
+#define KERNEL_SPMV_H
+
+#include "hip/hip_runtime.h"
+
+/**
+ * @brief inibuffer
+ * @param page_rank1 PageRank array 1
+ * @param page_rank2 PageRank array 2
+ * @param num_nodes number of vertices
+ */
+__global__ void
+inibuffer(float *page_rank1, float *page_rank2, const int num_nodes)
+{
+ // Get my workitem id
+ int tid = blockDim.x * blockIdx.x + threadIdx.x;
+ // Initialize two pagerank arrays
+ if (tid < num_nodes) {
+ page_rank1[tid] = 1 / (float)num_nodes;
+ page_rank2[tid] = 0.0f;
+ }
+}
+
+/**
+ * @brief inicsr
+ * @param row csr pointer array
+ * @param col csr col array
+ * @param data csr weigh array
+ * @param col_cnt array for #. out-going edges
+ * @param num_nodes number of vertices
+ * @param num_edges number of edges
+ */
+__global__ void
+inicsr(int *row, int *col, float *data, int *col_cnt, int num_nodes,
+ int num_edges)
+{
+ // Get my workitem id
+ int tid = blockDim.x * blockIdx.x + threadIdx.x;
+ if (tid < num_nodes) {
+ // Get the starting and ending pointers
+ int start = row[tid];
+ int end;
+ if (tid + 1 < num_nodes) {
+ end = row[tid + 1] ;
+ } else {
+ end = num_edges;
+ }
+
+ int nid;
+ // Navigate one row of data
+ for (int edge = start; edge < end; edge++) {
+ nid = col[edge];
+ // Each neighbor will get equal amount of pagerank
+ data[edge] = 1.0 / (float)col_cnt[nid];
+ }
+ }
+}
+
+/**
+ * @brief spmv_csr_scalar_kernel (simple spmv)
+ * @param num_nodes number of vertices
+ * @param row csr pointer array
+ * @param col csr col array
+ * @param data csr weigh array
+ * @param x input vector
+ * @param y output vector
+ */
+__global__ void
+spmv_csr_scalar_kernel(const int num_nodes, int *row, int *col, float *data,
+ float *x, float *y)
+{
+ // Get my workitem id
+ int tid = blockDim.x * blockIdx.x + threadIdx.x;
+ if (tid < num_nodes) {
+ // Get the start and end pointers
+ int row_start = row[tid];
+ int row_end = row[tid + 1];
+ float sum = 0;
+ //navigate one row and sum all the elements
+ for (int j = row_start; j < row_end; j++) {
+ sum += data[j] * x[col[j]];
+ }
+ y[tid] += sum;
+ }
+}
+
+/**
+ * @brief pagerank2
+ * @param page_rank1 PageRank array 1
+ * @param page_rank2 PageRank array 2
+ * @param num_nodes number of vertices
+ */
+__global__ void
+pagerank2(float *page_rank1, float *page_rank2, const int num_nodes)
+{
+ // Get my workitem id
+ int tid = blockDim.x * blockIdx.x + threadIdx.x;
+ // Update pagerank value with damping factor
+ if (tid < num_nodes) {
+ page_rank1[tid] = 0.15f / (float)num_nodes + 0.85f * page_rank2[tid];
+ page_rank2[tid] = 0.0f;
+ }
+}
+
+#endif // KERNEL_SPMV_H
diff --git a/src/gpu/pannotia/pagerank/pagerank.cpp b/src/gpu/pannotia/pagerank/pagerank.cpp
new file mode 100644
index 0000000..3d88882
--- /dev/null
+++ b/src/gpu/pannotia/pagerank/pagerank.cpp
@@ -0,0 +1,263 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+//#include <sys/time.h>
+#include "../graph_parser/parse.h"
+#include "../graph_parser/util.h"
+#include "kernel.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+#include <gem5/m5ops.h>
+#endif
+
+// Iteration count
+#define ITER 20
+
+void print_vectorf(float *vector, int num);
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+
+ int num_nodes;
+ int num_edges;
+ int file_format = 1;
+ bool directed = 0;
+
+ hipError_t err = hipSuccess;
+
+ if (argc == 3) {
+ tmpchar = argv[1]; // Graph inputfile
+ file_format = atoi(argv[2]); // File format
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ // Allocate the csr structure
+ csr_array *csr;
+
+ // Parse graph files into csr structure
+ if (file_format == 1) {
+ // Metis
+ csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
+ } else if (file_format == 0) {
+ // Dimacs9
+ csr = parseCOO(tmpchar, &num_nodes, &num_edges, 1);
+ } else if (file_format == 2) {
+ // Matrix market
+ csr = parseMM(tmpchar, &num_nodes, &num_edges, directed, 0);
+ } else {
+ printf("reserve for future");
+ exit(1);
+ }
+
+ // Allocate rank_array
+ float *rank_array = (float *)malloc(num_nodes * sizeof(float));
+ if (!rank_array) {
+ fprintf(stderr, "rank array not allocated successfully\n");
+ return -1;
+ }
+
+ int *row_d;
+ int *col_d;
+ int *data_d;
+
+ float *pagerank1_d;
+ float *pagerank2_d;
+
+ // Create device-side buffers for the graph
+ err = hipMalloc(&row_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_d (size:%d) => %s\n", num_edges, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&data_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc data_d (size:%d) => %s\n", num_edges, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Create buffers for pagerank
+ err = hipMalloc(&pagerank1_d, num_nodes * sizeof(float));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc pagerank1_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&pagerank2_d, num_nodes * sizeof(float));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc pagerank2_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+// double timer1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ // Copy the data to the device-side buffers
+ err = hipMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR:#endif hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Set up work dimensions
+ int block_size = 256;
+ int num_blocks = (num_nodes + block_size - 1) / block_size;
+
+ dim3 threads(block_size, 1, 1);
+ dim3 grid(num_blocks, 1, 1);
+
+// double timer3 = gettime();
+
+ // Launch the initialization kernel
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(inibuffer), dim3(grid), dim3(threads), 0, 0, row_d, pagerank1_d, pagerank2_d, num_nodes,
+ num_edges);
+ hipDeviceSynchronize();
+ err = hipGetLastError();
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: cudaLaunch failed (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Run PageRank for some iter. TO: convergence determination
+ for (int i = 0; i < ITER; i++) {
+ // Launch pagerank kernel 1
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(pagerank1), dim3(grid), dim3(threads), 0, 0, row_d, col_d, data_d, pagerank1_d,
+ pagerank2_d, num_nodes, num_edges);
+
+ // Launch pagerank kernel 2
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(pagerank2), dim3(grid), dim3(threads), 0, 0, row_d, col_d, data_d, pagerank1_d,
+ pagerank2_d, num_nodes, num_edges);
+ }
+ hipDeviceSynchronize();
+
+// double timer4 = gettime();
+
+ // Copy the rank buffer back
+ err = hipMemcpy(rank_array, pagerank1_d, num_nodes * sizeof(float), hipMemcpyDeviceToHost);
+
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy() failed (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+// double timer2 = gettime();
+
+ // Report timing characteristics
+// printf("kernel time = %lf ms\n", (timer4 - timer3) * 1000);
+// printf("kernel + memcpy time = %lf ms\n", (timer2 - timer1) * 1000);
+
+#if 1
+ // Print rank array
+ print_vectorf(rank_array, num_nodes);
+#endif
+
+ // Free the host-side arrays
+ free(rank_array);
+ csr->freeArrays();
+ free(csr);
+
+ // Free the device buffers
+ hipFree(row_d);
+ hipFree(col_d);
+ hipFree(data_d);
+
+ hipFree(pagerank1_d);
+ hipFree(pagerank2_d);
+
+ return 0;
+
+}
+
+void print_vectorf(float *vector, int num)
+{
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++) {
+ fprintf(fp, "%f\n", vector[i]);
+ }
+
+ fclose(fp);
+}
+
diff --git a/src/gpu/pannotia/pagerank/pagerank_spmv.cpp b/src/gpu/pannotia/pagerank/pagerank_spmv.cpp
new file mode 100644
index 0000000..4f650c6
--- /dev/null
+++ b/src/gpu/pannotia/pagerank/pagerank_spmv.cpp
@@ -0,0 +1,278 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+#include "../graph_parser/parse.h"
+#include "../graph_parser/util.h"
+#include "kernel_spmv.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+#include <gem5/m5ops.h>
+#endif
+
+// Iteration count
+#define ITER 20
+
+void print_vectorf(float *vector, int num);
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+
+ int num_nodes;
+ int num_edges;
+ int file_format = 1;
+ bool directed = 0;
+
+ hipError_t err = hipSuccess;
+
+ if (argc == 3) {
+ tmpchar = argv[1]; // Graph inputfile
+ file_format = atoi(argv[2]);
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ // Allocate the csr structure
+ csr_array *csr;
+
+ // Parse graph files into csr structure
+ if (file_format == 1) {
+ csr = parseMetis_transpose(tmpchar, &num_nodes, &num_edges, directed);
+ } else if (file_format == 0) {
+ csr = parseCOO_transpose(tmpchar, &num_nodes, &num_edges, directed);
+ } else {
+ printf("reserve for future");
+ exit(1);
+ }
+
+ // Allocate rank_arrays
+ float *pagerank_array = (float *)malloc(num_nodes * sizeof(float));
+ if (!pagerank_array) fprintf(stderr, "malloc failed page_rank_array\n");
+ float *pagerank_array2 = (float *)malloc(num_nodes * sizeof(float));
+ if (!pagerank_array2) fprintf(stderr, "malloc failed page_rank_array2\n");
+
+ int *row_d;
+ int *col_d;
+ float *data_d;
+
+ float *pagerank1_d;
+ float *pagerank2_d;
+ int *col_cnt_d;
+
+ // Create device-side buffers for the graph
+ err = hipMalloc(&row_d, (num_nodes + 1) * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_d (size:%d) => %s\n", num_edges, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&data_d, num_edges * sizeof(float));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc data_d (size:%d) => %s\n", num_edges, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Create buffers for pagerank
+ err = hipMalloc(&pagerank1_d, num_nodes * sizeof(float));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc pagerank1_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&pagerank2_d, num_nodes * sizeof(float));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc pagerank2_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_cnt_d, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_cnt_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ double timer1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ // Copy the data to the device-side buffers
+ err = hipMemcpy(row_d, csr->row_array, (num_nodes + 1) * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR:#endif hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_cnt_d, csr->col_cnt, num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_cnt_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Set up work dimensions
+ int block_size = 64;
+ int num_blocks = (num_nodes + block_size - 1) / block_size;
+
+ dim3 threads(block_size, 1, 1);
+ dim3 grid(num_blocks, 1, 1);
+
+ double timer3 = gettime();
+
+ // Launch the initialization kernel
+ hipLaunchKernelGGL(inibuffer, dim3(grid), dim3(threads), 0, 0, pagerank1_d, pagerank2_d, num_nodes);
+ hipDeviceSynchronize();
+ err = hipGetLastError();
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipLaunchByPtr failed (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Initialize the CSR
+ hipLaunchKernelGGL(inicsr, dim3(grid), dim3(threads), 0, 0, row_d, col_d, data_d, col_cnt_d, num_nodes,
+ num_edges);
+ hipDeviceSynchronize();
+ err = hipGetLastError();
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipLaunchByPtr failed (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Run PageRank for some iter. TO: convergence determination
+ for (int i = 0; i < ITER; i++) {
+ // Launch pagerank kernel 1
+ hipLaunchKernelGGL(spmv_csr_scalar_kernel, dim3(grid), dim3(threads), 0, 0, num_nodes, row_d, col_d,
+ data_d, pagerank1_d,
+ pagerank2_d);
+
+ // Launch pagerank kernel 2
+ hipLaunchKernelGGL(pagerank2, dim3(grid), dim3(threads), 0, 0, pagerank1_d, pagerank2_d, num_nodes);
+ }
+ hipDeviceSynchronize();
+
+ double timer4 = gettime();
+
+ // Copy the rank buffer back
+ err = hipMemcpy(pagerank_array, pagerank1_d, num_nodes * sizeof(float), hipMemcpyDeviceToHost);
+
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy() failed (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+ double timer2 = gettime();
+
+ // Report timing characteristics
+ printf("kernel time = %lf ms\n", (timer4 - timer3) * 1000);
+ printf("kernel + memcpy time = %lf ms\n", (timer2 - timer1) * 1000);
+
+#if 1
+ // Print rank array
+ print_vectorf(pagerank_array, num_nodes);
+#endif
+
+ // Free the host-side arrays
+ free(pagerank_array);
+ free(pagerank_array2);
+ csr->freeArrays();
+ free(csr);
+
+ // Free the device buffers
+ hipFree(row_d);
+ hipFree(col_d);
+ hipFree(data_d);
+
+ hipFree(pagerank1_d);
+ hipFree(pagerank2_d);
+
+ return 0;
+}
+
+void print_vectorf(float *vector, int num)
+{
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++) {
+ fprintf(fp, "%f\n", vector[i]);
+ }
+
+ fclose(fp);
+}
+
diff --git a/src/gpu/pannotia/sssp/Makefile b/src/gpu/pannotia/sssp/Makefile
new file mode 100644
index 0000000..6158bac
--- /dev/null
+++ b/src/gpu/pannotia/sssp/Makefile
@@ -0,0 +1,11 @@
+default:
+ make -f Makefile.default
+
+clean:
+ make -f Makefile.default clean
+
+gem5-fusion:
+ make -f Makefile.gem5-fusion
+
+clean-gem5-fusion:
+ make -f Makefile.gem5-fusion clean
diff --git a/src/gpu/pannotia/sssp/Makefile.default b/src/gpu/pannotia/sssp/Makefile.default
new file mode 100644
index 0000000..6096b52
--- /dev/null
+++ b/src/gpu/pannotia/sssp/Makefile.default
@@ -0,0 +1,29 @@
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+BASEEXE = sssp
+VARIANT ?= CSR
+ifeq ($(VARIANT),CSR)
+ EXECUTABLE = $(BASEEXE)
+ CPPFILES += sssp_csr.cpp
+else ifeq ($(VARIANT),ELL)
+ EXECUTABLE = $(BASEEXE)_ell
+ CPPFILES += sssp_ell.cpp
+endif
+
+OPTS = -O3
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): $(CPPFILES) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) -O3 --amdgpu-target=gfx801,gfx803,gfx906 $(CXXFLAGS) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(CPPFILES) -o $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: sssp clean
diff --git a/src/gpu/pannotia/sssp/Makefile.gem5-fusion b/src/gpu/pannotia/sssp/Makefile.gem5-fusion
new file mode 100644
index 0000000..05b8167
--- /dev/null
+++ b/src/gpu/pannotia/sssp/Makefile.gem5-fusion
@@ -0,0 +1,35 @@
+HIP_PATH ?= /opt/rocm/hip
+HIPCC = $(HIP_PATH)/bin/hipcc
+
+# these are needed for m5ops
+# TODO: Need some sort of explicit PATH? Read in?
+GEM5_PATH ?= /nobackup/sinclair/gem5
+CFLAGS += -I$(GEM5_PATH)/include -I../graph_parser
+LDFLAGS += -L$(GEM5_PATH)/util/m5/build/x86/out -lm5
+
+BASEEXE = sssp
+VARIANT ?= CSR
+ifeq ($(VARIANT),CSR)
+ EXECUTABLE = $(BASEEXE).gem5
+ CPPFILES += sssp_csr.cpp
+else ifeq ($(VARIANT),ELL)
+ EXECUTABLE = $(BASEEXE)_ell.gem5
+ CPPFILES += sssp_ell.cpp
+endif
+
+OPTS = -O3
+
+BIN_DIR ?= ./bin
+
+all: $(BIN_DIR)/$(EXECUTABLE)
+
+$(BIN_DIR)/$(EXECUTABLE): $(CPPFILES) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(BIN_DIR)
+ $(HIPCC) -O3 --amdgpu-target=gfx801,gfx803 $(CXXFLAGS) ../graph_parser/parse.cpp ../graph_parser/util.cpp $(CPPFILES) -DGEM5_FUSION -o $(BIN_DIR)/$(EXECUTABLE) $(CFLAGS) $(LDFLAGS)
+
+$(BIN_DIR):
+ mkdir -p $(BIN_DIR)
+
+clean:
+ rm -rf $(BIN_DIR)
+
+.PHONY: sssp clean
diff --git a/src/gpu/pannotia/sssp/README.md b/src/gpu/pannotia/sssp/README.md
new file mode 100644
index 0000000..43cfe0a
--- /dev/null
+++ b/src/gpu/pannotia/sssp/README.md
@@ -0,0 +1,66 @@
+---
+title: Pannotia SSSP Test
+tags:
+ - x86
+ - amdgpu
+layout: default
+permalink: resources/pannotia/sssp
+shortdoc: >
+ Resources to build a disk image with the GCN3 Pannotia SSSP workload.
+---
+
+Single-Source Shortest Path (sssp) is a graph analytics application that is part of the Pannotia benchmark suite. It is designed to calculate the shortest paths between the source vertex and all the other vertices in a graph. The provided version is for use with the gpu-compute model of gem5. Thus, it has been ported from the prior CUDA and OpenCL variants to HIP, and validated on a Vega-class AMD GPU.
+
+Compiling both SSSP variants, compiling the GCN3_X86/Vega_X86 versions of gem5, and running both SSSP variants on gem5 is dependent on the gcn-gpu docker image, `util/dockerfiles/gcn-gpu/Dockerfile` on the [gem5 stable branch](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable).
+
+## Compilation and Running
+
+SSSP has two variants: csr and ell. To compile the "csr" variant:
+
+```
+cd src/gpu/pannotia/sssp
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu make gem5-fusion
+```
+
+To compile the "ell" variant:
+
+```
+cd src/gpu/pannotia/sssp
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu bash -c "export VARIANT=ELL ; make gem5-fusion"
+```
+
+If you use the Makefile.default file instead, the Makefile will generate code designed to run on the real GPU instead. Moreover, note that Makefile.gem5-fusion requires you to set the GEM5_ROOT variable (either on the command line or by modifying the Makefile), because the Pannotia applications have been updated to use [m5ops](https://www.gem5.org/documentation/general_docs/m5ops/). By default, for both variants the Makefile builds for gfx801 and gfx803, and the binaries are placed in the src/gpu/pannotia/sssp/bin folder. Moreover, by default the VARIANT variable SSSP's Makefile assumes the csr variant is being used, hence why this variable does not need to be set for compiling it.
+
+## Compiling GCN3_X86/gem5.opt
+
+SSSP is a GPU application, which requires that gem5 is built with the GCN3_X86 (or Vega_X86, although this has been less heavily tested) architecture. The test is run with the GCN3_X86 gem5 variant, compiled using the gcn-gpu docker image:
+
+```
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest scons build/GCN3_X86/gem5.opt -j <num cores>
+```
+
+## Running SSSP on GCN3_X86/gem5.opt
+
+The following command shows how to run the SSSP csr version:
+
+# Assuming gem5 and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/sssp/bin -c sssp_csr.gem5 --options="1k_128k.gr 0"
+```
+
+To run the SSSP ell version:
+
+# Assuming gem5, pannotia (input graphs, see below), and gem5-resources are in your working directory
+```
+wget http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr
+docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n3 --mem-size=8GB --benchmark-root=gem5-resources/src/gpu/pannotia/sssp/bin -c sssp_ell.gem5 --options="1k_128k.gr 0"
+```
+
+Note that the datasets from the original Pannotia suite have been uploaded to: <http://dist.gem5.org/dist/develop/datasets/pannotia>. We recommend you start with the 1k_128k.gr input (<http://dist.gem5.org/dist/develop/datasets/pannotia/bc/1k_128k.gr>), as this is the smallest input that can be run with SSSP. Note that 1k_128k is not designed for SSSP specifically though -- the above link has larger graphs designed to run with SSSP that you should consider using for larger experiments.
+
+## Pre-built binary
+
+A pre-built binary will be added soon.
diff --git a/src/gpu/pannotia/sssp/kernel.h b/src/gpu/pannotia/sssp/kernel.h
new file mode 100644
index 0000000..e56140e
--- /dev/null
+++ b/src/gpu/pannotia/sssp/kernel.h
@@ -0,0 +1,190 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#ifndef KERNEL_H
+#define KERNEL_H
+
+#include "hip/hip_runtime.h"
+#define BIG_NUM 99999999
+
+/**
+ * @brief min.+
+ * @param num_nodes Number of vertices
+ * @param row CSR pointer array
+ * @param col CSR column array
+ * @param data Weight array
+ * @param x Input vector
+ * @param y Output vector
+ */
+__global__ void
+spmv_min_dot_plus_kernel(const int num_rows, int *row, int *col, int *data,
+ int *x, int *y)
+{
+ // Get my workitem id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ if (tid < num_rows) {
+ // Get the start and end pointers
+ int row_start = row[tid];
+ int row_end = row[tid + 1];
+
+ // Perform + for each pair of elements and a reduction with min
+ int min = x[tid];
+ for (int i = row_start; i < row_end; i++) {
+ if (data[i] + x[col[i]] < min) {
+ min = data[i] + x[col[i]];
+ }
+ }
+ y[tid] = min;
+ }
+}
+
+/**
+ * @brief min.+
+ * @param num_nodes number of vertices
+ * @param height the height of the adjacency matrix (col-major)
+ * @param col the col array
+ * @param data the data array
+ * @param x the input vector
+ * @param y the output vector
+ */
+__global__ void
+ell_min_dot_plus_kernel(const int num_nodes, const int height, int *col,
+ int *data, int *x, int *y)
+{
+ // Get workitem id
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ int mat_offset = tid;
+ int min = x[tid];
+
+ // The vertices process a row of matrix (col-major)
+ for (int i = 0; i < height; i++) {
+ int mat_elem = data[mat_offset];
+ int vec_elem = x[col[mat_offset]];
+ if (mat_elem + vec_elem < min) {
+ min = mat_elem + vec_elem;
+ }
+ mat_offset += num_nodes;
+ }
+ y[tid] = min;
+ }
+}
+
+/**
+ * @brief vector_init
+ * @param vector1 vector1
+ * @param vector2 vector2
+ * @param i source vertex id
+ * @param num_nodes number of vertices
+ */
+__global__ void
+vector_init(int *vector1, int *vector2, const int i, const int num_nodes)
+{
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ if (tid == i) {
+ // If it is the source vertex
+ vector1[tid] = 0;
+ vector2[tid] = 0;
+ } else {
+ // If it a non-source vertex
+ vector1[tid] = BIG_NUM;
+ vector2[tid] = BIG_NUM;
+ }
+ }
+}
+
+/**
+ * @brief vector_assign
+ * @param vector1 vector1
+ * @param vector2 vector2
+ * @param num_nodes number of vertices
+ */
+__global__ void
+vector_assign(int *vector1, int *vector2, const int num_nodes)
+{
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ vector1[tid] = vector2[tid];
+ }
+}
+
+/**
+ * @brief vector_diff
+ * @param vector1 vector1
+ * @param vector2 vector2
+ * @param stop termination variable
+ * @param num_nodes number of vertices
+ */
+__global__ void
+vector_diff(int *vector1, int *vector2, int *stop, const int num_nodes)
+{
+ int tid = hipBlockDim_x * hipBlockIdx_x + hipThreadIdx_x;
+
+ if (tid < num_nodes) {
+ if (vector2[tid] != vector1[tid]) {
+ *stop = 1;
+ }
+ }
+}
+
+#endif // KERNEL_H
diff --git a/src/gpu/pannotia/sssp/sssp_csr.cpp b/src/gpu/pannotia/sssp/sssp_csr.cpp
new file mode 100644
index 0000000..f971d17
--- /dev/null
+++ b/src/gpu/pannotia/sssp/sssp_csr.cpp
@@ -0,0 +1,300 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+//#include <sys/time.h>
+#include <algorithm>
+#include "../graph_parser/parse.h"
+#include "../graph_parser/util.h"
+#include "kernel.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+#include <gem5/m5ops.h>
+#endif
+
+void print_vector(int *vector, int num);
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+ bool directed = 1;
+
+ int num_nodes;
+ int num_edges;
+ int file_format = 1;
+
+ hipError_t err = hipSuccess;
+
+ if (argc == 3) {
+ tmpchar = argv[1]; // Graph inputfile
+ file_format = atoi(argv[2]);
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ // Allocate the csr structure
+ csr_array *csr;
+
+ // Parse the graph and store it into the CSR structure
+ if (file_format == 1) {
+ csr = parseMetis_transpose(tmpchar, &num_nodes, &num_edges, directed);
+ } else if (file_format == 0) {
+ csr = parseCOO_transpose(tmpchar, &num_nodes, &num_edges, directed);
+ } else {
+ printf("reserve for future");
+ exit(1);
+ }
+
+ // Allocate the cost array
+ int *cost_array = (int *)malloc(num_nodes * sizeof(int));
+ if (!cost_array) fprintf(stderr, "malloc failed cost_array\n");
+
+ // Set the cost array to zero
+ for (int i = 0; i < num_nodes; i++) {
+ cost_array[i] = 0;
+ }
+
+ // Create device-side buffers
+ int *row_d;
+ int *col_d;
+ int *data_d;
+ int *vector_d1;
+ int *vector_d2;
+ int *stop_d;
+
+ // Create the device-side graph structure
+ err = hipMalloc(&row_d, (num_nodes + 1) * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&col_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc col_d (size:%d) => %s\n", num_edges, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&data_d, num_edges * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc data_d (size:%d) => %s\n", num_edges, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Termination variable
+ err = hipMalloc(&stop_d, sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc stop_d (size:%d) => %s\n", 1, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Create the device-side buffers for sssp
+ err = hipMalloc(&vector_d1, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc vector_d1 (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&vector_d2, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc vector_d2 (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ //double timer1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ // Copy data to device side buffers
+ err = hipMemcpy(row_d, csr->row_array, (num_nodes + 1) * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(data_d, csr->data_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy data_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ //double timer3 = gettime();
+
+ // Work dimensions
+ int block_size = 64;
+ int num_blocks = (num_nodes + block_size - 1) / block_size;
+
+ dim3 threads(block_size, 1, 1);
+ dim3 grid(num_blocks, 1, 1);
+
+ // Source vertex 0
+ int sourceVertex = 0;
+
+ // Launch the initialization kernel
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(vector_init), dim3(grid), dim3(threads), 0, 0, vector_d1, vector_d2, sourceVertex, num_nodes);
+ hipDeviceSynchronize();
+ err = hipGetLastError();
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: vector_init failed (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ int stop = 1;
+ int cnt = 0;
+ // Main computation loop
+ for (int i = 1; i < num_nodes; i++) {
+ // Reset the termination variable
+ stop = 0;
+
+ // Copy the termination variable to the device
+ err = hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: write stop_d (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Launch the assignment kernel
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(vector_assign), dim3(grid), dim3(threads), 0, 0, vector_d1, vector_d2, num_nodes);
+
+ // Launch the min.+ kernel
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(spmv_min_dot_plus_kernel), dim3(grid), dim3(threads), 0, 0, num_nodes, row_d, col_d,
+ data_d, vector_d1,
+ vector_d2);
+
+ // Launch the check kernel
+ hipLaunchKernelGGL(HIP_KERNEL_NAME(vector_diff), dim3(grid), dim3(threads), 0, 0, vector_d1, vector_d2,
+ stop_d, num_nodes);
+
+ // Read the termination variable back
+ err = hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read stop_d (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Exit the loop
+ if (stop == 0) {
+ break;
+ }
+ cnt++;
+ }
+ hipDeviceSynchronize();
+ //double timer4 = gettime();
+
+ // Read the cost_array back
+ err = hipMemcpy(cost_array, vector_d1, num_nodes * sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read vector_d1 (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+ //double timer2 = gettime();
+
+ // Print the timing statistics
+ //printf("kernel + memcpy time = %lf ms\n", (timer2 - timer1) * 1000);
+ //printf("kernel time = %lf ms\n", (timer4 - timer3) * 1000);
+ printf("number iterations = %d\n", cnt);
+
+#if 1
+ // Print cost_array
+ print_vector(cost_array, num_nodes);
+#endif
+
+ // Clean up the host arrays
+ free(cost_array);
+ csr->freeArrays();
+ free(csr);
+
+ // Clean up the device-side buffers
+ hipFree(row_d);
+ hipFree(col_d);
+ hipFree(data_d);
+ hipFree(stop_d);
+ hipFree(vector_d1);
+ hipFree(vector_d2);
+
+ return 0;
+}
+
+void print_vector(int *vector, int num)
+{
+
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++)
+ fprintf(fp, "%d: %d\n", i + 1, vector[i]);
+
+ fclose(fp);
+}
diff --git a/src/gpu/pannotia/sssp/sssp_ell.cpp b/src/gpu/pannotia/sssp/sssp_ell.cpp
new file mode 100644
index 0000000..a621b17
--- /dev/null
+++ b/src/gpu/pannotia/sssp/sssp_ell.cpp
@@ -0,0 +1,300 @@
+/************************************************************************************\
+ * *
+ * Copyright � 2014 Advanced Micro Devices, Inc. *
+ * Copyright (c) 2015 Mark D. Hill and David A. Wood *
+ * Copyright (c) 2021 Gaurav Jain and Matthew D. Sinclair *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or without *
+ * modification, are permitted provided that the following are met: *
+ * *
+ * You must reproduce the above copyright notice. *
+ * *
+ * Neither the name of the copyright holder nor the names of its contributors *
+ * may be used to endorse or promote products derived from this software *
+ * without specific, prior, written permission from at least the copyright holder. *
+ * *
+ * You must include the following terms in your license and/or other materials *
+ * provided with the software. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
+ * OF SUCH DAMAGE. *
+ * *
+ * Without limiting the foregoing, the software may implement third party *
+ * technologies for which you must obtain licenses from parties other than AMD. *
+ * You agree that AMD has not obtained or conveyed to you, and that you shall *
+ * be responsible for obtaining the rights to use and/or distribute the applicable *
+ * underlying intellectual property rights related to the third party technologies. *
+ * These third party technologies are not licensed hereunder. *
+ * *
+ * If you use the software (in whole or in part), you shall adhere to all *
+ * applicable U.S., European, and other export laws, including but not limited to *
+ * the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
+ * and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
+ * to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
+ * license granted by the United States Department of Commerce Bureau of Industry *
+ * and Security or as otherwise permitted pursuant to a License Exception under *
+ * the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
+ * re-export or release to a national of a country in Country Groups D:1, E:1 or *
+ * E:2 any restricted technology, software, or source code you receive hereunder, *
+ * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
+ * technology or software, if such foreign produced direct product is subject to *
+ * national security controls as identified on the Commerce Control List (currently *
+ * found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
+ * listings, or for additional information about the EAR or your obligations under *
+ * those regulations, please refer to the U.S. Bureau of Industry and Security's *
+ * website at http://www.bis.doc.gov/. *
+ * *
+\************************************************************************************/
+
+#include "hip/hip_runtime.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+#include <algorithm>
+#include "../graph_parser/parse.h"
+#include "../graph_parser/util.h"
+#include "kernel.h"
+
+#ifdef GEM5_FUSION
+#include <stdint.h>
+extern "C" {
+void m5_work_begin(uint64_t workid, uint64_t threadid);
+void m5_work_end(uint64_t workid, uint64_t threadid);
+}
+#endif
+
+#define BIGNUM 99999999
+
+void print_vector(int *vector, int num);
+
+int main(int argc, char **argv)
+{
+ char *tmpchar;
+ bool directed = 1;
+
+ int num_nodes;
+ int num_edges;
+ int file_format = 1;
+
+ hipError_t err = hipSuccess;
+
+ if (argc == 3) {
+ tmpchar = argv[1]; // Graph inputfile
+ file_format = atoi(argv[2]);
+ } else {
+ fprintf(stderr, "You did something wrong!\n");
+ exit(1);
+ }
+
+ // Allocate the csr structure
+ csr_array *csr;
+
+ // Parse the graph and store it into the CSR structure
+ if (file_format == 1) {
+ csr = parseMetis_transpose(tmpchar, &num_nodes, &num_edges, directed);
+ } else if (file_format == 0) {
+ csr = parseCOO_transpose(tmpchar, &num_nodes, &num_edges, directed);
+ } else {
+ printf("reserve for future");
+ exit(1);
+ }
+
+ // Allocate ell and transform from csr
+ ell_array *ell = csr2ell(csr, num_nodes, num_edges, BIGNUM);
+ int height = ell->max_height;
+
+ // Allocate the cost array
+ int *cost_array = (int *)malloc(num_nodes * sizeof(int));
+ if (!cost_array) fprintf(stderr, "malloc failed cost_array\n");
+
+ // Set the cost array to zero
+ for (int i = 0; i < num_nodes; i++) {
+ cost_array[i] = 0;
+ }
+
+ // Create device-side buffers
+ int *ell_col_d;
+ int *ell_data_d;
+ int *vector_d1;
+ int *vector_d2;
+ int *stop_d;
+
+ // Create the device-side graph structure
+ err = hipMalloc(&ell_col_d, height * num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc ell_col_d (size:%d) => %s\n", height * num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&ell_data_d, height * num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc ell_data_d (size:%d) => %s\n", height * num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Termination variable
+ err = hipMalloc(&stop_d, sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc stop_d (size:%d) => %s\n", 1, hipGetErrorString(err));
+ return -1;
+ }
+
+ // Create the device-side buffers for sssp
+ err = hipMalloc(&vector_d1, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc vector_d1 (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+ err = hipMalloc(&vector_d2, num_nodes * sizeof(int));
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMalloc vector_d2 (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ double timer1 = gettime();
+
+#ifdef GEM5_FUSION
+ m5_work_begin(0, 0);
+#endif
+
+ // Copy data to device side buffers
+ err = hipMemcpy(ell_col_d, ell->col_array, height * num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy ell_col_d (size:%d) => %s\n", height * num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ err = hipMemcpy(ell_data_d, ell->data_array, height * num_nodes * sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: hipMemcpy ell_data_d (size:%d) => %s\n", height * num_nodes, hipGetErrorString(err));
+ return -1;
+ }
+
+ double timer3 = gettime();
+
+ // Work dimensions
+ int block_size = 64;
+ int num_blocks = (num_nodes + block_size - 1) / block_size;
+
+ dim3 threads(block_size, 1, 1);
+ dim3 grid(num_blocks, 1, 1);
+
+ // Source vertex 0
+ int sourceVertex = 0;
+
+ // Launch the initialization kernel
+ hipLaunchKernelGGL(vector_init, dim3(grid), dim3(threads), 0, 0, vector_d1, vector_d2, sourceVertex, num_nodes);
+ hipDeviceSynchronize();
+ err = hipGetLastError();
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: vector_init failed (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ int stop = 1;
+ int cnt = 0;
+ // Main computation loop
+ for (int i = 1; i < num_nodes; i++) {
+ // Reset the termination variable
+ stop = 0;
+
+ // Copy the termination variable to the device
+ err = hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: write stop_d (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Launch the assignment kernel
+ hipLaunchKernelGGL(vector_assign, dim3(grid), dim3(threads), 0, 0, vector_d1, vector_d2, num_nodes);
+
+ // Launch the min.+ kernel
+ hipLaunchKernelGGL(ell_min_dot_plus_kernel, dim3(grid), dim3(threads), 0, 0, num_nodes, height,
+ ell_col_d, ell_data_d,
+ vector_d1, vector_d2);
+
+ // Launch the check kernel
+ hipLaunchKernelGGL(vector_diff, dim3(grid), dim3(threads), 0, 0, vector_d1, vector_d2,
+ stop_d, num_nodes);
+
+ // Read the termination variable back
+ err = hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read stop_d (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+ // Exit the loop
+ if (stop == 0) {
+ break;
+ }
+ cnt++;
+ }
+ hipDeviceSynchronize();
+ double timer4 = gettime();
+
+ // Read the cost_array back
+ err = hipMemcpy(cost_array, vector_d1, num_nodes * sizeof(int), hipMemcpyDeviceToHost);
+ if (err != hipSuccess) {
+ fprintf(stderr, "ERROR: read vector_d1 (%s)\n", hipGetErrorString(err));
+ return -1;
+ }
+
+#ifdef GEM5_FUSION
+ m5_work_end(0, 0);
+#endif
+
+ double timer2 = gettime();
+
+ // Print the timing statistics
+ printf("kernel + memcpy time = %lf ms\n", (timer2 - timer1) * 1000);
+ printf("kernel time = %lf ms\n", (timer4 - timer3) * 1000);
+ printf("number iterations = %d\n", cnt);
+
+#if 1
+ // Print cost_array
+ print_vector(cost_array, num_nodes);
+#endif
+
+ // Clean up the host arrays
+ free(cost_array);
+ csr->freeArrays();
+ free(csr);
+
+ free(ell->col_array);
+ free(ell->data_array);
+ free(ell);
+
+ // Clean up the device-side buffers
+ hipFree(ell_col_d);
+ hipFree(ell_data_d);
+ hipFree(stop_d);
+ hipFree(vector_d1);
+ hipFree(vector_d2);
+
+ return 0;
+}
+
+void print_vector(int *vector, int num)
+{
+
+ FILE * fp = fopen("result.out", "w");
+ if (!fp) {
+ printf("ERROR: unable to open result.txt\n");
+ }
+
+ for (int i = 0; i < num; i++)
+ fprintf(fp, "%d: %d\n", i + 1, vector[i]);
+
+ fclose(fp);
+}
diff --git a/src/gpu/pennant/Makefile b/src/gpu/pennant/Makefile
index 14fec63..246e419 100644
--- a/src/gpu/pennant/Makefile
+++ b/src/gpu/pennant/Makefile
@@ -1,3 +1,4 @@
+HIP_PATH ?= /opt/rocm/bin
BUILDDIR := build
PRODUCT := pennant
@@ -20,7 +21,7 @@
# begin compiler-dependent flags
#
# gcc flags:
-CXX := hipcc #g++
+CXX := $(HIP_PATH)/hipcc #g++
CXXFLAGS_DEBUG := -g
CXXFLAGS_OPT := -O3 #-mcpu=native
CXXFLAGS_OPENMP := #-fopenmp
@@ -45,7 +46,7 @@
# end compiler-dependent flags
-CUDAC := hipcc
+CUDAC := $(HIP_PATH)/hipcc
CUDACFLAGS := #--generate-code arch=compute_60,code=sm_60 --ptxas-options=-v
CUDACFLAGS_DEBUG := -G -lineinfo
CUDACFLAGS_OPT := -O3
diff --git a/src/gpu/square/README.md b/src/gpu/square/README.md
index 104f434..28db907 100644
--- a/src/gpu/square/README.md
+++ b/src/gpu/square/README.md
@@ -23,20 +23,22 @@
The compiled binary can be found in the `bin` directory.
+## Pre-built binary
+
A pre-built binary can be found at <http://dist.gem5.org/dist/v21-1/test-progs/square/square>.
-## Compiling GN3_X86/gem5.opt
+## Compiling GCN3_X86/gem5.opt
The test is run with the GCN3_X86 gem5 variant, compiled using the gcn-gpu docker image:
```
git clone https://gem5.googlesource.com/public/gem5
cd gem5
-docker run -u $UID:$GUID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest scons build/GCN3_X86/gem5.opt -j <num cores>
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest scons build/GCN3_X86/gem5.opt -j <num cores>
```
## Running Square on GCN3_X86/gem5.opt
```
-docker run -u $UID:$GUID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n 3 -c bin/square
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) gcr.io/gem5-test/gcn-gpu:latest gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py -n 3 -c bin/square
```
diff --git a/src/npb/README.md b/src/npb/README.md
index 278c4c8..0ef8530 100644
--- a/src/npb/README.md
+++ b/src/npb/README.md
@@ -5,12 +5,13 @@
- fullsystem
permalink: resources/npb
shortdoc: >
- Disk images and gem5 configurations to run the [NAS parallel benchmarks](https://www.nas.nasa.gov/).
+ Disk image and a gem5 configuration script to run the [NAS parallel benchmarks](https://www.nas.nasa.gov/).
author: ["Ayaz Akram"]
license: BSD-3-Clause
---
-This document provides instructions to create a disk image needed to run the NPB tests with gem5 and points to the gem5 configuration files needed to run these tests.
+This document provides instructions to create a disk image needed to run the NPB tests with gem5 and points to an example gem5 configuration script needed to run these tests. The example script uses a pre-built disk-image.
+
The NAS parallel benchmarks ([NPB](https://www.nas.nasa.gov/)) are high performance computing (HPC) workloads consisting of different kernels and pseudo applications:
Kernels:
@@ -48,10 +49,6 @@
| |___ npb-install.sh # Compiles NPB inside the generated disk image
| |___ npb-hooks # The NPB source (modified to function better with gem5).
|
- |___ configs
- | |___ system # gem5 system config files
- | |___ run_npb.py # gem5 run script to run NPB tests
- |
|___ linux # Linux source and binary will live here
|
|___ README.md # This README file
@@ -77,32 +74,49 @@
Once this process succeeds, the created disk image can be found on `npb/npb-image/npb`.
A disk image already created following the above instructions can be found, gzipped, [here](http://dist.gem5.org/dist/v21-1/images/x86/ubuntu-18-04/npb.img.gz).
-## gem5 Run Scripts
+## Simulating NPB using an example script
-The gem5 scripts which configure the system and run simulation are available in configs-npb-tests/.
-The main script `run_npb.py` expects following arguments:
+An example script with a pre-configured system is available in the following directory within the gem5 repository:
-**kernel:** path to the Linux kernel. This disk image has been tested with version 4.19.83, available at <http://dist.gem5.org/dist/v21-1/kernels/x86/static/vmlinux-4.19.83>. More info on building Linux Kernels can be found in the `src/linux-kernels` directory.
+```
+gem5/configs/example/gem5_library/x86-npb-benchmarks.py
+```
-**disk:** path to the npb disk image.
+The example script specifies a system with the following parameters:
-**cpu:** CPU model (`kvm`, `atomic`, `timing`).
+* A `SimpleSwitchableProcessor` (`KVM` for startup and `TIMING` for ROI execution). There are 2 CPU cores, each clocked at 3 GHz.
+* 2 Level `MESI_Two_Level` cache with 32 kB L1I and L1D size, and, 256 kB L2 size. The L1 cache(s) has associativity of 8, and, the L2 cache has associativity 16. There are 2 L2 cache banks.
+* The system has 3 GB `SingleChannelDDR4_2400` memory.
+* The script uses `x86-linux-kernel-4.19.83` and `x86-npb`, the disk image created from following the instructions in this `README.md`.
-**mem_sys:** memory system (`classic`, `MI_example`, `MESI_Two_Level`, or `MOESI_CMP_directory`).
-
-**benchmark:** NPB benchmark to execute (`bt.A.x`, `cg.A.x`, `ep.A.x`, `ft.A.x`, `is.A.x`, `lu.A.x`, `mg.A.x`, `sp.A.x`).
-
-**Note:**
-We have only tested class `A` of the NPB suite, though `A`,`B`,`C` and `D` of NPB are available in the disk image
-For example, for build class `F` of the `bt` benchmark `bt.F.x` can be specified (replacinv `A` with `F` from above).
-
-**num_cpus:** number of CPU cores.
-
-An example of how to use these scripts:
+The example script must be run with the `X86_MESI_Two_Level` binary. To build:
```sh
-gem5/build/X86/gem5.opt configs/run_npb.py <kernel> <disk> <cpu> <mem_sys> <benchmark> <num_cpus>
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+scons build/X86/gem5.opt -j<proc>
```
+Once compiled, you may use the example config file to run the NPB benchmark programs. You would need to specify the benchmark program (`bt`, `cg`, `ep`, `ft`, `is`, `lu`, `mg`, `sp`) and the class (`A`, `B`, `C`) separately, using the following command:
+
+```sh
+# In the gem5 directory
+build/X86/gem5.opt \
+configs/example/gem5_library/x86-npb-benchmarks.py \
+--benchmark <benchmark_program> \
+--size <class_of_the_benchmark>
+```
+
+Description of the two arguments, provided in the above command are:
+* **--benchmark**, which refers to one of 8 benchmark programs, provided in the NAS parallel benchmark suite. These include `bt`, `cg`, `ep`, `ft`, `is`, `lu`, `mg` and `sp`. For more information on the workloads can be found at <https://www.nas.nasa.gov/>.
+* **--size**, which refers to the workload class to simulate. The classes present in the pre-built disk-image are `A`, `B`, `C` and `D`. More information regarding these classes are written in the following paragraphs.
+
+A few important notes to keep in mind while simulating NPB using the disk-image from gem5 resources:
+
+* The pre-built disk image has NPB executables for classes `A`, `B`, `C` and `D`.
+* Classes `D` and `F` requires main memory sizes of more than 3 GB. Therefore, most of the benchmark programs for class `D` will fail to be executed properly, as our system only has 3 GB of main memory. The `X86Board` from `gem5 stdlib` is currently limited to 3 GB of memory.
+* Only benchmark `ep` with class `D` works in the aforemented configuration.
+* The configuration file `x86-npb-benchmarks.py` takes class input of `A`, `B` or `C`.
+* More information on memory footprint for NPB is available in the paper by [Akram et al.](https://arxiv.org/abs/2010.13216)
## Working Status
diff --git a/src/npb/configs/run_npb.py b/src/npb/configs/run_npb.py
deleted file mode 100755
index 7aa3dca..0000000
--- a/src/npb/configs/run_npb.py
+++ /dev/null
@@ -1,215 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2019 The Regents of the University of California.
-# All rights reserved.
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power, Ayaz Akram
-
-""" Script to run NAS parallel benchmarks with gem5.
- The script expects kernel, diskimage, mem_sys,
- cpu (kvm, atomic, or timing), benchmark to run
- and number of cpus as arguments.
-
- If your application has ROI annotations, this script will count the total
- number of instructions executed in the ROI. It also tracks how much
- wallclock and simulated time.
-"""
-import argparse
-import time
-import m5
-import m5.ticks
-from m5.objects import *
-
-from system import *
-
-def writeBenchScript(dir, bench):
- """
- This method creates a script in dir which will be eventually
- passed to the simulated system (to run a specific benchmark
- at bootup).
- """
- file_name = '{}/run_{}'.format(dir, bench)
- bench_file = open(file_name,"w+")
- bench_file.write('/home/gem5/NPB3.3-OMP/bin/{} \n'.format(bench))
-
- # sleeping for sometime (5 seconds here) makes sure
- # that the benchmark's output has been
- # printed to the console
- bench_file.write('sleep 5 \n')
- bench_file.write('m5 exit \n')
- bench_file.close()
- return file_name
-
-supported_protocols = ["classic", "MI_example", "MESI_Two_Level",
- "MOESI_CMP_directory"]
-supported_cpu_types = ['kvm', 'atomic', 'timing']
-benchmark_choices = ['bt.A.x', 'cg.A.x', 'ep.A.x', 'ft.A.x',
- 'is.A.x', 'lu.A.x', 'mg.A.x', 'sp.A.x',
- 'bt.B.x', 'cg.B.x', 'ep.B.x', 'ft.B.x',
- 'is.B.x', 'lu.B.x', 'mg.B.x', 'sp.B.x',
- 'bt.C.x', 'cg.C.x', 'ep.C.x', 'ft.C.x',
- 'is.C.x', 'lu.C.x', 'mg.C.x', 'sp.C.x',
- 'bt.D.x', 'cg.D.x', 'ep.D.x', 'ft.D.x',
- 'is.D.x', 'lu.D.x', 'mg.D.x', 'sp.D.x',
- 'bt.F.x', 'cg.F.x', 'ep.F.x', 'ft.F.x',
- 'is.F.x', 'lu.F.x', 'mg.F.x', 'sp.F.x']
-
-def parse_options():
-
- parser = argparse.ArgumentParser(description='For use with gem5. This '
- 'runs a NAS Parallel Benchmark application. This only works '
- 'with x86 ISA.')
-
- # The manditry position arguments.
- parser.add_argument("kernel", type=str,
- help="Path to the kernel binary to boot")
- parser.add_argument("disk", type=str,
- help="Path to the disk image to boot")
- parser.add_argument("cpu", type=str, choices=supported_cpu_types,
- help="The type of CPU to use in the system")
- parser.add_argument("mem_sys", type=str, choices=supported_protocols,
- help="Type of memory system or coherence protocol")
- parser.add_argument("benchmark", type=str, choices=benchmark_choices,
- help="The NPB application to run")
- parser.add_argument("num_cpus", type=int, help="Number of CPU cores")
-
- # The optional arguments.
- parser.add_argument("--no_host_parallel", action="store_true",
- help="Do NOT run gem5 on multiple host threads "
- "(kvm only)")
- parser.add_argument("--second_disk", type=str,
- help="The second disk image to mount (/dev/hdb)")
- parser.add_argument("--no_prefetchers", action="store_true",
- help="Enable prefectchers on the caches")
- parser.add_argument("--l1i_size", type=str, default='32kB',
- help="L1 instruction cache size. Default: 32kB")
- parser.add_argument("--l1d_size", type=str, default='32kB',
- help="L1 data cache size. Default: 32kB")
- parser.add_argument("--l2_size", type=str, default = "256kB",
- help="L2 cache size. Default: 256kB")
- parser.add_argument("--l3_size", type=str, default = "4MB",
- help="L2 cache size. Default: 4MB")
-
- return parser.parse_args()
-
-if __name__ == "__m5_main__":
- args = parse_options()
-
-
- # create the system we are going to simulate
- system = MySystem(args.kernel, args.disk, args.num_cpus, args,
- no_kvm=False)
-
-
- if args.mem_sys == "classic":
- system = MySystem(args.kernel, args.disk, args.num_cpus, args,
- no_kvm=False)
- else:
- system = MyRubySystem(args.kernel, args.disk, args.mem_sys,
- args.num_cpus, args)
-
- # Exit from guest on workbegin/workend
- system.exit_on_work_items = True
-
- # Create and pass a script to the simulated system to run the reuired
- # benchmark
- system.readfile = writeBenchScript(m5.options.outdir, args.benchmark)
-
- # set up the root SimObject and start the simulation
- root = Root(full_system = True, system = system)
-
- if system.getHostParallel():
- # Required for running kvm on multiple host cores.
- # Uses gem5's parallel event queue feature
- # Note: The simulator is quite picky about this number!
- root.sim_quantum = int(1e9) # 1 ms
-
- #needed for long running jobs
- m5.disableAllListeners()
-
- # instantiate all of the objects we've created above
- m5.instantiate()
-
- globalStart = time.time()
-
- print("Running the simulation")
- print("Using cpu: {}".format(args.cpu))
- exit_event = m5.simulate()
-
- if exit_event.getCause() == "workbegin":
- print("Done booting Linux")
- # Reached the start of ROI
- # start of ROI is marked by an
- # m5_work_begin() call
- print("Resetting stats at the start of ROI!")
- m5.stats.reset()
- start_tick = m5.curTick()
- start_insts = system.totalInsts()
- # switching cpu if argument cpu == atomic or timing
- if args.cpu == 'atomic':
- system.switchCpus(system.cpu, system.atomicCpu)
- if args.cpu == 'timing':
- system.switchCpus(system.cpu, system.timingCpu)
- else:
- print("Unexpected termination of simulation !")
- exit()
-
- # Simulate the ROI
- exit_event = m5.simulate()
-
- # Reached the end of ROI
- # Finish executing the benchmark
-
- print("Dump stats at the end of the ROI!")
- m5.stats.dump()
- end_tick = m5.curTick()
- end_insts = system.totalInsts()
- m5.stats.reset()
-
- # Switching back to KVM does not work
- # with Ruby mem protocols, so not
- # switching back to simulate the remaining
- # part
-
- if args.mem_sys == 'classic':
- # switch cpu back to kvm if atomic/timing was used for ROI
- if args.cpu == 'atomic':
- system.switchCpus(system.atomicCpu, system.cpu)
- if args.cpu == 'timing':
- system.switchCpus(system.timingCpu, system.cpu)
-
- # Simulate the remaning part of the benchmark
- exit_event = m5.simulate()
- else:
- print("Ruby Mem: Not Switching back to KVM!")
-
- print("Done with the simulation")
- print()
- print("Performance statistics:")
-
- print("Simulated time in ROI: %.2fs" % ((end_tick-start_tick)/1e12))
- print("Instructions executed in ROI: %d" % ((end_insts-start_insts)))
- print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
- print("Total wallclock time: %.2fs, %.2f min" % \
- (time.time()-globalStart, (time.time()-globalStart)/60))
diff --git a/src/npb/configs/system/MESI_Two_Level.py b/src/npb/configs/system/MESI_Two_Level.py
deleted file mode 100755
index 6fd9b4c..0000000
--- a/src/npb/configs/system/MESI_Two_Level.py
+++ /dev/null
@@ -1,336 +0,0 @@
-#Copyright (c) 2020 The Regents of the University of California.
-#All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MESI TWO Level protocol
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MESITwoLevelCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
- fatal("This system assumes MESI_Two_Level!")
-
- super(MESITwoLevelCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MESI_Two_Level example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU
- # core. The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in \
- range(self._numL2Caches)] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False)
- self.l2_select_num_bits = int(math.log(num_l2Caches , 2))
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.enable_prefetch = False
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.out_port = ruby_system.network.in_port
-
- self.optionalQueue = MessageBuffer()
-
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getBlockSizeBits(system,
- num_l2Caches))
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
- self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/npb/configs/system/MI_example_caches.py b/src/npb/configs/system/MI_example_caches.py
deleted file mode 100755
index 3c7a71d..0000000
--- a/src/npb/configs/system/MI_example_caches.py
+++ /dev/null
@@ -1,275 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2015 Jason Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Power
-
-""" This file creates a set of Ruby caches, the Ruby network, and a simple
-point-to-point topology.
-See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
-You can change simple_ruby to import from this file instead of from msi_caches
-to use the MI_example protocol instead of MSI.
-
-IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
- also needs to be updated. For now, email Jason <jason@lowepower.com>
-
-"""
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MIExampleSystem(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MI_example':
- fatal("This system assumes MI_example!")
-
- super(MIExampleSystem, self).__init__()
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MI example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # Create one controller for each L1 cache (and the cache mem obj.)
- # Create a single directory controller (Really the memory cntrl)
- self.controllers = \
- [L1Cache(system, self, cpu) for cpu in cpus] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU. In many systems this is more
- # complicated since you have to create sequencers for DMA controllers
- # and other controllers, too.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].cacheMemory,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[0:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu):
- """CPUs are needed to grab the clock domain and system is needed for
- the cache block size.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.cacheMemory = RubyCache(size = '16kB',
- assoc = 8,
- start_index_bit = self.getBlockSizeBits(system))
- self.clk_domain = cpu.clk_domain
- self.send_evictions = self.sendEvicts(cpu)
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromCache = MessageBuffer(ordered = True)
- self.requestFromCache.out_port = ruby_system.network.in_port
- self.responseFromCache = MessageBuffer(ordered = True)
- self.responseFromCache.out_port = ruby_system.network.in_port
- self.forwardToCache = MessageBuffer(ordered = True)
- self.forwardToCache.in_port = ruby_system.network.out_port
- self.responseToCache = MessageBuffer(ordered = True)
- self.responseToCache.in_port = ruby_system.network.out_port
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer(ordered = True)
- self.requestToDir.in_port = ruby_system.network.out_port
- self.dmaRequestToDir = MessageBuffer(ordered = True)
- self.dmaRequestToDir.in_port = ruby_system.network.out_port
-
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.dmaResponseFromDir = MessageBuffer(ordered = True)
- self.dmaResponseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/npb/configs/system/MOESI_CMP_directory.py b/src/npb/configs/system/MOESI_CMP_directory.py
deleted file mode 100755
index 33f9f47..0000000
--- a/src/npb/configs/system/MOESI_CMP_directory.py
+++ /dev/null
@@ -1,350 +0,0 @@
-#Copyright (c) 2020 The Regents of the University of California.
-#All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MOESI CMP directory
-protocol.
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MOESICMPDirCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
- fatal("This system assumes MOESI_CMP_directory!")
-
- super(MOESICMPDirCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MOESI_CMP_directory example uses 3 virtual networks
- self.number_of_virtual_networks = 3
- self.network.number_of_virtual_networks = 3
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU
- # core. The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in \
- range(self._numL2Caches)] + [DirController(self, \
- system.mem_ranges, mem_ctrls)] + [DMAController(self) for i \
- in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getL2StartIdx(system,
- num_l2Caches),
- dataAccessLatency = 20,
- tagAccessLatency = 20)
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getL2StartIdx(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.GlobalRequestFromL2Cache = MessageBuffer()
- self.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
-
- self.GlobalRequestToL2Cache = MessageBuffer()
- self.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.reqToDir = MessageBuffer()
- self.reqToDir.out_port = ruby_system.network.in_port
- self.respToDir = MessageBuffer()
- self.respToDir.out_port = ruby_system.network.in_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/npb/configs/system/__init__.py b/src/npb/configs/system/__init__.py
deleted file mode 100755
index 94e676f..0000000
--- a/src/npb/configs/system/__init__.py
+++ /dev/null
@@ -1,31 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from .system import MySystem
-from .ruby_system import MyRubySystem
diff --git a/src/npb/configs/system/caches.py b/src/npb/configs/system/caches.py
deleted file mode 100755
index 9e44211..0000000
--- a/src/npb/configs/system/caches.py
+++ /dev/null
@@ -1,173 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-""" Caches with options for a simple gem5 configuration script
-
-This file contains L1 I/D and L2 caches to be used in the simple
-gem5 configuration script.
-"""
-
-from m5.objects import Cache, L2XBar, StridePrefetcher
-
-# Some specific options for caches
-# For all options see src/mem/cache/BaseCache.py
-
-class PrefetchCache(Cache):
-
- def __init__(self, options):
- super(PrefetchCache, self).__init__()
- if not options or options.no_prefetchers:
- return
- self.prefetcher = StridePrefetcher()
-
-class L1Cache(PrefetchCache):
- """Simple L1 Cache with default values"""
-
- assoc = 8
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 16
- tgts_per_mshr = 20
- writeback_clean = True
-
- def __init__(self, options=None):
- super(L1Cache, self).__init__(options)
- pass
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU-side port
- This must be defined in a subclass"""
- raise NotImplementedError
-
-class L1ICache(L1Cache):
- """Simple L1 instruction cache with default values"""
-
- def __init__(self, opts=None):
- super(L1ICache, self).__init__(opts)
- if not opts or not opts.l1i_size:
- return
- self.size = opts.l1i_size
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU icache port"""
- self.cpu_side = cpu.icache_port
-
-class L1DCache(L1Cache):
- """Simple L1 data cache with default values"""
-
- def __init__(self, opts=None):
- super(L1DCache, self).__init__(opts)
- if not opts or not opts.l1d_size:
- return
- self.size = opts.l1d_size
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU dcache port"""
- self.cpu_side = cpu.dcache_port
-
-class MMUCache(Cache):
- # Default parameters
- size = '8kB'
- assoc = 4
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(MMUCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect the CPU itb and dtb to the cache
- Note: This creates a new crossbar
- """
- self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
-class L2Cache(PrefetchCache):
- """Simple L2 Cache with default values"""
-
- # Default parameters
- assoc = 16
- tag_latency = 10
- data_latency = 10
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self, opts=None):
- super(L2Cache, self).__init__(opts)
- if not opts or not opts.l2_size:
- return
- self.size = opts.l2_size
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
-
-class L3Cache(Cache):
- """Simple L3 Cache bank with default values
- This assumes that the L3 is made up of multiple banks. This cannot
- be used as a standalone L3 cache.
- """
-
- # Default parameters
- assoc = 32
- tag_latency = 40
- data_latency = 40
- response_latency = 10
- mshrs = 256
- tgts_per_mshr = 12
- clusivity = 'mostly_excl'
-
- def __init__(self, opts):
- super(L3Cache, self).__init__()
- self.size = (opts.l3_size)
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
diff --git a/src/npb/configs/system/fs_tools.py b/src/npb/configs/system/fs_tools.py
deleted file mode 100755
index 5e5e2df..0000000
--- a/src/npb/configs/system/fs_tools.py
+++ /dev/null
@@ -1,39 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
-
-class CowDisk(IdeDisk):
-
- def __init__(self, filename):
- super(CowDisk, self).__init__()
- self.driveID = 'device0'
- self.image = CowDiskImage(child=RawDiskImage(read_only=True),
- read_only=False)
- self.image.child.image_file = filename
diff --git a/src/npb/configs/system/ruby_system.py b/src/npb/configs/system/ruby_system.py
deleted file mode 100755
index a6d7fcb..0000000
--- a/src/npb/configs/system/ruby_system.py
+++ /dev/null
@@ -1,238 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-
-
-class MyRubySystem(System):
-
- def __init__(self, kernel, disk, mem_sys, num_cpus, opts):
- super(MyRubySystem, self).__init__()
- self._opts = opts
-
- self._host_parallel = True
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- self.initFS(num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus)
-
- self.createMemoryControllersDDR3()
-
- # Create the cache hierarchy for the system.
- if mem_sys == 'MI_example':
- from .MI_example_caches import MIExampleSystem
- self.caches = MIExampleSystem()
- elif mem_sys == 'MESI_Two_Level':
- from .MESI_Two_Level import MESITwoLevelCache
- self.caches = MESITwoLevelCache()
- elif mem_sys == 'MOESI_CMP_directory':
- from .MOESI_CMP_directory import MOESICMPDirCache
- self.caches = MOESICMPDirCache()
- self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma,
- self.iobus.mem_side_ports],
- self.iobus)
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
-
- # the number of eventqs are set based
- # on experiments with few benchmarks
-
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus):
-
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
- self.createCPUThreads(self.cpu)
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.timingCpu = [TimingSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.timingCpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createMemoryControllersDDR3(self):
- self._createMemoryControllers(1, DDR3_1600_8x8)
-
- def _createMemoryControllers(self, num, cls):
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = self.mem_ranges[0]))
- for i in range(num)
- ]
-
- def initFS(self, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # North Bridge
- self.iobus = IOXBar()
-
- # connect the io bus
- # Note: pass in a reference to where Ruby will connect to in the future
- # so the port isn't connected twice.
- self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/npb/configs/system/system.py b/src/npb/configs/system/system.py
deleted file mode 100755
index f0e71c2..0000000
--- a/src/npb/configs/system/system.py
+++ /dev/null
@@ -1,392 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2018 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-from .caches import *
-
-
-class MySystem(System):
-
- def __init__(self, kernel, disk, num_cpus, opts, no_kvm=False):
- super(MySystem, self).__init__()
- self._opts = opts
- self._no_kvm = no_kvm
-
- self._host_parallel = not self._opts.no_host_parallel
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '2.3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- mem_size = '32GB'
- self.mem_ranges = [AddrRange('100MB'), # For kernel
- AddrRange(0xC0000000, size=0x100000), # For I/0
- AddrRange(Addr('4GB'), size = mem_size) # All data
- ]
-
- # Create the main memory bus
- # This connects to main memory
- self.membus = SystemXBar(width = 64) # 64-byte width
- self.membus.badaddr_responder = BadAddr()
- self.membus.default = Self.badaddr_responder.pio
-
- # Set up the system port for functional access from the simulator
- self.system_port = self.membus.cpu_side_ports
-
- self.initFS(self.membus, num_cpus)
-
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
-
- self.setDiskImages(disk, disk)
-
- if opts.second_disk:
- self.setDiskImages(disk, opts.second_disk)
- else:
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus)
-
- # Create the cache heirarchy for the system.
- self.createCacheHierarchy()
-
- # Set up the interrupt controllers for the system (x86 specific)
- self.setupInterrupts()
-
- self.createMemoryControllersDDR4()
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
-
- # the number of eventqs are set based
- # on experiments with few benchmarks
-
- if len(self.cpu) > 16:
- cpu.eventq_index = (i/4) + 1
- else:
- cpu.eventq_index = (i/2) + 1
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus):
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.mem_mode = 'timing'
-
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.timingCpu = [TimingSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
-
- self.createCPUThreads(self.timingCpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createCacheHierarchy(self):
- # Create an L3 cache (with crossbar)
- self.l3bus = L2XBar(width = 64,
- snoop_filter = SnoopFilter(max_capacity='32MB'))
-
- for cpu in self.cpu:
- # Create a memory bus, a coherent crossbar, in this case
- cpu.l2bus = L2XBar()
-
- # Create an L1 instruction and data cache
- cpu.icache = L1ICache(self._opts)
- cpu.dcache = L1DCache(self._opts)
- cpu.mmucache = MMUCache()
-
- # Connect the instruction and data caches to the CPU
- cpu.icache.connectCPU(cpu)
- cpu.dcache.connectCPU(cpu)
- cpu.mmucache.connectCPU(cpu)
-
- # Hook the CPU ports up to the l2bus
- cpu.icache.connectBus(cpu.l2bus)
- cpu.dcache.connectBus(cpu.l2bus)
- cpu.mmucache.connectBus(cpu.l2bus)
-
- # Create an L2 cache and connect it to the l2bus
- cpu.l2cache = L2Cache(self._opts)
- cpu.l2cache.connectCPUSideBus(cpu.l2bus)
-
- # Connect the L2 cache to the L3 bus
- cpu.l2cache.connectMemSideBus(self.l3bus)
-
- self.l3cache = L3Cache(self._opts)
- self.l3cache.connectCPUSideBus(self.l3bus)
-
- # Connect the L3 cache to the membus
- self.l3cache.connectMemSideBus(self.membus)
-
- def setupInterrupts(self):
- for cpu in self.cpu:
- # create the interrupt controller CPU and connect to the membus
- cpu.createInterruptController()
-
- # For x86 only, connect interrupts to the memory
- # Note: these are directly connected to the memory bus and
- # not cached
- cpu.interrupts[0].pio = self.membus.mem_side_ports
- cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
- cpu.interrupts[0].int_responder = self.membus.mem_side_ports
-
- # Memory latency: Using the smaller number from [3]: 96ns
- def createMemoryControllersDDR4(self):
- self._createMemoryControllers(8, DDR4_2400_16x4)
-
- def _createMemoryControllers(self, num, cls):
- kernel_controller = self._createKernelMemoryController(cls)
-
- ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
-
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = ranges[i]),
- port = self.membus.mem_side_ports)
- for i in range(num)
- ] + [kernel_controller]
-
- def _createKernelMemoryController(self, cls):
- return MemCtrl(dram = cls(range = self.mem_ranges[0]),
- port = self.membus.mem_side_ports)
-
- def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
- from math import log
- bits = int(log(num, 2))
- if 2**bits != num:
- m5.fatal("Non-power of two number of memory controllers")
-
- intlv_bits = bits
- ranges = [
- AddrRange(start=rng.start,
- end=rng.end,
- intlvHighBit = intlv_low_bit + intlv_bits - 1,
- xorHighBit = xor_low_bit + intlv_bits - 1,
- intlvBits = intlv_bits,
- intlvMatch = i)
- for i in range(num)
- ]
-
- return ranges
-
- def initFS(self, membus, cpus):
- self.pc = Pc()
- self.workload = X86FsLinux()
-
- # Constants similar to x86_traits.hh
- IO_address_space_base = 0x8000000000000000
- pci_config_address_space_base = 0xc000000000000000
- interrupts_address_space_base = 0xa000000000000000
- APIC_range_size = 1 << 12;
-
- # North Bridge
- self.iobus = IOXBar()
- self.bridge = Bridge(delay='50ns')
- self.bridge.mem_side_port = self.iobus.cpu_side_ports
- self.bridge.cpu_side_port = membus.mem_side_ports
- # Allow the bridge to pass through:
- # 1) kernel configured PCI device memory map address: address range
- # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
- # 2) the bridge to pass through the IO APIC (two pages, already
- # contained in 1),
- # 3) everything in the IO address range up to the local APIC, and
- # 4) then the entire PCI address space and beyond.
- self.bridge.ranges = \
- [
- AddrRange(0xC0000000, 0xFFFF0000),
- AddrRange(IO_address_space_base,
- interrupts_address_space_base - 1),
- AddrRange(pci_config_address_space_base,
- Addr.max)
- ]
-
- # Create a bridge from the IO bus to the memory bus to allow access
- # to the local APIC (two pages)
- self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
- self.apicbridge.mem_side_port = membus.cpu_side_ports
- self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
- interrupts_address_space_base +
- cpus * APIC_range_size
- - 1)]
-
- # connect the io bus
- self.pc.attachIO(self.iobus)
-
- # Add a tiny cache to the IO bus.
- # This cache is required for the classic memory model for coherence
- self.iocache = Cache(assoc=8,
- tag_latency = 50,
- data_latency = 50,
- response_latency = 50,
- mshrs = 20,
- size = '1kB',
- tgts_per_mshr = 12,
- addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.mem_side_ports
- self.iocache.mem_side = self.membus.cpu_side_ports
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
- # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which
- # force IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests
- # to this specific range can pass though bridge to iobus.
- entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
- size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
- range_type=2))
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- # Add the rest of memory. This is where all the actual data is
- entries.append(X86E820Entry(addr = self.mem_ranges[-1].start,
- size='%dB' % (self.mem_ranges[-1].size()),
- range_type=1))
-
- self.workload.e820_table.entries = entries
-
diff --git a/src/parsec/README.md b/src/parsec/README.md
index 17801f5..801471d 100644
--- a/src/parsec/README.md
+++ b/src/parsec/README.md
@@ -11,7 +11,7 @@
license: BSD-3-Clause
---
-This document includes instructions on how to create an Ubuntu 18.04 disk-image with PARSEC benchmark installed. The disk-image will be compatible with the gem5 simulator.
+This document includes instructions on how to create an Ubuntu 18.04 disk-image with PARSEC benchmark installed. The disk-image will be compatible with the gem5 simulator. It also demostrates how tosimulate the same using an example gem5 script with a pre-configured system. The script uses a pre-built disk-image.
This is how the `src/parsec-tests/` directory will look like if all the artifacts are created correctly.
@@ -31,19 +31,8 @@
| |___ runscript.sh # script to run each workload
| |___ parsec-benchmark # the parsec benchmark suite
|
- |___ configs
- | |___ system # system config directory
- | |___ run_parsec.py # gem5 run script
- |
- |___ configs-mesi-two-level
- | |___ system # system config directory
- | |___ run_parsec_mesi_two_level.py # gem5 run script
- |
|___ README.md
```
-
-Notice that there are two sets of system configuration directories and run scripts. For further detail on the config files look [here](#gem5-run-scripts).
-
## Building the disk image
In order to build the disk-image for PARSEC tests with gem5, build the m5 utility in `src/parsec-tests/` using the following:
@@ -75,29 +64,41 @@
You can find the disk-image in `parsec/parsec-image/parsec`.
-## gem5 run scripts
+## Simulating PARSEC using an example script
-There are two sets of run scripts and system configuration files in the directory. The scripts found in `configs` use the classic memory system while the scripts in `configs-mesi-two-level` use the ruby memory system with MESI_Two_Level cache coherency protocol. The parameters used in the both sets of experiments are explained below:
+An example script with a pre-configured system is available in the following directory within the gem5 repository:
-* **kernel**: The path to the linux kernel. We have verified capatibility with kernel version 4.19.83 which you can download at <http://dist.gem5.org/dist/v21-1/kernels/x86/static/vmlinux-4.19.83>. More information on building kernels for gem5 can be around in `src/linux-kernel`.
-* **disk**: The path to the PARSEC disk-image. This can be downloaded, gzipped, from <http://dist.gem5.org/dist/v21-1/images/x86/ubuntu-18-04/parsec.img.gz>.
-* **cpu**: The type of cpu to use. There are two supported options: `kvm` (KvmCPU) and `timing` (TimingSimpleCPU).
-* **benchmark**: The PARSEC workload to run. They include `blackscholes`, `bodytrack`, `canneal`, `dedup`, `facesim`, `ferret`, `fluidanimate`, `freqmine`, `raytrace`, `streamcluster`, `swaptions`, `vips`, `x264`. For more information on the workloads can be found at <https://parsec.cs.princeton.edu/>.
-* **size**: The size of the chosen workload. Valid sizes are `simsmall`, `simmedium`, and `simlarge`.
-* **num_cpus**: The number of cpus to simulate. When using `configs`, the only valid option is `1`. When using `configs-mesi-two-level` the number of supported cpus is show in the table below:
+```
+gem5/configs/example/gem5_library/x86-parsec-benchmarks.py
+```
+The example script specifies a system with the following parameters:
-| CPU Model | Core Counts |
-|-----------------|-------------|
-| KvmCPU | 1,2,8 |
-| TimingSimpleCPU | 1,2 |
+* A `SimpleSwitchableProcessor` (`KVM` for startup and `TIMING` for ROI execution). There are 2 CPU cores, each clocked at 3 GHz.
+* 2 Level `MESI_Two_Level` cache with 32 kB L1I and L1D size, and, 256 kB L2 size. The L1 cache(s) has associativity of 8, and, the L2 cache has associativity 16. There are 2 L2 cache banks.
+* The system has 3 GB `SingleChannelDDR4_2400` memory.
+* The script uses `x86-linux-kernel-4.19.83` and `x86-parsec`, the disk image created from following the instructions in this `README.md`.
-Below are the examples of running an experiment with the two configurations.
+The example script must be run with the `X86_MESI_Two_Level` binary. To build:
```sh
-<gem5 X86 binary> configs/run_parsec.py <kernel> <disk> <cpu> <benchmark> <size> <num_cpus>
-<gem5 X86_MESI_Two_Level binary> configs-mesi-two-level/run_parsec.py <kernel> <disk> <cpu> <benchmark> <size> <num_cpus>
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+scons build/X86/gem5.opt -j<proc>
```
+Once compiled, you may use the example config file to run the PARSEC benchmark programs using the following command:
+
+```sh
+# In the gem5 directory
+build/X86/gem5.opt \
+configs/example/gem5_library/x86-parsec-benchmarks.py \
+--benchmark <benchmark_program> \
+--size <size> \
+```
+
+Description of the two arguments, provided in the above command are:
+* **--benchmark**, which refers to one of 13 benchmark programs, provided in the PARSEC benchmark suite. These include `blackscholes`, `bodytrack`, `canneal`, `dedup`, `facesim`, `ferret`, `fluidanimate`, `freqmine`, `raytrace`, `streamcluster`, `swaptions`, `vips`, `x264`. For more information on the workloads can be found at <https://parsec.cs.princeton.edu/>.
+* **--size**, which refers to the size of the workload to simulate. There are three valid choices for the same: `simsmall`, `simmedium` and `simlarge`.
## Working Status
diff --git a/src/parsec/configs-mesi-two-level/run_parsec_mesi_two_level.py b/src/parsec/configs-mesi-two-level/run_parsec_mesi_two_level.py
deleted file mode 100755
index 311d8ca..0000000
--- a/src/parsec/configs-mesi-two-level/run_parsec_mesi_two_level.py
+++ /dev/null
@@ -1,225 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2019 The Regents of the University of California.
-# All rights reserved.
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" Script to run PARSEC benchmarks with gem5. The memory model used
- in the experiments is Ruby and uses MESEI_Two_Level protocolx.
- The script expects kernel, diskimage, cpu (kvm or timing),
- benchmark, benchmark size, and number of cpu cores as arguments.
- This script is best used if your disk-image has workloads tha have
- ROI annotations compliant with m5 utility. You can use the script in
- ../disk-images/parsec/ with the parsec-benchmark repo at
- https://github.com/darchr/parsec-benchmark.git to create a working
- disk-image for this script.
-
-"""
-import argparse
-import time
-import m5
-import m5.ticks
-from m5.objects import *
-
-from system import *
-
-supported_cpu_types = ["kvm", "timing"]
-benchmark_choices = ["blackscholes", "bodytrack", "canneal", "dedup",
- "facesim", "ferret", "fluidanimate", "freqmine",
- "raytrace", "streamcluster", "swaptions", "vips", "x264"]
-size_choices=["simsmall", "simmedium", "simlarge"]
-
-
-def parse_options():
-
- parser = argparse.ArgumentParser(description='For use with gem5. This '
- 'runs a NAS Parallel Benchmark application. This only works '
- 'with x86 ISA.')
-
- parser.add_argument("kernel", type=str,
- help="Path to the kernel binary to boot")
- parser.add_argument("disk", type=str, help="Path to the PARSEC disk image")
- parser.add_argument("cpu", type=str, choices=supported_cpu_types,
- help="The type of CPU to use in the system")
- parser.add_argument("benchmark", type=str, choices=benchmark_choices,
- help="The PARSEC benchmark application to run")
- parser.add_argument("size", type=str, choices=size_choices,
- help="The input size to the PARSEC benchmark "
- "application")
- parser.add_argument("num_cpus", type=int, choices=[1,2,8],
- help="The number of CPU cores")
-
- return parser.parse_args()
-
-def writeBenchScript(dir, bench, size, num_cpus):
- """
- This method creates a script in dir which will be eventually
- passed to the simulated system (to run a specific benchmark
- at bootup).
- """
- file_name = '{}/run_{}'.format(dir, bench)
- bench_file = open(file_name, 'w+')
- bench_file.write('cd /home/gem5/parsec-benchmark\n')
- bench_file.write('source env.sh\n')
- bench_file.write('parsecmgmt -a run -p \
- {} -c gcc-hooks -i {} -n {}\n'.format(bench, size, num_cpus))
-
- # sleeping for sometime makes sure
- # that the benchmark's output has been
- # printed to the console
- bench_file.write('sleep 5 \n')
- bench_file.write('m5 exit \n')
- bench_file.close()
- return file_name
-
-if __name__ == "__m5_main__":
-
- args = parse_options()
-
- # create the system we are going to simulate
- system = MyRubySystem(args.kernel, args.disk, args.num_cpus, args)
-
- # Exit from guest on workbegin/workend
- system.exit_on_work_items = True
-
- # Create and pass a script to the simulated system to run the reuired
- # benchmark
- system.readfile = writeBenchScript(m5.options.outdir, args.benchmark,
- args.size, args.num_cpus)
-
- # set up the root SimObject and start the simulation
- root = Root(full_system = True, system = system)
-
- if system.getHostParallel():
- # Required for running kvm on multiple host cores.
- # Uses gem5's parallel event queue feature
- # Note: The simulator is quite picky about this number!
- root.sim_quantum = int(1e9) # 1 ms
-
- #needed for long running jobs
- m5.disableAllListeners()
-
- # instantiate all of the objects we've created above
- m5.instantiate()
-
- globalStart = time.time()
-
- print("Running the simulation")
- print("Using cpu: {}".format(args.cpu))
-
- start_tick = m5.curTick()
- end_tick = m5.curTick()
- start_insts = system.totalInsts()
- end_insts = system.totalInsts()
- m5.stats.reset()
-
- exit_event = m5.simulate()
-
- if exit_event.getCause() == "workbegin":
- print("Done booting Linux")
- # Reached the start of ROI
- # start of ROI is marked by an
- # m5_work_begin() call
- print("Resetting stats at the start of ROI!")
- m5.stats.reset()
- start_tick = m5.curTick()
- start_insts = system.totalInsts()
- # switching to timing cpu if argument cpu == timing
- if args.cpu == 'timing':
- system.switchCpus(system.cpu, system.timingCpu)
- else:
- print("Unexpected termination of simulation!")
- print()
- m5.stats.dump()
- end_tick = m5.curTick()
- end_insts = system.totalInsts()
- m5.stats.reset()
- print("Performance statistics:")
-
- print("Simulated time: %.2fs" % ((end_tick-start_tick)/1e12))
- print("Instructions executed: %d" % ((end_insts-start_insts)))
- print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
- print("Total wallclock time: %.2fs, %.2f min" % \
- (time.time()-globalStart, (time.time()-globalStart)/60))
- exit()
-
- # Simulate the ROI
- exit_event = m5.simulate()
-
- # Reached the end of ROI
- # Finish executing the benchmark with kvm cpu
- if exit_event.getCause() == "workend":
- # Reached the end of ROI
- # end of ROI is marked by an
- # m5_work_end() call
- print("Dump stats at the end of the ROI!")
- m5.stats.dump()
- end_tick = m5.curTick()
- end_insts = system.totalInsts()
- m5.stats.reset()
- # switching to timing cpu if argument cpu == timing
- if args.cpu == 'timing':
- # This line is commented due to an unimplemented
- # flush request in MESI_Two_Level that results in
- # the crashing of simulation. There will be a patch
- # fixing this issue but the line is commented out
- # for now.
- # system.switchCpus(system.timingCpu, system.cpu)
- print("Performance statistics:")
-
- print("Simulated time: %.2fs" % ((end_tick-start_tick)/1e12))
- print("Instructions executed: %d" % ((end_insts-start_insts)))
- print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
- print("Total wallclock time: %.2fs, %.2f min" % \
- (time.time()-globalStart, (time.time()-globalStart)/60))
- exit()
- else:
- print("Unexpected termination of simulation!")
- print()
- m5.stats.dump()
- end_tick = m5.curTick()
- end_insts = system.totalInsts()
- m5.stats.reset()
- print("Performance statistics:")
-
- print("Simulated time: %.2fs" % ((end_tick-start_tick)/1e12))
- print("Instructions executed: %d" % ((end_insts-start_insts)))
- print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
- print("Total wallclock time: %.2fs, %.2f min" % \
- (time.time()-globalStart, (time.time()-globalStart)/60))
- exit()
-
- # Simulate the remaning part of the benchmark
- exit_event = m5.simulate()
-
- print("Done with the simulation")
- print()
- print("Performance statistics:")
-
- print("Simulated time in ROI: %.2fs" % ((end_tick-start_tick)/1e12))
- print("Instructions executed in ROI: %d" % ((end_insts-start_insts)))
- print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
- print("Total wallclock time: %.2fs, %.2f min" % \
- (time.time()-globalStart, (time.time()-globalStart)/60))
diff --git a/src/parsec/configs-mesi-two-level/system/MESI_Two_Level.py b/src/parsec/configs-mesi-two-level/system/MESI_Two_Level.py
deleted file mode 100644
index 4dfdf39..0000000
--- a/src/parsec/configs-mesi-two-level/system/MESI_Two_Level.py
+++ /dev/null
@@ -1,339 +0,0 @@
-#Copyright (c) 2020 The Regents of the University of California.
-#All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MESI TWO Level protocol
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-This system support the memory size of up to 3GB.
-"""
-
-
-
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MESITwoLevelCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
- fatal("This system assumes MESI_Two_Level!")
-
- super(MESITwoLevelCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MESI_Two_Level example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU core.
- # The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in range(self._numL2Caches)] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = \
- self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False)
- self.l2_select_num_bits = int(math.log(num_l2Caches , 2))
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.enable_prefetch = False
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.out_port = ruby_system.network.in_port
-
- self.optionalQueue = MessageBuffer()
-
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getBlockSizeBits(system, num_l2Caches))
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
- self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
-
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/parsec/configs-mesi-two-level/system/__init__.py b/src/parsec/configs-mesi-two-level/system/__init__.py
deleted file mode 100755
index fcc7c95..0000000
--- a/src/parsec/configs-mesi-two-level/system/__init__.py
+++ /dev/null
@@ -1,29 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-from .ruby_system import MyRubySystem
\ No newline at end of file
diff --git a/src/parsec/configs-mesi-two-level/system/fs_tools.py b/src/parsec/configs-mesi-two-level/system/fs_tools.py
deleted file mode 100755
index 9c02722..0000000
--- a/src/parsec/configs-mesi-two-level/system/fs_tools.py
+++ /dev/null
@@ -1,40 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
-import errno
-import os
-import sys
-class CowDisk(IdeDisk):
-
- def __init__(self, filename):
- super(CowDisk, self).__init__()
- self.driveID = 'device0'
- self.image = CowDiskImage(child=RawDiskImage(read_only=True),
- read_only=False)
- self.image.child.image_file = filename
diff --git a/src/parsec/configs-mesi-two-level/system/ruby_system.py b/src/parsec/configs-mesi-two-level/system/ruby_system.py
deleted file mode 100755
index e4e9d1f..0000000
--- a/src/parsec/configs-mesi-two-level/system/ruby_system.py
+++ /dev/null
@@ -1,242 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-import m5
-import math
-from m5.objects import *
-from .fs_tools import *
-
-class MyRubySystem(System):
-
- def __init__(self, kernel, disk, num_cpus, opts):
- super(MyRubySystem, self).__init__()
- self._opts = opts
-
- self._host_parallel = True
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- self.initFS(num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus)
-
- self.createMemoryControllersDDR3()
-
- # Create the cache hierarchy for the system.
-
- from .MESI_Two_Level import MESITwoLevelCache
- self.caches = MESITwoLevelCache()
-
- self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma,
- self.iobus.mem_side_ports],
- self.iobus)
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
-
- # the number of eventqs are set based
- # on experiments with few benchmarks
-
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus):
-
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
- self.createCPUThreads(self.cpu)
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.timingCpu = [TimingSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.timingCpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createMemoryControllersDDR3(self):
- self._createMemoryControllers(1, DDR3_1600_8x8)
-
- def _createMemoryControllers(self, num, cls):
- intlv_bits = int(math.log(num, 2))
- mem_ctrls = []
- for i in range(num):
- interface = cls()
- interface.range = AddrRange(self.mem_ranges[0].start,
- size = self.mem_ranges[0].size(),
- intlvHighBit = 7,
- xorHighBit = 20,
- intlvBits = intlv_bits,
- intlvMatch = i)
- ctrl = MemCtrl()
- ctrl.dram = interface
- mem_ctrls.append(ctrl)
- self.mem_cntrls = mem_ctrls
-
- def initFS(self, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # North Bridge
- self.iobus = IOXBar()
-
- # connect the io bus
- # Note: pass in a reference to where Ruby will connect to in the future
- # so the port isn't connected twice.
- self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/parsec/configs/run_parsec.py b/src/parsec/configs/run_parsec.py
deleted file mode 100644
index 5dac66d..0000000
--- a/src/parsec/configs/run_parsec.py
+++ /dev/null
@@ -1,209 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2019 The Regents of the University of California.
-# All rights reserved.
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-""" Script to run PARSEC benchmarks with gem5.
- The script expects kernel, diskimage, cpu (kvm or timing),
- benchmark, benchmark size, and number of cpu cores as arguments.
- This script is best used if your disk-image has workloads tha have
- ROI annotations compliant with m5 utility. You can use the script in
- ../disk-images/parsec/ with the parsec-benchmark repo at
- https://github.com/darchr/parsec-benchmark.git to create a working
- disk-image for this script.
-"""
-import argparse
-import time
-import m5
-import m5.ticks
-from m5.objects import *
-
-from system import *
-
-supported_cpu_types = ["kvm", "timing"]
-benchmark_choices = ["blackscholes", "bodytrack", "canneal", "dedup",
- "facesim", "ferret", "fluidanimate", "freqmine",
- "raytrace", "streamcluster", "swaptions", "vips", "x264"]
-size_choices=["simsmall", "simmedium", "simlarge"]
-
-
-def parse_options():
-
- parser = argparse.ArgumentParser(description='For use with gem5. This '
- 'runs a NAS Parallel Benchmark application. This only works '
- 'with x86 ISA.')
-
- parser.add_argument("kernel", type=str,
- help="Path to the kernel binary to boot")
- parser.add_argument("disk", type=str, help="Path to the PARSEC disk image")
- parser.add_argument("cpu", type=str, choices=supported_cpu_types,
- help="The type of CPU to use in the system")
- parser.add_argument("benchmark", type=str, choices=benchmark_choices,
- help="The PARSEC benchmark application to run")
- parser.add_argument("size", type=str, choices=size_choices,
- help="The input size to the PARSEC benchmark "
- "application")
- parser.add_argument("num_cpus", type=int, choices=[1,2,8],
- help="The number of CPU cores")
-
- return parser.parse_args()
-
-def writeBenchScript(dir, bench, size, num_cpus):
- """
- This method creates a script in dir which will be eventually
- passed to the simulated system (to run a specific benchmark
- at bootup).
- """
- file_name = '{}/run_{}'.format(dir, bench)
- bench_file = open(file_name, 'w+')
- bench_file.write('cd /home/gem5/parsec-benchmark\n')
- bench_file.write('source env.sh\n')
- bench_file.write('parsecmgmt -a run -p \
- {} -c gcc-hooks -i {} -n {}\n'.format(bench, size, num_cpus))
-
- # sleeping for sometime makes sure
- # that the benchmark's output has been
- # printed to the console
- bench_file.write('sleep 5 \n')
- bench_file.write('m5 exit \n')
- bench_file.close()
- return file_name
-
-if __name__ == "__m5_main__":
-
- args = parse_options()
-
- # create the system
- system = MySystem(args.kernel, args.disk, args.cpu, args.num_cpus)
-
- # Exit from guest on workbegin/workend
- system.exit_on_work_items = True
-
- # Create and pass a script to the simulated system to run the reuired
- # benchmark
- system.readfile = writeBenchScript(m5.options.outdir, args.benchmark,
- args.size, args.num_cpus)
-
- # set up the root SimObject and start the simulation
- root = Root(full_system = True, system = system)
-
- if system.getHostParallel():
- # Required for running kvm on multiple host cores.
- # Uses gem5's parallel event queue feature
- # Note: The simulator is quite picky about this number!
- root.sim_quantum = int(1e9) # 1 ms
-
- #needed for long running jobs
- m5.disableAllListeners()
-
- # instantiate all of the objects we've created above
- m5.instantiate()
-
- globalStart = time.time()
-
- print("Running the simulation")
- print("Using cpu: {}".format(args.cpu))
-
- start_tick = m5.curTick()
- end_tick = m5.curTick()
- start_insts = system.totalInsts()
- end_insts = system.totalInsts()
- m5.stats.reset()
-
- exit_event = m5.simulate()
-
- if exit_event.getCause() == "workbegin":
- print("Done booting Linux")
- # Reached the start of ROI
- # start of ROI is marked by an
- # m5_work_begin() call
- print("Resetting stats at the start of ROI!")
- m5.stats.reset()
- start_tick = m5.curTick()
- start_insts = system.totalInsts()
- # switching to timing cpu if argument cpu == timing
- if args.cpu == 'timing':
- system.switchCpus(system.cpu, system.detailedCpu)
- else:
- print("Unexpected termination of simulation!")
- print()
- m5.stats.dump()
- end_tick = m5.curTick()
- end_insts = system.totalInsts()
- m5.stats.reset()
- print("Performance statistics:")
-
- print("Simulated time: %.2fs" % ((end_tick-start_tick)/1e12))
- print("Instructions executed: %d" % ((end_insts-start_insts)))
- print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
- print("Total wallclock time: %.2fs, %.2f min" % \
- (time.time()-globalStart, (time.time()-globalStart)/60))
- exit()
-
- # Simulate the ROI
- exit_event = m5.simulate()
-
- # Reached the end of ROI
- # Finish executing the benchmark with kvm cpu
- if exit_event.getCause() == "workend":
- # Reached the end of ROI
- # end of ROI is marked by an
- # m5_work_end() call
- print("Dump stats at the end of the ROI!")
- m5.stats.dump()
- end_tick = m5.curTick()
- end_insts = system.totalInsts()
- m5.stats.reset()
- # switching to timing cpu if argument cpu == timing
- if args.cpu == 'timing':
- system.switchCpus(system.timingCpu, system.cpu)
- else:
- print("Unexpected termination of simulation!")
- print()
- m5.stats.dump()
- end_tick = m5.curTick()
- end_insts = system.totalInsts()
- m5.stats.reset()
- print("Performance statistics:")
-
- print("Simulated time: %.2fs" % ((end_tick-start_tick)/1e12))
- print("Instructions executed: %d" % ((end_insts-start_insts)))
- print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
- print("Total wallclock time: %.2fs, %.2f min" % \
- (time.time()-globalStart, (time.time()-globalStart)/60))
- exit()
-
- # Simulate the remaning part of the benchmark
- exit_event = m5.simulate()
-
- print("Done with the simulation")
- print()
- print("Performance statistics:")
-
- print("Simulated time in ROI: %.2fs" % ((end_tick-start_tick)/1e12))
- print("Instructions executed in ROI: %d" % ((end_insts-start_insts)))
- print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
- print("Total wallclock time: %.2fs, %.2f min" % \
- (time.time()-globalStart, (time.time()-globalStart)/60))
diff --git a/src/parsec/configs/system/MESI_Two_Level.py b/src/parsec/configs/system/MESI_Two_Level.py
deleted file mode 100644
index 314f640..0000000
--- a/src/parsec/configs/system/MESI_Two_Level.py
+++ /dev/null
@@ -1,341 +0,0 @@
-#Copyright (c) 2020 The Regents of the University of California.
-#All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MESI TWO Level protocol
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MESITwoLevelCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
- fatal("This system assumes MESI_Two_Level!")
-
- super(MESITwoLevelCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MESI_Two_Level example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU
- # core. The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in \
- range(self._numL2Caches)] + [DirController(self, \
- system.mem_ranges, mem_ctrls)] + [DMAController(self) for i \
- in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # I/D cache is combined and grab from ctrl
- icache = self.controllers[i].L1Icache,
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = \
- self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_ports
- cpu.dtb.walker.port = self.sequencers[i].in_ports
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False)
- self.l2_select_num_bits = int(math.log(num_l2Caches , 2))
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.enable_prefetch = False
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.out_port = ruby_system.network.in_port
-
- self.optionalQueue = MessageBuffer()
-
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getBlockSizeBits(system,
- num_l2Caches))
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
- self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/parsec/configs/system/MI_example_caches.py b/src/parsec/configs/system/MI_example_caches.py
deleted file mode 100644
index a9a171c..0000000
--- a/src/parsec/configs/system/MI_example_caches.py
+++ /dev/null
@@ -1,277 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-""" This file creates a set of Ruby caches, the Ruby network, and a simple
-point-to-point topology.
-See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
-You can change simple_ruby to import from this file instead of from msi_caches
-to use the MI_example protocol instead of MSI.
-
-IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
- also needs to be updated. For now, email Jason <jason@lowepower.com>
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MIExampleSystem(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MI_example':
- fatal("This system assumes MI_example!")
-
- super(MIExampleSystem, self).__init__()
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MI example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # Create one controller for each L1 cache (and the cache mem obj.)
- # Create a single directory controller (Really the memory cntrl)
- self.controllers = \
- [L1Cache(system, self, cpu) for cpu in cpus] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU. In many systems this is more
- # complicated since you have to create sequencers for DMA controllers
- # and other controllers, too.
- self.sequencers = [RubySequencer(version = i,
- # I/D cache is combined and grab from ctrl
- icache = self.controllers[i].cacheMemory,
- dcache = self.controllers[i].cacheMemory,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[0:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = \
- self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_ports
- cpu.dtb.walker.port = self.sequencers[i].in_ports
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu):
- """CPUs are needed to grab the clock domain and system is needed for
- the cache block size.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.cacheMemory = RubyCache(size = '16kB',
- assoc = 8,
- start_index_bit = self.getBlockSizeBits(system))
- self.clk_domain = cpu.clk_domain
- self.send_evictions = self.sendEvicts(cpu)
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromCache = MessageBuffer(ordered = True)
- self.requestFromCache.out_port = ruby_system.network.in_port
- self.responseFromCache = MessageBuffer(ordered = True)
- self.responseFromCache.out_port = ruby_system.network.in_port
- self.forwardToCache = MessageBuffer(ordered = True)
- self.forwardToCache.in_port = ruby_system.network.out_port
- self.responseToCache = MessageBuffer(ordered = True)
- self.responseToCache.in_port = ruby_system.network.out_port
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer(ordered = True)
- self.requestToDir.in_port = ruby_system.network.out_port
- self.dmaRequestToDir = MessageBuffer(ordered = True)
- self.dmaRequestToDir.in_port = ruby_system.network.out_port
-
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.dmaResponseFromDir = MessageBuffer(ordered = True)
- self.dmaResponseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/parsec/configs/system/MOESI_CMP_directory.py b/src/parsec/configs/system/MOESI_CMP_directory.py
deleted file mode 100644
index f24022a..0000000
--- a/src/parsec/configs/system/MOESI_CMP_directory.py
+++ /dev/null
@@ -1,351 +0,0 @@
-#Copyright (c) 2020 The Regents of the University of California.
-#All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MOESI CMP directory
-protocol.
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MOESICMPDirCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
- fatal("This system assumes MOESI_CMP_directory!")
-
- super(MOESICMPDirCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MOESI_CMP_directory example uses 3 virtual networks
- self.number_of_virtual_networks = 3
- self.network.number_of_virtual_networks = 3
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU
- # core. The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in \
- range(self._numL2Caches)] + [DirController(self, \
- system.mem_ranges, mem_ctrls)] + [DMAController(self) for i \
- in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # I/D cache is combined and grab from ctrl
- icache = self.controllers[i].L1Icache,
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_ports
- cpu.dtb.walker.port = self.sequencers[i].in_ports
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getL2StartIdx(system,
- num_l2Caches),
- dataAccessLatency = 20,
- tagAccessLatency = 20)
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getL2StartIdx(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.GlobalRequestFromL2Cache = MessageBuffer()
- self.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
-
- self.GlobalRequestToL2Cache = MessageBuffer()
- self.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.reqToDir = MessageBuffer()
- self.reqToDir.out_port = ruby_system.network.in_port
- self.respToDir = MessageBuffer()
- self.respToDir.out_port = ruby_system.network.in_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/parsec/configs/system/__init__.py b/src/parsec/configs/system/__init__.py
deleted file mode 100644
index 5b02b9a..0000000
--- a/src/parsec/configs/system/__init__.py
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from .system import MySystem
-from .ruby_system import MyRubySystem
-
diff --git a/src/parsec/configs/system/caches.py b/src/parsec/configs/system/caches.py
deleted file mode 100644
index 7d60733..0000000
--- a/src/parsec/configs/system/caches.py
+++ /dev/null
@@ -1,140 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-""" Caches with options for a simple gem5 configuration script
-
-This file contains L1 I/D and L2 caches to be used in the simple
-gem5 configuration script.
-"""
-
-from m5.objects import Cache, L2XBar, StridePrefetcher
-
-# Some specific options for caches
-# For all options see src/mem/cache/BaseCache.py
-
-class PrefetchCache(Cache):
-
- def __init__(self):
- super(PrefetchCache, self).__init__()
- self.prefetcher = StridePrefetcher()
-
-class L1Cache(PrefetchCache):
- """Simple L1 Cache with default values"""
-
- assoc = 8
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 16
- tgts_per_mshr = 20
- writeback_clean = True
-
- def __init__(self):
- super(L1Cache, self).__init__()
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU-side port
- This must be defined in a subclass"""
- raise NotImplementedError
-
-class L1ICache(L1Cache):
- """Simple L1 instruction cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1ICache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU icache port"""
- self.cpu_side = cpu.icache_port
-
-class L1DCache(L1Cache):
- """Simple L1 data cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1DCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU dcache port"""
- self.cpu_side = cpu.dcache_port
-
-class MMUCache(Cache):
- # Default parameters
- size = '8kB'
- assoc = 4
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(MMUCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect the CPU itb and dtb to the cache
- Note: This creates a new crossbar
- """
- self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
-class L2Cache(PrefetchCache):
- """Simple L2 Cache with default values"""
-
- # Default parameters
- size = '256kB'
- assoc = 16
- tag_latency = 10
- data_latency = 10
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(L2Cache, self).__init__()
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
diff --git a/src/parsec/configs/system/fs_tools.py b/src/parsec/configs/system/fs_tools.py
deleted file mode 100644
index 9e49ce7..0000000
--- a/src/parsec/configs/system/fs_tools.py
+++ /dev/null
@@ -1,36 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
-
-class CowDisk(IdeDisk):
-
- def __init__(self, filename):
- super(CowDisk, self).__init__()
- self.driveID = 'device0'
- self.image = CowDiskImage(child=RawDiskImage(read_only=True),
- read_only=False)
- self.image.child.image_file = filename
diff --git a/src/parsec/configs/system/ruby_system.py b/src/parsec/configs/system/ruby_system.py
deleted file mode 100644
index 3959a71..0000000
--- a/src/parsec/configs/system/ruby_system.py
+++ /dev/null
@@ -1,228 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-
-
-class MyRubySystem(System):
-
- def __init__(self, kernel, disk, cpu_type, mem_sys, num_cpus):
- super(MyRubySystem, self).__init__()
-
- self._host_parallel = cpu_type == "kvm"
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- self.initFS(num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(cpu_type, num_cpus)
-
- self.createMemoryControllersDDR3()
-
- # Create the cache hierarchy for the system.
- if mem_sys == 'MI_example':
- from .MI_example_caches import MIExampleSystem
- self.caches = MIExampleSystem()
- elif mem_sys == 'MESI_Two_Level':
- from .MESI_Two_Level import MESITwoLevelCache
- self.caches = MESITwoLevelCache()
- elif mem_sys == 'MOESI_CMP_directory':
- from .MOESI_CMP_directory import MOESICMPDirCache
- self.caches = MOESICMPDirCache()
- self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports],
- self.iobus)
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPU(self, cpu_type, num_cpus):
- if cpu_type == "atomic":
- self.cpu = [AtomicSimpleCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.mem_mode = 'atomic'
- elif cpu_type == "kvm":
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
- elif cpu_type == "o3":
- self.cpu = [DerivO3CPU(cpu_id = i)
- for i in range(num_cpus)]
- self.mem_mode = 'timing'
- elif cpu_type == "simple":
- self.cpu = [TimingSimpleCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.mem_mode = 'timing'
- else:
- m5.fatal("No CPU type {}".format(cpu_type))
-
- for cpu in self.cpu:
- cpu.createThreads()
- cpu.createInterruptController()
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createMemoryControllersDDR3(self):
- self._createMemoryControllers(1, DDR3_1600_8x8)
-
- def _createMemoryControllers(self, num, cls):
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = self.mem_ranges[0]))
- for i in range(num)
- ]
-
- def initFS(self, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # North Bridge
- self.iobus = IOXBar()
-
- # connect the io bus
- # Note: pass in a reference to where Ruby will connect to in the future
- # so the port isn't connected twice.
- self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/parsec/configs/system/system.py b/src/parsec/configs/system/system.py
deleted file mode 100644
index 09030c2..0000000
--- a/src/parsec/configs/system/system.py
+++ /dev/null
@@ -1,331 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-from .caches import *
-
-class MySystem(System):
-
- def __init__(self, kernel, disk, cpu_type, num_cpus, no_kvm = False):
- super(MySystem, self).__init__()
-
- self._no_kvm = no_kvm
- self._host_parallel = cpu_type == "kvm"
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- # Create the main memory bus
- # This connects to main memory
- self.membus = SystemXBar(width = 64) # 64-byte width
- self.membus.badaddr_responder = BadAddr()
- self.membus.default = Self.badaddr_responder.pio
-
- # Set up the system port for functional access from the simulator
- self.system_port = self.membus.cpu_side_ports
-
- self.initFS(self.membus, num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(cpu_type, num_cpus)
-
- # Create the cache heirarchy for the system.
- self.createCacheHierarchy()
-
- # Set up the interrupt controllers for the system (x86 specific)
- self.setupInterrupts()
-
- self.createMemoryControllersDDR3()
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPU(self, cpu_type, num_cpus):
- # set up a kvm core or an atomic core to boot
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.mem_mode = 'atomic'
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- for cpu in self.cpu:
- cpu.createThreads()
-
- # set up the detailed cpu or a kvm model with more cores
- if cpu_type == "atomic":
- self.detailedCpu = [AtomicSimpleCPU(cpu_id = i, switched_out = True)
- for i in range(num_cpus)]
- elif cpu_type == "kvm":
- # Note KVM needs a VM and atomic_noncaching
- self.detailedCpu = [X86KvmCPU(cpu_id = i, switched_out = True)
- for i in range(num_cpus)]
- self.kvm_vm = KvmVM()
- elif cpu_type == "o3":
- self.detailedCpu = [DerivO3CPU(cpu_id = i, switched_out = True)
- for i in range(num_cpus)]
- elif cpu_type == "simple" or cpu_type == "timing":
- self.detailedCpu = [TimingSimpleCPU(cpu_id = i, switched_out = True)
- for i in range(num_cpus)]
- else:
- m5.fatal("No CPU type {}".format(cpu_type))
-
- for cpu in self.detailedCpu:
- cpu.createThreads()
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createCacheHierarchy(self):
- for cpu in self.cpu:
- # Create a memory bus, a coherent crossbar, in this case
- cpu.l2bus = L2XBar()
-
- # Create an L1 instruction and data cache
- cpu.icache = L1ICache()
- cpu.dcache = L1DCache()
- cpu.mmucache = MMUCache()
-
- # Connect the instruction and data caches to the CPU
- cpu.icache.connectCPU(cpu)
- cpu.dcache.connectCPU(cpu)
- cpu.mmucache.connectCPU(cpu)
-
- # Hook the CPU ports up to the l2bus
- cpu.icache.connectBus(cpu.l2bus)
- cpu.dcache.connectBus(cpu.l2bus)
- cpu.mmucache.connectBus(cpu.l2bus)
-
- # Create an L2 cache and connect it to the l2bus
- cpu.l2cache = L2Cache()
- cpu.l2cache.connectCPUSideBus(cpu.l2bus)
-
- # Connect the L2 cache to the L3 bus
- cpu.l2cache.connectMemSideBus(self.membus)
-
- def setupInterrupts(self):
- for cpu in self.cpu:
- # create the interrupt controller CPU and connect to the membus
- cpu.createInterruptController()
-
- # For x86 only, connect interrupts to the memory
- # Note: these are directly connected to the memory bus and
- # not cached
- cpu.interrupts[0].pio = self.membus.mem_side_ports
- cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
- cpu.interrupts[0].int_responder = self.membus.mem_side_ports
-
-
- def createMemoryControllersDDR3(self):
- self._createMemoryControllers(1, DDR3_1600_8x8)
-
- def _createMemoryControllers(self, num, cls):
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = self.mem_ranges[0]),
- port = self.membus.mem_side_ports)
- for i in range(num)
- ]
-
- def initFS(self, membus, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # Constants similar to x86_traits.hh
- IO_address_space_base = 0x8000000000000000
- pci_config_address_space_base = 0xc000000000000000
- interrupts_address_space_base = 0xa000000000000000
- APIC_range_size = 1 << 12
-
- # North Bridge
- self.iobus = IOXBar()
- self.bridge = Bridge(delay='50ns')
- self.bridge.mem_side_port = self.iobus.cpu_side_ports
- self.bridge.cpu_side_port = membus.mem_side_ports
- # Allow the bridge to pass through:
- # 1) kernel configured PCI device memory map address: address range
- # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
- # 2) the bridge to pass through the IO APIC (two pages, already
- # contained in 1),
- # 3) everything in the IO address range up to the local APIC, and
- # 4) then the entire PCI address space and beyond.
- self.bridge.ranges = \
- [
- AddrRange(0xC0000000, 0xFFFF0000),
- AddrRange(IO_address_space_base,
- interrupts_address_space_base - 1),
- AddrRange(pci_config_address_space_base,
- Addr.max)
- ]
-
- # Create a bridge from the IO bus to the memory bus to allow access
- # to the local APIC (two pages)
- self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
- self.apicbridge.mem_side_port = membus.cpu_side_ports
- self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
- interrupts_address_space_base +
- cpus * APIC_range_size
- - 1)]
-
- # connect the io bus
- self.pc.attachIO(self.iobus)
-
- # Add a tiny cache to the IO bus.
- # This cache is required for the classic memory model for coherence
- self.iocache = Cache(assoc=8,
- tag_latency = 50,
- data_latency = 50,
- response_latency = 50,
- mshrs = 20,
- size = '1kB',
- tgts_per_mshr = 12,
- addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.mem_side_ports
- self.iocache.mem_side = self.membus.cpu_side_ports
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/riscv-boot-exit-nodisk/README.md b/src/riscv-boot-exit-nodisk/README.md
new file mode 100644
index 0000000..a325891
--- /dev/null
+++ b/src/riscv-boot-exit-nodisk/README.md
@@ -0,0 +1,264 @@
+---
+title: RISC-V full system with no disk
+tags:
+ - riscv
+ - fullsystem
+ - nodisk
+layout: default
+permalink: resources/riscv-fs-nodisk
+shortdoc: >
+ Resources to build a riscv bootloader containing a linux kernel and a workload expected to run at early userspace.
+author: ["Hoa Nguyen"]
+---
+
+This resource provides the possibility of conducting a RISC-V full system
+simulation without a block device by leveraging
+[Linux's userspace support] (https://www.kernel.org/doc/html/latest/driver-api/early-userspace/early_userspace_support.html).
+
+# Overview
+
+This document provides instructions to create a RISCV bootloader
+(`berkeley bootloader (bbl)`) and also points to the associated gem5 scripts to
+run riscv Linux full system simulations without using a disk image. The
+bootloader `bbl` is compiled with a Linux kernel, a device tree, and a
+workload. Similar to the `riscv-fs` resource, we'll also rely on
+[BusyBox](https://www.busybox.net/) for basic Linux utilities, on
+`UCanLinux` for the configuration of the Linux kernel and the configuration of
+BusyBox, and on `riscv-pk` for building a proxy kernel.
+
+```
+riscv-fs-nodisk/
+ |___ gem5/ # gem5 source code (to be cloned here)
+ |
+ |___ riscv-gnu-toolchain/ # riscv tool chain for cross compilation
+ |
+ |___ riscv64-sample/ # UCanLinux source
+ |
+ |___ linux/ # linux source
+ |
+ |___ busybox/ # busybox source
+ |
+ |___ riscv-pk/ # riscv proxy kernel source (bbl)
+ |
+ |___ cpio/ # contains the .cpio files
+ |
+ |___ initdir/ # contains the structure of initramfs
+ |
+ |___ configs/
+ | |___ system # gem5 system config files
+ | |___ run_riscv.py # gem5 run script
+ |
+ |___ README.md # This README file
+```
+
+# How does it work?
+
+When Linux kernel booting process takes place, `initramfs`, a root filesystem
+embedded into the kernel, will be loaded to memory. When `initramfs` is loaded,
+the kernel will try to execute one of the following scripts located in that
+filesystem,
+[{`/init, /sbin/init, /etc/init, /bin/init, /bin/sh`}](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/init/main.c?h=v5.10&id=2c85ebc57b3e1817b6ce1a6b703928e113a90442#n1467).
+Instead of using the default `/init` script, we will use our version of `/init`
+to execute the desired workload right after the early userspace is loaded.
+
+**Note:** Since the `initramfs` decompressing process takes place while
+Linux kernel is booting (which means it will happen *during* the full system
+simulation), we'll try to minimize the size of the `initramfs`.
+
+# Building the resource
+## Step 1. Building the `riscv-gnu-toolchain`
+In this step, we'll use
+[GNU toolchain for RISC-V](https://github.com/riscv-collab/riscv-gnu-toolchain).
+
+This step is necessary if you do not have basic libraries built for RISCV or
+if you're cross-compiling RISCV.
+
+```sh
+cd riscv-fs-nodisk/
+git clone https://github.com/riscv-collab/riscv-gnu-toolchain --recursive
+cd riscv-gnu-toolchain
+git checkout 1a36b5dc44d71ab6a583db5f4f0062c2a4ad963b
+# --prefix parameter specifying the installation location
+./configure --prefix=/opt/riscv
+make linux -j $(nproc)
+```
+
+To update the PATH environment variable so that the RISCV compilers can be
+found,
+```sh
+export PATH=$PATH:/opt/riscv/bin/
+```
+
+## Step 2. Getting the `UCanLinux` Source
+This repo contains a Linux configuration for RISCV at
+`riscv64-sample/kernel.config` and a BusyBox configuration at
+`riscv64-sample/busybox.config`.
+
+```sh
+# going back to base riscv-fs directory
+cd riscv-fs-nodisk/
+git clone https://github.com/UCanLinux/riscv64-sample
+```
+
+## Step 3. Getting and Building `busybox`
+More information about Busybox is [here](https://www.busybox.net/).
+```sh
+cd riscv-fs-nodisk/
+git clone git://busybox.net/busybox.git
+cd busybox
+git checkout 1_34_stable # checkout the a stable branch
+cp ../riscv64-sample/busybox.config .config
+yes "" | make CROSS_COMPILE=riscv64-unknown-linux-gnu- oldconfig
+make CROSS_COMPILE=riscv64-unknown-linux-gnu- all -j$(nproc)
+make CROSS_COMPILE=riscv64-unknown-linux-gnu- install
+```
+The files of interest are in `busybox/_install/bin`.
+
+## Step 4. Getting and Compiling the `Linux kernel`
+We'll compiling the Linux kernel to get the `linux/usr/gen_init_cpio`, which
+would be used later.
+```sh
+cd riscv-fs-nodisk/
+git clone --depth 1 --branch v5.10 https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
+cd linux
+cp ../riscv64-sample/kernel.config .config
+yes "" | make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- oldconfig
+make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- menuconfig
+# Go to "General setup --->"
+# Check on "Initial RAM filesystem and RAM disk (initramfs/initrd) support"
+make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- all -j $(nproc)
+```
+
+## Step 5. Compiling the Workload (e.g. gem5's m5)
+```sh
+cd riscv-fs-nodisk/
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5/util/m5
+scons build/riscv/out/m5
+```
+
+**Note**: the default cross-compiler is `riscv64-unknown-linux-gnu-`.
+To change the cross-compiler, you can set the cross-compiler using the scons
+sticky variable `riscv.CROSS_COMPILE`. For example,
+```sh
+scons riscv.CROSS_COMPILE=riscv64-linux-gnu- build/riscv/out/m5
+```
+
+## Step 6. Determining the Structure of `initramfs`
+```sh
+cd riscv-fs-nodisk/
+mkdir cpio
+mkdir misc
+mkdir initdir
+```
+### Userspace
+We'll use the `riscv64-sample/initdir` to define the structure of `initramfs`.
+```sh
+cd riscv-fs-nodisk/initdir
+cp -r ../busybox/_install/bin/ .
+mkdir lib
+cp /opt/riscv/sysroot/lib/ld-linux-riscv64-lp64d.so.1 lib/ # busybox' dependency
+cp /opt/riscv/sysroot/lib/libc.so.6 lib/ # busybox' dependency
+cp /opt/riscv/sysroot/lib/libm.so.6 lib/ # busybox' dependency
+cp /opt/riscv/sysroot/lib/libresolv.so.2 lib/ # busybox' dependency
+mkdir proc
+mkdir sys
+mkdir sbin
+cp ../gem5/util/m5/build/riscv/out/m5 sbin/m5 # replace m5 by the desired workload
+```
+
+Create `initdir/init` script with the following content,
+```
+#!/bin/busybox sh
+
+exec /sbin/init # script to execute the workload
+```
+
+Create `initdir/sbin/init` script with the following content,
+```
+#!/bin/busybox sh
+
+/sbin/m5 exit
+```
+
+Make the scripts executable,
+```sh
+chmod +x init
+chmod +x sbin/init
+```
+
+To create the cpio file of the `initdir` folder,
+```sh
+cd riscv-fs-nodisk/linux
+usr/gen_initramfs.sh -o ../cpio/disk.cpio ../initdir/
+lsinitramfs ../cpio/disk.cpio # checking the file structure of the created cpio file
+```
+
+### `/dev/` folder
+By default, `initramfs` would have a `/dev/console` and `/dev/tty`. Without
+these devices, we cannot see what is written to `stdout` and `stderr`.
+
+The following commands will build a `.cpio` file with `/dev/console` and
+`/dev/tty`,
+```sh
+cd riscv-fs-nodisk/misc
+mkdir dev
+fakeroot -- mknod -m 622 dev/console c 5 1
+fakeroot -- mknod -m 622 dev/tty c 5 0
+fakeroot -- mknod -m 622 dev/ttyprintk c 5 3
+fakeroot -- mknod -m 622 dev/null c 1 3
+fakeroot -- find . -print0 | cpio --owner root:root --null -o --format=newc > ../cpio/dev.cpio
+cd ../
+rm -r misc
+```
+**Note:** `mknod -m 622 /dev/tty c 5 0` means we're creating `/dev/tty` with
+permission of `622`. `c` means a character device being created, `5` is the
+major number, and `0` is the minor number. More information about the
+major/minor numbering is available at
+(https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/admin-guide/devices.txt).
+
+### Merging .cpio files to a single .cpio file
+```sh
+cd riscv-fs-nodisk/cpio
+cat disk.cpio dev.cpio > init.cpio
+```
+
+## Step 7. Compiling `Linux Kernel` with a customized `initramfs`
+```sh
+cd riscv-fs-nodisk/linux
+make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- menuconfig
+# Go to "General setup --->"
+# Check on "Initial RAM filesystem and RAM disk (initramfs/initrd) support"
+# Change "Initramfs source file(s)" to the absoblute path of riscv-fs-nodisk/cpio/init.cpio
+make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- all -j $(nproc)
+```
+
+The file of interest is at `arch/riscv/boot/Image`.
+
+## Step 8. Compiling `bbl` with the Linux kernel as the payload
+```sh
+cd riscv-fs-nodisk/
+git clone https://github.com/riscv/riscv-pk.git
+cd riscv-pk
+mkdir build
+cd build
+
+# configure bbl build
+../configure --host=riscv64-unknown-linux-gnu --with-payload=../../linux/arch/riscv/boot/Image --prefix=/opt/riscv/
+
+make -j$(nproc)
+
+chmod 755 bbl
+
+riscv64-unknown-linux-gnu-strip bbl
+cp bbl bbl-m5-exit
+```
+
+The desired bootloader is file is at `riscv-fs-nodisk/riscv-pk/build/bbl` or
+`riscv-fs-nodisk/riscv-pk/build/bbl-m5-exit`.
+
+
+## Example
+```sh
+gem5/build/RISCV/gem5.opt configs/run_riscv.py bbl-m5-exit atomic 1
+```
diff --git a/src/riscv-boot-exit-nodisk/configs/riscv_fs.py b/src/riscv-boot-exit-nodisk/configs/riscv_fs.py
new file mode 100644
index 0000000..faf427a
--- /dev/null
+++ b/src/riscv-boot-exit-nodisk/configs/riscv_fs.py
@@ -0,0 +1,133 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This example runs a simple linux boot.
+
+Characteristics
+---------------
+
+* Runs exclusively on the RISC-V ISA with the classic caches
+* Assumes that the kernel and the workload are compiled into the bootloader
+* Automatically generates the DTB file
+* Automatically executes `m5 exit` when booting is done
+"""
+
+import m5
+from m5.objects import Root
+
+from gem5.runtime import get_runtime_isa
+from gem5.components.boards.riscv_board import RiscvBoard
+from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.isas import ISA
+from gem5.utils.requires import requires
+from gem5.resources.resource import Resource, CustomResource
+
+import argparse
+
+def parse_options():
+ parser = argparse.ArgumentParser(
+ description="Full System Linux booting without disk image")
+
+ parser.add_argument("--bbl", default=None,
+ help="Path to the bbl binary with a Linux kernel"
+ " and a workload. Default:"
+ " gem5-resources' bbl-boot-exit-nodisk")
+
+ parser.add_argument("--cpu-type", required=True, help="CPU Type")
+
+ parser.add_argument("--num-cpus", type=int, required=True,
+ help="Number of CPU cores")
+
+ return parser.parse_args()
+
+if __name__ == "__m5_main__":
+
+ args = parse_options()
+ cpu = None
+ if args.cpu_type == "atomic":
+ cpu = CPUTypes.ATOMIC
+ elif args.cpu_type == "timing":
+ cpu = CPUTypes.TIMING
+ elif args.cpu_type == "o3":
+ cpu = CPUTypes.O3
+ else:
+ assert(False, "The CPU type must be one of: {atomic, timing, o3}")
+
+ bbl = CustomResource(args.bbl) if args.bbl else Resource('riscv-boot-exit-nodisk')
+
+ # Run a check to ensure the right version of gem5 is being used.
+ requires(isa_required=ISA.RISCV)
+
+ from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy \
+ import (
+ PrivateL1PrivateL2CacheHierarchy,
+ )
+
+ # Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been tested.
+ cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+ l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
+ )
+
+ # Setup the system memory.
+ memory = SingleChannelDDR3_1600()
+
+ # Setup a single core Processor.
+ processor = SimpleProcessor(cpu_type=cpu, num_cores=1)
+
+ # Setup the board.
+ board = RiscvBoard(
+ clk_freq="1GHz",
+ processor=processor,
+ memory=memory,
+ cache_hierarchy=cache_hierarchy,
+ use_disk_image=False
+ )
+
+ board.connect_things()
+
+ # Set the Full System workload.
+ board.set_workload(
+ disk_image=None,
+ bootloader=bbl,
+ kernel_boot_params = "console=ttyS0"
+ )
+
+ root = Root(full_system=True, system=board)
+
+ m5.instantiate()
+
+ print("Beginning simulation!")
+ # Note: You can access the terminal upon boot using
+ # m5term (`./util/term`): `./m5term localhost <port>`. Note the `<port>`
+ # value is obtained from the gem5 terminal stdout. Look out for
+ # "system.platform.terminal: Listening for connections on port <port>".
+ exit_event = m5.simulate()
+ print(
+ "Exiting @ tick {} because {}.".format(m5.curTick(), exit_event.getCause())
+ )
diff --git a/src/riscv-fs/configs/system/system.py b/src/riscv-fs/configs/system/system.py
index 3f545f1..85d162d 100755
--- a/src/riscv-fs/configs/system/system.py
+++ b/src/riscv-fs/configs/system/system.py
@@ -119,6 +119,9 @@
# Create the memory controller
self.createMemoryControllerDDR3()
+ # Set number of CPU cores
+ self.platform.setNumCores(num_cpus)
+
self.setupInterrupts()
# using RiscvLinux as the base full system workload
diff --git a/src/riscv-tests/README.md b/src/riscv-tests/README.md
index 570e4e4..d3ce2d1 100644
--- a/src/riscv-tests/README.md
+++ b/src/riscv-tests/README.md
@@ -55,7 +55,7 @@
A test program for RISC-V is written within a single assembly language file,
which is passed through the C preprocessor, and all regular assembly
directives can be used. An example test program is shown below. Each test
-program should first include the `riscv test.h` header file, which defines the
+program should first include the `riscv_test.h` header file, which defines the
macros used by the TVM. The header file will have different contents depending
on the target environment for which the test will be built. One of the goals
of the various TVMs is to allow the same test program to be compiled and run
diff --git a/src/riscv-tests/benchmarks/Makefile b/src/riscv-tests/benchmarks/Makefile
index cc32714..c9469e2 100644
--- a/src/riscv-tests/benchmarks/Makefile
+++ b/src/riscv-tests/benchmarks/Makefile
@@ -37,7 +37,7 @@
RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
-RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf
+RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns
RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
diff --git a/src/riscv-tests/benchmarks/common/test.ld b/src/riscv-tests/benchmarks/common/test.ld
index 679c4ba..a50b017 100644
--- a/src/riscv-tests/benchmarks/common/test.ld
+++ b/src/riscv-tests/benchmarks/common/test.ld
@@ -28,6 +28,7 @@
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
+ . = ALIGN(0x1000);
.text : { *(.text) }
/* data segment */
diff --git a/src/riscv-tests/benchmarks/pmp/pmp.c b/src/riscv-tests/benchmarks/pmp/pmp.c
index 2ccd769..ec07e4a 100644
--- a/src/riscv-tests/benchmarks/pmp/pmp.c
+++ b/src/riscv-tests/benchmarks/pmp/pmp.c
@@ -8,6 +8,7 @@
#include "util.h"
volatile int trap_expected;
+volatile int granule;
#define INLINE inline __attribute__((always_inline))
@@ -55,8 +56,6 @@
return va - SCRATCH + (uintptr_t)scratch;
}
-#define GRANULE (1UL << PMP_SHIFT)
-
typedef struct {
uintptr_t cfg;
uintptr_t a0;
@@ -85,14 +84,14 @@
p.a1 = p.a0 + range;
}
- p.a0 *= GRANULE;
- p.a1 *= GRANULE;
+ p.a0 *= granule;
+ p.a1 *= granule;
addr = va2pa(addr);
uintptr_t hits = 0;
- for (uintptr_t i = 0; i < size; i += GRANULE) {
+ for (uintptr_t i = 0; i < size; i += granule) {
if (p.a0 <= addr + i && addr + i < p.a1)
- hits += GRANULE;
+ hits += granule;
}
return hits == 0 || hits >= size;
@@ -126,7 +125,7 @@
INLINE void test_range_once(pmpcfg_t p, uintptr_t base, uintptr_t range)
{
- for (uintptr_t addr = base; addr < base + range; addr += GRANULE)
+ for (uintptr_t addr = base; addr < base + range; addr += granule)
test_all_sizes(p, addr);
}
@@ -153,7 +152,7 @@
INLINE pmpcfg_t set_pmp_napot(uintptr_t base, uintptr_t range)
{
pmpcfg_t p;
- p.cfg = PMP_R | (range > GRANULE ? PMP_NAPOT : PMP_NA4);
+ p.cfg = PMP_R | (range > granule ? PMP_NAPOT : PMP_NA4);
p.a0 = 0;
p.a1 = (base + (range/2 - 1)) >> PMP_SHIFT;
return set_pmp(p);
@@ -172,18 +171,33 @@
static void test_ranges(uintptr_t addr, uintptr_t size)
{
- for (uintptr_t range = GRANULE; range <= size; range += GRANULE)
+ for (uintptr_t range = granule; range <= size; range += granule)
test_range(addr, range);
}
static void exhaustive_test(uintptr_t addr, uintptr_t size)
{
- for (uintptr_t base = addr; base < addr + size; base += GRANULE)
+ for (uintptr_t base = addr; base < addr + size; base += granule)
test_ranges(base, size - (base - addr));
}
+static void detect_granule()
+{
+ write_csr(pmpcfg0, NULL);
+ write_csr(pmpaddr0, 0xffffffffffffffffULL);
+ uintptr_t ret = read_csr(pmpaddr0);
+ int g = 2;
+ for(uintptr_t i = 1; i; i<<=1) {
+ if((ret & i) != 0)
+ break;
+ g++;
+ }
+ granule = 1UL << g;
+}
+
int main()
{
+ detect_granule();
init_pt();
const int max_exhaustive = 32;
diff --git a/src/riscv-tests/debug/Makefile b/src/riscv-tests/debug/Makefile
index 3efdea8..06f7d9d 100644
--- a/src/riscv-tests/debug/Makefile
+++ b/src/riscv-tests/debug/Makefile
@@ -4,16 +4,19 @@
src_dir ?= .
GDBSERVER_PY = $(src_dir)/gdbserver.py
TESTS = $(shell $(GDBSERVER_PY) --list-tests $(src_dir)/targets/RISC-V/spike32.py)
+MULTI_TESTS = $(shell $(GDBSERVER_PY) --list-tests $(src_dir)/targets/RISC-V/spike32.py | \
+ grep -i multi)
default: spike$(XLEN) spike$(XLEN)-2
-all-tests: spike32 spike32-2 spike32-2-rtos spike32-2-hwthread \
- spike64 spike64-2 spike64-2-rtos spike64-2-hwthread
+all-tests: spike32 spike-multi-limited spike32-2 spike32-2-hwthread \
+ spike64 spike64-2 spike64-2-hwthread
+
+slow-tests: spike-multi all-tests
all: pylint all-tests
run.%:
- echo $@
$(GDBSERVER_PY) \
$(src_dir)/targets/RISC-V/$(word 2, $(subst ., ,$@)).py \
$(word 3, $(subst ., ,$@)) \
@@ -23,11 +26,14 @@
--server_cmd $(RISCV)/bin/openocd
# Target to check all the multicore options.
-multi-tests: spike32-2 spike64-2-rtos spike32-2-hwthread
+multi-tests: spike32-2 spike32-2-hwthread
pylint:
pylint --rcfile=pylint.rc `git ls-files '*.py'`
+spike-multi-limited: $(foreach test, $(MULTI_TESTS), run.spike-multi.$(test))
+ echo Finished $@
+
spike%: $(foreach test, $(TESTS), run.spike%.$(test))
echo Finished $@
diff --git a/src/riscv-tests/debug/README.md b/src/riscv-tests/debug/README.md
index 6133b6c..7dd6790 100644
--- a/src/riscv-tests/debug/README.md
+++ b/src/riscv-tests/debug/README.md
@@ -9,7 +9,8 @@
Requirements
============
The following should be in the user's path:
-* riscv64-unknown-elf-gcc
+* riscv64-unknown-elf-gcc (`rvv-0.9.x` branch for riscv-gnu-toolchain should
+ work if master does not have vector support yet)
* riscv64-unknown-elf-gdb (can be overridden with `--gdb` when running
gdbserver.py manually), which should be the latest from
git://sourceware.org/git/binutils-gdb.git.
diff --git a/src/riscv-tests/debug/bin/README.md b/src/riscv-tests/debug/bin/README.md
new file mode 100644
index 0000000..7e81515
--- /dev/null
+++ b/src/riscv-tests/debug/bin/README.md
@@ -0,0 +1,7 @@
+This directory contains binaries that are not easy to compile.
+
+RTOSDemo32.axf and RTOSDemo64.axf are created by checking out
+https://github.com/FreeRTOS/FreeRTOS, following the instructions in
+`FreeRTOS/Demo/RISC-V-spike-htif_GCC/README.md`, and building:
+* `make XLEN=32 BASE_ADDRESS=0x10000000`
+* `make XLEN=64 BASE_ADDRESS=0x1212340000`
diff --git a/src/riscv-tests/debug/bin/RTOSDemo32.axf b/src/riscv-tests/debug/bin/RTOSDemo32.axf
new file mode 100644
index 0000000..5fa3fe7
--- /dev/null
+++ b/src/riscv-tests/debug/bin/RTOSDemo32.axf
Binary files differ
diff --git a/src/riscv-tests/debug/bin/RTOSDemo64.axf b/src/riscv-tests/debug/bin/RTOSDemo64.axf
new file mode 100644
index 0000000..bfa2a2a
--- /dev/null
+++ b/src/riscv-tests/debug/bin/RTOSDemo64.axf
Binary files differ
diff --git a/src/riscv-tests/debug/gdbserver.py b/src/riscv-tests/debug/gdbserver.py
index da671d3..3484906 100755
--- a/src/riscv-tests/debug/gdbserver.py
+++ b/src/riscv-tests/debug/gdbserver.py
@@ -8,13 +8,14 @@
import tempfile
import time
import os
+import re
import targets
import testlib
from testlib import assertEqual, assertNotEqual, assertIn, assertNotIn
from testlib import assertGreater, assertRegex, assertLess
from testlib import GdbTest, GdbSingleHartTest, TestFailed
-from testlib import assertTrue, TestNotApplicable
+from testlib import assertTrue, TestNotApplicable, CompileError
MSTATUS_UIE = 0x00000001
MSTATUS_SIE = 0x00000002
@@ -77,6 +78,23 @@
def readable_binary_string(s):
return "".join("%02x" % ord(c) for c in s)
+class InfoTest(GdbTest):
+ def test(self):
+ output = self.gdb.command("monitor riscv info")
+ info = {}
+ for line in output.splitlines():
+ if re.search(r"Found \d+ triggers", line):
+ continue
+ if re.search(r"Disabling abstract command writes to CSRs.", line):
+ continue
+ if re.search(
+ r"keep_alive.. was not invoked in the \d+ ms timelimit.",
+ line):
+ continue
+ k, v = line.strip().split()
+ info[k] = v
+ assertEqual(int(info.get("hart.xlen")), self.hart.xlen)
+
class SimpleRegisterTest(GdbTest):
def check_reg(self, name, alias):
a = random.randrange(1<<self.hart.xlen)
@@ -170,7 +188,7 @@
return self.target.implements_custom_test
def check_custom(self, magic):
- regs = {k: v for k, v in self.gdb.info_registers("all").items()
+ regs = {k: v for k, v in self.gdb.info_registers("all", ops=20).items()
if k.startswith("custom")}
assertEqual(set(regs.keys()),
set(("custom1",
@@ -237,18 +255,25 @@
def test(self):
self.access_test(8, 'long long')
-# FIXME: I'm not passing back invalid addresses correctly in read/write memory.
-#class MemTestReadInvalid(SimpleMemoryTest):
-# def test(self):
-# # This test relies on 'gdb_report_data_abort enable' being executed in
-# # the openocd.cfg file.
-# try:
-# self.gdb.p("*((int*)0xdeadbeef)")
-# assert False, "Read should have failed."
-# except testlib.CannotAccess as e:
-# assertEqual(e.address, 0xdeadbeef)
-# self.gdb.p("*((int*)0x%x)" % self.hart.ram)
-#
+class MemTestReadInvalid(SimpleMemoryTest):
+ def test(self):
+ bad_address = self.hart.bad_address
+ good_address = self.hart.ram + 0x80
+
+ self.write_nop_program(2)
+ self.gdb.p("$s0=0x12345678")
+ self.gdb.p("*((int*)0x%x)=0xabcdef" % good_address)
+ # This test relies on 'gdb_report_data_abort enable' being executed in
+ # the openocd.cfg file.
+ try:
+ self.gdb.p("*((int*)0x%x)" % bad_address)
+ assert False, "Read should have failed."
+ except testlib.CannotAccess as e:
+ assertEqual(e.address, bad_address)
+ self.gdb.stepi() # Don't let gdb cache register read
+ assertEqual(self.gdb.p("*((int*)0x%x)" % good_address), 0xabcdef)
+ assertEqual(self.gdb.p("$s0"), 0x12345678)
+
#class MemTestWriteInvalid(SimpleMemoryTest):
# def test(self):
# # This test relies on 'gdb_report_data_abort enable' being executed in
@@ -569,10 +594,10 @@
self.exit()
class Hwbp1(DebugTest):
- def test(self):
- if self.hart.instruction_hardware_breakpoint_count < 1:
- raise TestNotApplicable
+ def early_applicable(self):
+ return self.hart.instruction_hardware_breakpoint_count > 0
+ def test(self):
if not self.hart.honors_tdata1_hmode:
# Run to main before setting the breakpoint, because startup code
# will otherwise clear the trigger that we set.
@@ -590,11 +615,103 @@
self.gdb.b("_exit")
self.exit()
-class Hwbp2(DebugTest):
- def test(self):
- if self.hart.instruction_hardware_breakpoint_count < 2:
- raise TestNotApplicable
+def MCONTROL_TYPE(xlen):
+ return 0xf<<((xlen)-4)
+def MCONTROL_DMODE(xlen):
+ return 1<<((xlen)-5)
+def MCONTROL_MASKMAX(xlen):
+ return 0x3<<((xlen)-11)
+MCONTROL_SELECT = (1<<19)
+MCONTROL_TIMING = (1<<18)
+MCONTROL_ACTION = (0x3f<<12)
+MCONTROL_CHAIN = (1<<11)
+MCONTROL_MATCH = (0xf<<7)
+MCONTROL_M = (1<<6)
+MCONTROL_H = (1<<5)
+MCONTROL_S = (1<<4)
+MCONTROL_U = (1<<3)
+MCONTROL_EXECUTE = (1<<2)
+MCONTROL_STORE = (1<<1)
+MCONTROL_LOAD = (1<<0)
+
+MCONTROL_TYPE_NONE = 0
+MCONTROL_TYPE_MATCH = 2
+
+MCONTROL_ACTION_DEBUG_EXCEPTION = 0
+MCONTROL_ACTION_DEBUG_MODE = 1
+MCONTROL_ACTION_TRACE_START = 2
+MCONTROL_ACTION_TRACE_STOP = 3
+MCONTROL_ACTION_TRACE_EMIT = 4
+
+MCONTROL_MATCH_EQUAL = 0
+MCONTROL_MATCH_NAPOT = 1
+MCONTROL_MATCH_GE = 2
+MCONTROL_MATCH_LT = 3
+MCONTROL_MATCH_MASK_LOW = 4
+MCONTROL_MATCH_MASK_HIGH = 5
+
+def set_field(reg, mask, val):
+ return ((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))
+
+class HwbpManual(DebugTest):
+ """Make sure OpenOCD behaves "normal" when the user sets a trigger by
+ writing the trigger registers themselves directly."""
+ def early_applicable(self):
+ return self.target.support_manual_hwbp and \
+ self.hart.instruction_hardware_breakpoint_count >= 1
+
+ def test(self):
+ if not self.hart.honors_tdata1_hmode:
+ # Run to main before setting the breakpoint, because startup code
+ # will otherwise clear the trigger that we set.
+ self.gdb.b("main")
+ self.gdb.c()
+
+ self.gdb.command("delete")
+ #self.gdb.hbreak("rot13")
+ tdata1 = MCONTROL_DMODE(self.hart.xlen)
+ tdata1 = set_field(tdata1, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE)
+ tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL)
+ tdata1 |= MCONTROL_M | MCONTROL_S | MCONTROL_U | MCONTROL_EXECUTE
+
+ tselect = 0
+ while True:
+ self.gdb.p("$tselect=%d" % tselect)
+ value = self.gdb.p("$tselect")
+ if value != tselect:
+ raise TestNotApplicable
+ self.gdb.p("$tdata1=0x%x" % tdata1)
+ value = self.gdb.p("$tselect")
+ if value == tdata1:
+ break
+ self.gdb.p("$tdata1=0")
+ tselect += 1
+
+ self.gdb.p("$tdata2=&rot13")
+ # The breakpoint should be hit exactly 2 times.
+ for _ in range(2):
+ output = self.gdb.c(ops=2)
+ self.gdb.p("$pc")
+ assertRegex(output, r"[bB]reakpoint")
+ assertIn("rot13 ", output)
+ self.gdb.p("$tdata2=&crc32a")
+ self.gdb.c()
+ before = self.gdb.p("$pc")
+ assertEqual(before, self.gdb.p("&crc32a"))
+ self.gdb.stepi()
+ after = self.gdb.p("$pc")
+ assertNotEqual(before, after)
+
+ self.gdb.b("_exit")
+ self.exit()
+
+
+class Hwbp2(DebugTest):
+ def early_applicable(self):
+ return self.hart.instruction_hardware_breakpoint_count >= 2
+
+ def test(self):
self.gdb.command("delete")
self.gdb.hbreak("main")
self.gdb.hbreak("rot13")
@@ -615,9 +732,14 @@
output = self.gdb.c(checkOutput=False)
assertIn("Cannot insert hardware breakpoint", output)
+ # There used to be a bug where this would fail if done twice in a row.
+ output = self.gdb.c(checkOutput=False)
+ assertIn("Cannot insert hardware breakpoint", output)
# Clean up, otherwise the hardware breakpoints stay set and future
# tests may fail.
- self.gdb.command("D")
+ self.gdb.command("delete")
+ self.gdb.b("_exit")
+ self.exit()
class Registers(DebugTest):
def test(self):
@@ -667,6 +789,163 @@
self.gdb.p("i=0")
self.exit()
+class MemorySampleTest(DebugTest):
+ def early_applicable(self):
+ return self.target.support_memory_sampling
+
+ def setup(self):
+ DebugTest.setup(self)
+ self.gdb.b("main:start")
+ self.gdb.c()
+ self.gdb.p("i=123")
+
+ @staticmethod
+ def check_incrementing_samples(raw_samples, check_addr,
+ tolerance=0x200000):
+ first_timestamp = None
+ end = None
+ total_samples = 0
+ previous_value = None
+ for line in raw_samples.splitlines():
+ m = re.match(r"^timestamp \w+: (\d+)", line)
+ if m:
+ timestamp = int(m.group(1))
+ if not first_timestamp:
+ first_timestamp = timestamp
+ else:
+ end = (timestamp, total_samples)
+ else:
+ address, value = line.split(': ')
+ address = int(address, 16)
+ if address == check_addr:
+ value = int(value, 16)
+ if not previous_value is None:
+ # TODO: what if the counter wraps?
+ assertGreater(value, previous_value)
+ assertLess(value, previous_value + tolerance)
+ previous_value = value
+ total_samples += 1
+ if end and total_samples > 0:
+ print("%d samples/second" % (1000 * end[1] / (end[0] -
+ first_timestamp)))
+ else:
+ raise Exception("No samples collected.")
+
+ @staticmethod
+ def check_samples_equal(raw_samples, check_addr, check_value):
+ total_samples = 0
+ for line in raw_samples.splitlines():
+ if not line.startswith("timestamp "):
+ address, value = line.split(': ')
+ address = int(address, 16)
+ if address == check_addr:
+ value = int(value, 16)
+ assertEqual(value, check_value)
+ total_samples += 1
+ assertGreater(total_samples, 0)
+
+ def collect_samples(self):
+ self.gdb.c(wait=False)
+ time.sleep(5)
+ output = self.gdb.interrupt()
+ assert "main" in output
+ return self.gdb.command("monitor riscv dump_sample_buf", ops=5)
+
+class MemorySampleSingle(MemorySampleTest):
+ def test(self):
+ addr = self.gdb.p("&j")
+ sizeof_j = self.gdb.p("sizeof(j)")
+ self.gdb.command("monitor riscv memory_sample 0 0x%x %d" % (
+ addr, sizeof_j))
+
+ raw_samples = self.collect_samples()
+ self.check_incrementing_samples(raw_samples, addr)
+
+ # Buffer should have been emptied by dumping.
+ raw_samples = self.gdb.command("monitor riscv dump_sample_buf", ops=5)
+ assertEqual(len(raw_samples), 0)
+
+class MemorySampleMixed(MemorySampleTest):
+ def test(self):
+ addr = {}
+ for i, name in enumerate(("j", "i32", "i64")):
+ addr[name] = self.gdb.p("&%s" % name)
+ sizeof = self.gdb.p("sizeof(%s)" % name)
+ self.gdb.command("monitor riscv memory_sample %d 0x%x %d" % (
+ i, addr[name], sizeof))
+
+ raw_samples = self.collect_samples()
+ self.check_incrementing_samples(raw_samples, addr["j"],
+ tolerance=0x400000)
+ self.check_samples_equal(raw_samples, addr["i32"], 0xdeadbeef)
+ self.check_samples_equal(raw_samples, addr["i64"], 0x1122334455667788)
+
+class RepeatReadTest(DebugTest):
+ def early_applicable(self):
+ return self.target.supports_clint_mtime
+
+ def test(self):
+ self.gdb.b("main:start")
+ self.gdb.c()
+ mtime_addr = 0x02000000 + 0xbff8
+ count = 1024
+ output = self.gdb.command("monitor riscv repeat_read %d 0x%x 4" %
+ (count, mtime_addr))
+ values = []
+ for line in output.splitlines():
+ # Ignore warnings
+ if line.startswith("Batch memory"):
+ continue
+ for v in line.split():
+ values.append(int(v, 16))
+
+ assertEqual(len(values), count)
+ # mtime should only ever increase, unless it wraps
+ slop = 0x100000
+ for i in range(1, len(values)):
+ if values[i] < values[i-1]:
+ # wrapped
+ assertLess(values[i], slop)
+ else:
+ assertGreater(values[i], values[i-1])
+ assertLess(values[i], values[i-1] + slop)
+
+ output = self.gdb.command("monitor riscv repeat_read 0 0x%x 4" %
+ mtime_addr)
+ assertEqual(output, "")
+
+class Semihosting(GdbSingleHartTest):
+ # Include malloc so that gdb can assign a string.
+ compile_args = ("programs/semihosting.c", "programs/tiny-malloc.c",
+ "-DDEFINE_MALLOC", "-DDEFINE_FREE")
+
+ def early_applicable(self):
+ return self.target.test_semihosting
+
+ def setup(self):
+ self.gdb.load()
+ self.parkOtherHarts()
+ self.gdb.b("_exit")
+
+ def exit(self, expected_result=0):
+ output = self.gdb.c()
+ assertIn("Breakpoint", output)
+ assertIn("_exit", output)
+ assertEqual(self.gdb.p("status"), expected_result)
+
+ def test(self):
+ """Sending gdb ^C while the program is running should cause it to
+ halt."""
+ temp = tempfile.NamedTemporaryFile(suffix=".data")
+
+ self.gdb.b("main:begin")
+ self.gdb.c()
+ self.gdb.p('filename="%s"' % temp.name, ops=3)
+ self.exit()
+
+ contents = open(temp.name, "r").readlines()
+ assertIn("Hello, world!\n", contents)
+
class InterruptTest(GdbSingleHartTest):
compile_args = ("programs/interrupt.c",)
@@ -738,18 +1017,18 @@
self.gdb.c()
assertIn("main_end", self.gdb.where())
- hart_ids = []
+ hart_ids = set()
for hart in self.target.harts:
self.gdb.select_hart(hart)
# Check register values.
x1 = self.gdb.p("$x1")
hart_id = self.gdb.p("$mhartid")
assertEqual(x1, hart_id << 8)
- assertNotIn(hart_id, hart_ids)
- hart_ids.append(hart_id)
+ assertNotIn((hart.system, hart_id), hart_ids)
+ hart_ids.add((hart.system, hart_id))
for n in range(2, 32):
value = self.gdb.p("$x%d" % n)
- assertEqual(value, (hart_ids[-1] << 8) + n - 1)
+ assertEqual(value, (hart_id << 8) + n - 1)
# Confirmed that we read different register values for different harts.
# Write a new value to x1, and run through the add sequence again.
@@ -1053,7 +1332,8 @@
class TriggerDmode(TriggerTest):
def early_applicable(self):
- return self.hart.honors_tdata1_hmode
+ return self.hart.honors_tdata1_hmode and \
+ self.hart.instruction_hardware_breakpoint_count > 0
def check_triggers(self, tdata1_lsbs, tdata2):
dmode = 1 << (self.hart.xlen-5)
@@ -1156,6 +1436,8 @@
assertEqual(123, self.gdb.p("$csr832"))
class DownloadTest(GdbTest):
+ compile_args = ("programs/infinite_loop.S", )
+
def setup(self):
# pylint: disable=attribute-defined-outside-init
length = min(2**18, max(2**10, self.hart.ram_size - 2048))
@@ -1188,15 +1470,23 @@
if self.crc < 0:
self.crc += 2**32
- self.binary = self.target.compile(self.hart, self.download_c.name,
- "programs/checksum.c")
- self.gdb.global_command("file %s" % self.binary)
+ compiled = {}
+ for hart in self.target.harts:
+ key = hart.system
+ if key not in compiled:
+ compiled[key] = self.target.compile(hart, self.download_c.name,
+ "programs/checksum.c")
+ self.gdb.select_hart(hart)
+ self.gdb.command("file %s" % compiled.get(key))
+
+ self.gdb.select_hart(self.hart)
def test(self):
self.gdb.load()
self.parkOtherHarts()
self.gdb.command("b _exit")
- self.gdb.c(ops=100)
+ #self.gdb.c(ops=100)
+ self.gdb.c()
assertEqual(self.gdb.p("status"), self.crc)
os.unlink(self.download_c.name)
@@ -1289,6 +1579,7 @@
self.disable_pmp()
self.gdb.load()
+ self.parkOtherHarts()
self.gdb.b("main")
output = self.gdb.c()
assertRegex(output, r"\bmain\b")
@@ -1352,6 +1643,132 @@
self.gdb.p("vms=&sv48")
self.test_translation()
+class VectorTest(GdbSingleHartTest):
+ compile_args = ("programs/vectors.S", )
+
+ def early_applicable(self):
+ if not self.hart.extensionSupported('V'):
+ return False
+ # If the compiler can't build this test, say it's not applicable. At
+ # some time all compilers will support the V extension, but we're not
+ # there yet.
+ try:
+ self.compile()
+ except CompileError as e:
+ if b"Error: unknown CSR `vlenb'" in e.stderr:
+ return False
+ return True
+
+ def setup(self):
+ self.gdb.load()
+ self.gdb.b("main")
+ self.gdb.c()
+
+ def test(self):
+ vlenb = self.gdb.p("$vlenb")
+ self.gdb.command("delete")
+ self.gdb.b("_exit")
+ self.gdb.b("trap_entry")
+
+ self.gdb.b("test0")
+
+ output = self.gdb.c()
+ assertIn("Breakpoint", output)
+ assertIn("test0", output)
+
+ # I'm not convinced that writing 0 is supported on every vector
+ # implementation. If this test fails, that might be why.
+ for regname in ('$vl', '$vtype'):
+ value = self.gdb.p(regname)
+ assertNotEqual(value, 0)
+ self.gdb.p("%s=0" % regname)
+ self.gdb.command("flushregs")
+ assertEqual(self.gdb.p(regname), 0)
+ self.gdb.p("%s=0x%x" % (regname, value))
+ self.gdb.command("flushregs")
+ assertEqual(self.gdb.p(regname), value)
+
+ assertEqual(self.gdb.p("$a0"), 0)
+ a = self.gdb.x("&a", 'b', vlenb)
+ b = self.gdb.x("&b", 'b', vlenb)
+ v4 = self.gdb.p("$v4")
+ assertEqual(a, b)
+ assertEqual(b, v4["b"])
+ assertEqual(0, self.gdb.p("$a0"))
+
+ self.gdb.b("test1")
+
+ output = self.gdb.c()
+ assertIn("Breakpoint", output)
+ assertIn("test1", output)
+
+ assertEqual(self.gdb.p("$a0"), 0)
+ b = self.gdb.x("&b", 'b', vlenb)
+ c = self.gdb.x("&c", 'b', vlenb)
+ v4 = self.gdb.p("$v4")
+ assertEqual(b, c)
+ assertEqual(c, v4["b"])
+ assertEqual(0, self.gdb.p("$a0"))
+
+ output = self.gdb.c()
+ assertIn("Breakpoint", output)
+ assertIn("_exit", output)
+ assertEqual(self.gdb.p("status"), 0)
+
+class FreeRtosTest(GdbTest):
+ def early_applicable(self):
+ return self.target.freertos_binary
+
+ def freertos(self):
+ return True
+
+ def test(self):
+ self.gdb.command("file %s" % self.target.freertos_binary)
+ self.gdb.load()
+
+ output = self.gdb.command("monitor riscv_freertos_stacking mainline")
+
+ # Turn off htif, which doesn't work when the file is loaded into spike
+ # through gdb. It only works when spike loads the ELF file itself.
+ bp = self.gdb.b("main")
+ self.gdb.c()
+ self.gdb.command("delete %d" % bp)
+ self.gdb.p("*((int*) &use_htif) = 0")
+ # Need this, otherwise gdb complains that there is no current active
+ # thread.
+ self.gdb.threads()
+
+ bp = self.gdb.b("prvQueueReceiveTask")
+
+ self.gdb.c()
+ self.gdb.command("delete %d" % bp)
+
+ bp = self.gdb.b("prvQueueSendTask")
+ self.gdb.c()
+ self.gdb.command("delete %d" % bp)
+
+ # Now we know for sure at least 2 threads have executed.
+
+ threads = self.gdb.threads()
+ assertGreater(len(threads), 1)
+
+ values = {}
+ for thread in threads:
+ assertNotIn("No Name", thread[1])
+ self.gdb.thread(thread)
+ assertEqual(self.gdb.p("$zero"), 0)
+ output = self.gdb.command("info reg sp")
+ assertIn("ucHeap", output)
+ self.gdb.command("info reg mstatus")
+ values[thread.id] = self.gdb.p("$s11")
+ self.gdb.p("$s11=0x%x" % (values[thread.id] ^ int(thread.id)))
+
+ # Test that writing worked
+ self.gdb.stepi()
+ for thread in self.gdb.threads():
+ self.gdb.thread(thread)
+ assertEqual(self.gdb.p("$s11"), values[thread.id] ^ int(thread.id))
+
parsed = None
def main():
parser = argparse.ArgumentParser(
diff --git a/src/riscv-tests/debug/programs/debug.c b/src/riscv-tests/debug/programs/debug.c
index 8a4aa73..641aa4e 100644
--- a/src/riscv-tests/debug/programs/debug.c
+++ b/src/riscv-tests/debug/programs/debug.c
@@ -55,6 +55,8 @@
int j = 0;
char fox[] = "The quick brown fox jumps of the lazy dog.";
unsigned int checksum = 0;
+ volatile uint32_t i32 = 0xdeadbeef;
+ volatile uint64_t i64 = 0x1122334455667788;
start:
while (i)
diff --git a/src/riscv-tests/debug/programs/entry.S b/src/riscv-tests/debug/programs/entry.S
index 3796b3b..091efa4 100755
--- a/src/riscv-tests/debug/programs/entry.S
+++ b/src/riscv-tests/debug/programs/entry.S
@@ -71,6 +71,9 @@
addi t0, t0, -1
bnez t0, 1b
+ # Catch trap in case trigger module is not implemented
+ la t2, 2f
+ csrrw t2, mtvec, t2
# Clear all hardware triggers
li t0, ~0
1:
@@ -79,6 +82,10 @@
csrw CSR_TDATA1, zero
csrr t1, CSR_TSELECT
beq t0, t1, 1b
+.p2align 2
+2:
+ # Restore mtvec
+ csrw mtvec, t2
#ifdef MULTICORE
csrr t0, CSR_MHARTID
diff --git a/src/riscv-tests/debug/programs/semihosting.c b/src/riscv-tests/debug/programs/semihosting.c
new file mode 100644
index 0000000..2ceea8c
--- /dev/null
+++ b/src/riscv-tests/debug/programs/semihosting.c
@@ -0,0 +1,73 @@
+#include <stdint.h>
+
+#include "semihosting.h"
+
+size_t strlen(const char *buf)
+{
+ int len = 0;
+ while (buf[len])
+ len++;
+ return len;
+}
+
+#define O_RDONLY 0
+#define O_WRONLY 1
+#define O_RDWR 2
+#define O_RDWR 2
+#define O_TRUNC 0x0800
+
+int errno;
+
+/* These semihosting functions came from the Freedom Metal source. */
+static int open(const char *name, int flags, int mode) {
+ int semiflags = 0;
+
+ switch (flags & (O_RDONLY | O_WRONLY | O_RDWR)) {
+ case O_RDONLY:
+ semiflags = 0; /* 'r' */
+ break;
+ case O_WRONLY:
+ if (flags & O_TRUNC)
+ semiflags = 4; /* 'w' */
+ else
+ semiflags = 8; /* 'a' */
+ break;
+ default:
+ if (flags & O_TRUNC)
+ semiflags = 6; /* 'w+' */
+ else
+ semiflags = 10; /* 'a+' */
+ break;
+ }
+
+ volatile semihostparam_t arg = {.param1 = (uintptr_t)name,
+ .param2 = (uintptr_t)semiflags,
+ .param3 = (uintptr_t)strlen(name)};
+
+ int ret = (int)semihost_call_host(SEMIHOST_SYS_OPEN, (uintptr_t)&arg);
+ if (ret == -1)
+ errno = semihost_call_host(SEMIHOST_SYS_ERRNO, 0);
+ return ret;
+}
+
+static ssize_t write(int file, const void *ptr, size_t len)
+{
+ volatile semihostparam_t arg = {.param1 = (uintptr_t)file,
+ .param2 = (uintptr_t)ptr,
+ .param3 = (uintptr_t)len};
+ ssize_t ret =
+ (ssize_t)semihost_call_host(SEMIHOST_SYS_WRITE, (uintptr_t)&arg);
+
+ return (len - ret);
+}
+
+int main()
+{
+ char *filename = NULL;
+ const char *message = "Hello, world!\n";
+ int fd;
+
+begin:
+ fd = open(filename, O_WRONLY, 0644);
+ write(fd, message, strlen(message));
+}
\ No newline at end of file
diff --git a/src/riscv-tests/debug/programs/semihosting.h b/src/riscv-tests/debug/programs/semihosting.h
new file mode 100644
index 0000000..201e414
--- /dev/null
+++ b/src/riscv-tests/debug/programs/semihosting.h
@@ -0,0 +1,82 @@
+#include <sys/types.h>
+
+#ifndef _SEMIHOSTING_H_
+#define _SEMIHOSTING_H_
+
+// ----------------------------------------------------------------------------
+
+// Semihosting operations.
+enum Semihost_Sys_Op {
+ // Regular operations
+ SEMIHOST_SYS_CLOCK = 0x10,
+ SEMIHOST_SYS_CLOSE = 0x02,
+ SEMIHOST_SYS_ELAPSED = 0x30,
+ SEMIHOST_SYS_ERRNO = 0x13,
+ SEMIHOST_SYS_EXIT = 0x18,
+ SEMIHOST_SYS_EXIT_EXTENDED = 0x20,
+ SEMIHOST_SYS_FLEN = 0x0C,
+ SEMIHOST_SYS_GET_CMDLINE = 0x15,
+ SEMIHOST_SYS_HEAPINFO = 0x16,
+ SEMIHOST_SYS_ISERROR = 0x08,
+ SEMIHOST_SYS_ISTTY = 0x09,
+ SEMIHOST_SYS_OPEN = 0x01,
+ SEMIHOST_SYS_READ = 0x06,
+ SEMIHOST_SYS_READC = 0x07,
+ SEMIHOST_SYS_REMOVE = 0x0E,
+ SEMIHOST_SYS_RENAME = 0x0F,
+ SEMIHOST_SYS_SEEK = 0x0A,
+ SEMIHOST_SYS_SYSTEM = 0x12,
+ SEMIHOST_SYS_TICKFREQ = 0x31,
+ SEMIHOST_SYS_TIME = 0x11,
+ SEMIHOST_SYS_TMPNAM = 0x0D,
+ SEMIHOST_SYS_WRITE = 0x05,
+ SEMIHOST_SYS_WRITEC = 0x03,
+ SEMIHOST_SYS_WRITE0 = 0x04,
+};
+
+enum ADP_Code {
+ ADP_Stopped_BranchThroughZero = 0x20000,
+ ADP_Stopped_UndefinedInstr = 0x20001,
+ ADP_Stopped_SoftwareInterrupt = 0x20002,
+ ADP_Stopped_PrefetchAbort = 0x20003,
+ ADP_Stopped_DataAbort = 0x20004,
+ ADP_Stopped_AddressException = 0x20005,
+ ADP_Stopped_IRQ = 0x20006,
+ ADP_Stopped_FIQ = 0x20007,
+ ADP_Stopped_BreakPoint = 0x20020,
+ ADP_Stopped_WatchPoint = 0x20021,
+ ADP_Stopped_StepComplete = 0x20022,
+ ADP_Stopped_RunTimeErrorUnknown = 0x20023,
+ ADP_Stopped_InternalError = 0x20024,
+ ADP_Stopped_UserInterruption = 0x20025,
+ ADP_Stopped_ApplicationExit = 0x20026,
+ ADP_Stopped_StackOverflow = 0x20027,
+ ADP_Stopped_DivisionByZero = 0x20028,
+ ADP_Stopped_OSSpecific = 0x20029,
+};
+
+typedef struct {
+ uintptr_t param1;
+ uintptr_t param2;
+ uintptr_t param3;
+} semihostparam_t;
+
+static inline uintptr_t __attribute__((always_inline))
+semihost_call_host(uintptr_t op, uintptr_t arg) {
+ register uintptr_t r0 asm("a0") = op;
+ register uintptr_t r1 asm("a1") = arg;
+
+ asm volatile(".option push \n"
+ ".option norvc \n"
+ " slli zero,zero,0x1f \n"
+ " ebreak \n"
+ " srai zero,zero,0x7 \n"
+ ".option pop \n"
+
+ : "=r"(r0) /* Outputs */
+ : "r"(r0), "r"(r1) /* Inputs */
+ : "memory");
+ return r0;
+}
+
+#endif
\ No newline at end of file
diff --git a/src/riscv-tests/debug/programs/vectors.S b/src/riscv-tests/debug/programs/vectors.S
new file mode 100644
index 0000000..53e53be
--- /dev/null
+++ b/src/riscv-tests/debug/programs/vectors.S
@@ -0,0 +1,159 @@
+#include "encoding.h"
+
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+
+ .global main
+ .global main_end
+ .global main_post_csrr
+
+ // Load constants into all registers so we can test no register are
+ // clobbered after attaching.
+main:
+ SREG ra, 0(sp)
+ addi sp, sp, REGBYTES
+
+ // Set VS=1
+ csrr t0, CSR_MSTATUS
+ li t1, set_field(0, MSTATUS_VS, 1)
+ or t0, t0, t1
+ csrw CSR_MSTATUS, t0
+
+ // copy a to b
+ la a0, a
+ jal vector_load_v4
+ la a0, b
+ jal shift_store_v4
+
+ // assert a == b
+ la a0, a
+ la a1, b
+ jal check_equal
+test0:
+ bne a0, zero, return_from_main
+
+ // copy b to c
+ la a0, b
+ jal shift_load_v4
+ la a0, c
+ jal vector_store_v4
+
+ // assert b == c
+ la a0, b
+ la a1, c
+ jal check_equal
+test1:
+ bne a0, zero, return_from_main
+
+return_from_main:
+ addi sp, sp, -REGBYTES
+ LREG ra, 0(sp)
+ ret
+
+vector_load_v4:
+ // a0: point to memory to load from
+ csrr s0, vlenb
+ vsetvli zero, s0, e8, m1 # Vectors of 8b
+ vle8.v v4, 0(a0) # Load bytes
+ ret
+
+vector_store_v4:
+ // a0: point to memory to store to
+ csrr s0, vlenb
+ vsetvli zero, s0, e8, m1 # Vectors of 8b
+ vse8.v v4, 0(a0) # Load bytes
+ ret
+
+shift_load_v4:
+ // a0: pointer to memory to load from
+
+ // Configure all elements in the chain
+ csrr s0, vlenb
+#if XLEN == 32
+ vsetvli zero, s0, e32
+#else
+ vsetvli zero, s0, e64
+#endif
+
+ // Figure out how long the chain is.
+ csrr s0, vlenb
+ li s1, XLEN/8
+ divu s0, s0, s1
+
+1:
+ LREG s2, 0(a0)
+ vslide1down.vx v4, v4, s2
+ addi a0, a0, REGBYTES
+ addi s0, s0, -1
+ bne s0, zero, 1b
+
+ ret
+
+shift_store_v4:
+ // a0: pointer to memory to store to
+
+ // Configure all elements in the chain
+ csrr s0, vlenb
+#if XLEN == 32
+ vsetvli zero, s0, e32
+#else
+ vsetvli zero, s0, e64
+#endif
+
+ // Figure out how long the chain is.
+ csrr s0, vlenb
+ li s1, XLEN/8
+ divu s0, s0, s1
+
+1:
+ vmv.x.s s2, v4
+ SREG s2, 0(a0)
+ vslide1down.vx v4, v4, s2
+ addi a0, a0, REGBYTES
+ addi s0, s0, -1
+ bne s0, zero, 1b
+
+ ret
+
+check_equal:
+ csrr s0, vlenb
+1:
+ lb s1, 0(a0)
+ lb s2, 0(a1)
+ bne s1, s2, 2f
+ addi a0, a0, 1
+ addi a1, a1, 1
+ addi s0, s0, -1
+ bne s0, zero, 1b
+ li a0, 0 // equal
+ ret
+2: // unequal
+ li a0, 1
+ ret
+
+ .data
+ .align 6
+a: .word 0xaa00, 0xaa01, 0xaa02, 0xaa03, 0xaa04, 0xaa05, 0xaa06, 0xaa07
+ .word 0xaa08, 0xaa09, 0xaa0a, 0xaa0b, 0xaa0c, 0xaa0d, 0xaa0e, 0xaa0f
+ .word 0xaa10, 0xaa11, 0xaa12, 0xaa13, 0xaa14, 0xaa15, 0xaa16, 0xaa17
+ .word 0xaa18, 0xaa19, 0xaa1a, 0xaa1b, 0xaa1c, 0xaa1d, 0xaa1e, 0xaa1f
+
+b: .word 0xbb00, 0xbb01, 0xbb02, 0xbb03, 0xbb04, 0xbb05, 0xbb06, 0xbb07
+ .word 0xbb08, 0xbb09, 0xbb0b, 0xbb0b, 0xbb0c, 0xbb0d, 0xbb0e, 0xbb0f
+ .word 0xbb10, 0xbb11, 0xbb13, 0xbb13, 0xbb14, 0xbb15, 0xbb16, 0xbb17
+ .word 0xbb18, 0xbb19, 0xbb1b, 0xbb1b, 0xbb1c, 0xbb1d, 0xbb1e, 0xbb1f
+
+c: .word 0xcc00, 0xcc01, 0xcc02, 0xcc03, 0xcc04, 0xcc05, 0xcc06, 0xcc07
+ .word 0xcc08, 0xcc09, 0xcc0c, 0xcc0c, 0xcc0c, 0xcc0d, 0xcc0e, 0xcc0f
+ .word 0xcc10, 0xcc11, 0xcc13, 0xcc13, 0xcc14, 0xcc15, 0xcc16, 0xcc17
+ .word 0xcc18, 0xcc19, 0xcc1c, 0xcc1c, 0xcc1c, 0xcc1d, 0xcc1e, 0xcc1f
\ No newline at end of file
diff --git a/src/riscv-tests/debug/rbb_daisychain.py b/src/riscv-tests/debug/rbb_daisychain.py
new file mode 100755
index 0000000..b7c21e6
--- /dev/null
+++ b/src/riscv-tests/debug/rbb_daisychain.py
@@ -0,0 +1,111 @@
+#!/usr/bin/python3
+
+import argparse
+import sys
+import socket
+
+# https://github.com/ntfreak/openocd/blob/master/doc/manual/jtag/drivers/remote_bitbang.txt
+
+class Tap:
+ def __init__(self, port):
+ self.port = port
+ self.socket = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.socket.connect(("localhost", port))
+
+ def execute(self, commands):
+ sent = self.socket.send(commands)
+ assert len(commands) == sent
+ read_count = 0
+ for command in commands:
+ if command == ord('R'):
+ read_count += 1
+ result = b""
+ while len(result) < read_count:
+ result += self.socket.recv(read_count - len(result))
+ assert len(result) == read_count
+ return result
+
+class Chain:
+ def __init__(self, debug=False):
+ self.debug = debug
+ self.taps = []
+
+ def append(self, tap):
+ self.taps.append(tap)
+
+ def execute(self, commands):
+ values = []
+ for i, tap in enumerate(self.taps):
+ tmp_commands = []
+ for command in commands:
+ if i > 0 and ord('0') <= command <= ord('7'):
+ # Replace TDI with the value from the previous TAP.
+ v = values.pop(0)
+ command &= 0xfe
+ if v == ord('1'):
+ command |= 1
+
+ if i < len(self.taps) - 1:
+ if command != ord('R'):
+ tmp_commands.append(command)
+ if ord('0') <= command <= ord('7'):
+ # Read TDO before every scan.
+ tmp_commands.append(ord('R'))
+ else:
+ tmp_commands.append(command)
+ assert len(values) == 0
+ values = list(tap.execute(bytes(tmp_commands)))
+ if self.debug:
+ sys.stdout.write(" %d %r -> %r\n" % (i, bytes(tmp_commands),
+ bytes(values)))
+ return bytes(values)
+
+def main():
+ parser = argparse.ArgumentParser(
+ description='Combine multiple remote_bitbang processes into a '
+ 'single scan-chain.')
+ parser.add_argument("listen_port", type=int,
+ help="port to listen on")
+ parser.add_argument("tap_port", nargs="+", type=int,
+ help="port of a remote_bitbang TAP to connect to")
+ parser.add_argument("--debug", action='store_true',
+ help="Print out debug messages.")
+ args = parser.parse_args()
+
+ server = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ server.bind(("localhost", args.listen_port))
+ server.listen(1)
+
+ chain = Chain(args.debug)
+ for port in args.tap_port:
+ chain.append(Tap(port))
+
+ sys.stdout.write("Listening on port %d.\n" % server.getsockname()[1])
+ sys.stdout.flush()
+
+ while True:
+ (client, _) = server.accept()
+
+ while True:
+ try:
+ commands = client.recv(4096)
+ except (ConnectionResetError, OSError):
+ sys.stdout.write("Client disconnected due to exception.\n")
+ break
+
+ if len(commands) == 0:
+ sys.stdout.write("Client disconnected.\n")
+ break
+
+ if args.debug:
+ sys.stdout.write("%r\n" % commands)
+ result = chain.execute(commands)
+ if args.debug:
+ sys.stdout.write(" -> %r\n" % result)
+ client.send(result)
+
+ client.close()
+ sys.stdout.flush()
+
+if __name__ == '__main__':
+ sys.exit(main())
diff --git a/src/riscv-tests/debug/targets.py b/src/riscv-tests/debug/targets.py
index f4192b6..dd0175e 100644
--- a/src/riscv-tests/debug/targets.py
+++ b/src/riscv-tests/debug/targets.py
@@ -1,5 +1,6 @@
import importlib
import os.path
+import re
import sys
import tempfile
@@ -28,6 +29,10 @@
ram = None
ram_size = None
+ # Address where we expect memory accesses to fail, usually because there is
+ # no device mapped to that location.
+ bad_address = None
+
# Number of instruction triggers the hart supports.
instruction_hardware_breakpoint_count = 0
@@ -39,6 +44,20 @@
# jumpers.
reset_vectors = []
+ # system is set to an identifier of the system this hart belongs to. Harts
+ # within the same system are assumed to share memory, and to have unique
+ # hartids within that system. So for most cases the default value of None
+ # is fine.
+ system = None
+
+ def __init__(self, misa=None, system=None, link_script_path=None):
+ if misa:
+ self.misa = misa
+ if system:
+ self.system = system
+ if link_script_path:
+ self.link_script_path = link_script_path
+
def extensionSupported(self, letter):
# target.misa is set by testlib.ExamineTarget
if self.misa:
@@ -91,6 +110,22 @@
# whether they are applicable or not.
skip_tests = []
+ # Set False if semihosting should not be tested in this configuration,
+ # because it doesn't work and isn't expected to work.
+ test_semihosting = True
+
+ # Set False if manual hwbps (breakpoints set by directly writing tdata*)
+ # isn't supposed to work.
+ support_manual_hwbp = True
+
+ # Set False if memory sampling is not supported due to OpenOCD
+ # limitation/hardware support.
+ support_memory_sampling = True
+
+ # Relative path to a FreeRTOS binary compiled from the spike demo project
+ # in https://github.com/FreeRTOS/FreeRTOS.
+ freertos_binary = None
+
# Internal variables:
directory = None
temporary_files = []
@@ -102,6 +137,7 @@
self.server_cmd = parsed.server_cmd
self.sim_cmd = parsed.sim_cmd
self.temporary_binary = None
+ self.compiler_supports_v = True
Target.isolate = parsed.isolate
if not self.name:
self.name = type(self).__name__
@@ -125,17 +161,18 @@
def create(self):
"""Create the target out of thin air, eg. start a simulator."""
- def server(self):
+ def server(self, test):
"""Start the debug server that gdb connects to, eg. OpenOCD."""
return testlib.Openocd(server_cmd=self.server_cmd,
config=self.openocd_config_path,
- timeout=self.server_timeout_sec)
+ timeout=self.server_timeout_sec,
+ freertos=test.freertos())
- def compile(self, hart, *sources):
- binary_name = "%s_%s-%d" % (
+ def do_compile(self, hart, *sources):
+ binary_name = "%s_%s-%x" % (
self.name,
os.path.basename(os.path.splitext(sources[0])[0]),
- hart.xlen)
+ hart.misa)
if Target.isolate:
self.temporary_binary = tempfile.NamedTemporaryFile(
prefix=binary_name + "_")
@@ -161,6 +198,8 @@
for letter in "fdc":
if hart.extensionSupported(letter):
march += letter
+ if hart.extensionSupported("v") and self.compiler_supports_v:
+ march += "v"
args.append("-march=%s" % march)
if hart.xlen == 32:
args.append("-mabi=ilp32")
@@ -170,6 +209,24 @@
testlib.compile(args)
return binary_name
+ def compile(self, hart, *sources):
+ for _ in range(2):
+ try:
+ return self.do_compile(hart, *sources)
+ except testlib.CompileError as e:
+ # If the compiler doesn't support V, disable it from the
+ # current configuration. Eventually all gcc branches will
+ # support V, but we're not there yet.
+ m = re.search(r"Error: cannot find default versions of the "
+ r"ISA extension `(\w)'", e.stderr.decode())
+ if m and m.group(1) in "v":
+ extension = m.group(1)
+ print("Disabling extension %r because the "
+ "compiler doesn't support it." % extension)
+ self.compiler_supports_v = False
+ else:
+ raise
+
def add_target_options(parser):
parser.add_argument("target", help=".py file that contains definition for "
"the target to test with.")
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-1.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-1.cfg
index d1ed60e..5f11b08 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike-1.cfg
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-1.cfg
@@ -8,10 +8,13 @@
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+if {$::env(USE_FREERTOS)} {
+ target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos FreeRTOS
+} else {
+ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+}
$_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
-
gdb_report_data_abort enable
gdb_report_register_access_error enable
@@ -26,3 +29,5 @@
riscv authdata_write [expr $challenge + 1]
halt
+
+arm semihosting enable
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg
index 31a5f68..c378a45 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg
@@ -11,7 +11,6 @@
set _TARGETNAME_0 $_CHIPNAME.cpu0
set _TARGETNAME_1 $_CHIPNAME.cpu1
target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread
-#target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
target smp $_TARGETNAME_0 $_TARGETNAME_1
@@ -20,8 +19,11 @@
# Expose an unimplemented CSR so we can test non-existent register access
# behavior.
-riscv expose_csrs 2288
-riscv expose_custom 1,12345-12348
+foreach t [target names] {
+ targets $t
+ riscv expose_csrs 2288
+ riscv expose_custom 1,12345-12348
+}
init
@@ -29,3 +31,8 @@
riscv authdata_write [expr $challenge + 1]
halt
+
+foreach t [target names] {
+ targets $t
+ arm semihosting enable
+}
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-2.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-2.cfg
index c9de7d2..640fba9 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike-2.cfg
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-2.cfg
@@ -18,15 +18,19 @@
# Expose an unimplemented CSR so we can test non-existent register access
# behavior.
-riscv expose_csrs 2288
-riscv expose_custom 1,12345-12348
+foreach t [target names] {
+ targets $t
+ riscv expose_csrs 2288
+ riscv expose_custom 1,12345-12348
+}
init
set challenge [riscv authdata_read]
riscv authdata_write [expr $challenge + 1]
-targets $_TARGETNAME_0
-halt
-targets $_TARGETNAME_1
-halt
+foreach t [target names] {
+ targets $t
+ halt
+ arm semihosting enable
+}
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-multi.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-multi.cfg
new file mode 100644
index 0000000..ef6dfc6
--- /dev/null
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-multi.cfg
@@ -0,0 +1,46 @@
+# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
+adapter_khz 10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+jtag newtap riscv.0 cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap riscv.1 cpu -irlen 5 -expected-id 0x10e31913
+
+target create riscv.0.cpu0 riscv -chain-position riscv.0.cpu -coreid 0
+target create riscv.0.cpu1 riscv -chain-position riscv.0.cpu -coreid 1
+target create riscv.1.cpu0 riscv -chain-position riscv.1.cpu -coreid 0
+target create riscv.1.cpu1 riscv -chain-position riscv.1.cpu -coreid 1
+
+riscv.0.cpu0 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+riscv.0.cpu1 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+riscv.1.cpu0 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+riscv.1.cpu1 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+foreach t [target names] {
+ targets $t
+ riscv expose_csrs 2288
+ riscv expose_custom 1,12345-12348
+}
+
+init
+
+targets riscv.0.cpu0
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+targets riscv.1.cpu0
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+foreach t [target names] {
+ targets $t
+ halt
+ arm semihosting enable
+}
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-multi.py b/src/riscv-tests/debug/targets/RISC-V/spike-multi.py
new file mode 100644
index 0000000..82de76f
--- /dev/null
+++ b/src/riscv-tests/debug/targets/RISC-V/spike-multi.py
@@ -0,0 +1,31 @@
+import targets
+import testlib
+
+import spike32 # pylint: disable=import-error
+import spike64 # pylint: disable=import-error
+
+class multispike(targets.Target):
+ harts = [
+ spike32.spike32_hart(misa=0x4034112d, system=0),
+ spike32.spike32_hart(misa=0x4034112d, system=0),
+ spike64.spike64_hart(misa=0x8000000000341129, system=1),
+ spike64.spike64_hart(misa=0x8000000000341129, system=1)]
+ openocd_config_path = "spike-multi.cfg"
+ # Increased timeout because we use abstract_rti to artificially slow things
+ # down.
+ timeout_sec = 30
+ implements_custom_test = True
+ support_hasel = False
+ support_memory_sampling = False # Needs SBA
+
+ def create(self):
+ return testlib.MultiSpike(
+ [
+ testlib.Spike(self, isa="RV64IMAFDV",
+ support_hasel=False, support_abstract_csr=False,
+ vlen=512, elen=64, harts=self.harts[2:]),
+ testlib.Spike(self, isa="RV32IMAFDCV",
+ support_abstract_csr=True, support_haltgroups=False,
+ # elen must be at least 64 because D is supported.
+ elen=64, harts=self.harts[:2]),
+ ])
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg b/src/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg
deleted file mode 100644
index 7cd1c3f..0000000
--- a/src/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
-adapter_khz 10000
-
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-# Expose an unimplemented CSR so we can test non-existent register access
-# behavior.
-riscv expose_csrs 2288
-riscv expose_custom 1,12345-12348
-
-init
-
-set challenge [riscv authdata_read]
-riscv authdata_write [expr $challenge + 1]
-
-halt
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py b/src/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py
index 2ad2998..e84391a 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py
@@ -9,6 +9,7 @@
openocd_config_path = "spike-2-hwthread.cfg"
timeout_sec = 5
implements_custom_test = True
+ support_memory_sampling = False # not supported without sba
def create(self):
return testlib.Spike(self, isa="RV32IMAV", support_hasel=True,
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py b/src/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py
deleted file mode 100644
index 8872739..0000000
--- a/src/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py
+++ /dev/null
@@ -1,17 +0,0 @@
-import targets
-import testlib
-
-import spike32 # pylint: disable=import-error
-
-class spike32_2(targets.Target):
- harts = [spike32.spike32_hart(misa=0x40141129),
- spike32.spike32_hart(misa=0x40141129)]
- openocd_config_path = "spike-rtos.cfg"
- timeout_sec = 30
- implements_custom_test = True
- support_hasel = False
-
- def create(self):
- return testlib.Spike(self, progbufsize=0, dmi_rti=4,
- support_hasel=False, support_abstract_csr=True,
- support_haltgroups=False)
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike32.py b/src/riscv-tests/debug/targets/RISC-V/spike32.py
index b261f6c..17d28fb 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike32.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike32.py
@@ -5,18 +5,18 @@
xlen = 32
ram = 0x10000000
ram_size = 0x10000000
+ bad_address = ram - 8
instruction_hardware_breakpoint_count = 4
reset_vectors = [0x1000]
link_script_path = "spike32.lds"
- def __init__(self, misa):
- self.misa = misa
-
class spike32(targets.Target):
harts = [spike32_hart(misa=0x4034112d)]
openocd_config_path = "spike-1.cfg"
timeout_sec = 30
implements_custom_test = True
+ support_memory_sampling = False # Needs SBA
+ freertos_binary = "bin/RTOSDemo32.axf"
def create(self):
# 64-bit FPRs on 32-bit target
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py b/src/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py
index 5d8d6e6..db381d4 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py
@@ -4,11 +4,17 @@
import spike64 # pylint: disable=import-error
class spike64_2(targets.Target):
- harts = [spike64.spike64_hart(misa=0x8000000000141129),
- spike64.spike64_hart(misa=0x8000000000141129)]
+ harts = [spike64.spike64_hart(misa=0x8000000000341129),
+ spike64.spike64_hart(misa=0x8000000000341129)]
openocd_config_path = "spike-2-hwthread.cfg"
- timeout_sec = 5
+ # Increased timeout because we use abstract_rti to artificially slow things
+ # down.
+ timeout_sec = 20
implements_custom_test = True
+ support_hasel = False
+ support_memory_sampling = False # Needs SBA
def create(self):
- return testlib.Spike(self)
+ return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30,
+ support_hasel=False, support_abstract_csr=False,
+ vlen=512, elen=64)
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py b/src/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py
index db6263a..acb217f 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py
@@ -10,6 +10,9 @@
timeout_sec = 60
implements_custom_test = True
support_hasel = False
+ test_semihosting = False
+ support_manual_hwbp = False # not supported with `-rtos riscv`
+ support_memory_sampling = False # not supported with `-rtos riscv`
def create(self):
return testlib.Spike(self, abstract_rti=30, support_hasel=False,
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike64-2.py b/src/riscv-tests/debug/targets/RISC-V/spike64-2.py
index 5ace23b..e710fe1 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike64-2.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike64-2.py
@@ -4,16 +4,12 @@
import spike64 # pylint: disable=import-error
class spike64_2(targets.Target):
- harts = [spike64.spike64_hart(misa=0x8000000000341129),
- spike64.spike64_hart(misa=0x8000000000341129)]
+ harts = [spike64.spike64_hart(misa=0x8000000000141129),
+ spike64.spike64_hart(misa=0x8000000000141129)]
openocd_config_path = "spike-2.cfg"
- # Increased timeout because we use abstract_rti to artificially slow things
- # down.
- timeout_sec = 20
+ timeout_sec = 5
implements_custom_test = True
- support_hasel = False
+ support_memory_sampling = False # Needs SBA
def create(self):
- return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30,
- support_hasel=False, support_abstract_csr=False,
- vlen=512, elen=64)
+ return testlib.Spike(self)
diff --git a/src/riscv-tests/debug/targets/RISC-V/spike64.py b/src/riscv-tests/debug/targets/RISC-V/spike64.py
index ec43a11..31088ff 100644
--- a/src/riscv-tests/debug/targets/RISC-V/spike64.py
+++ b/src/riscv-tests/debug/targets/RISC-V/spike64.py
@@ -5,18 +5,18 @@
xlen = 64
ram = 0x1212340000
ram_size = 0x10000000
+ bad_address = ram - 8
instruction_hardware_breakpoint_count = 4
reset_vectors = [0x1000]
link_script_path = "spike64.lds"
-
- def __init__(self, misa=0x8000000000141125):
- self.misa = misa
+ misa = 0x8000000000141125
class spike64(targets.Target):
harts = [spike64_hart()]
openocd_config_path = "spike-1.cfg"
timeout_sec = 30
implements_custom_test = True
+ freertos_binary = "bin/RTOSDemo64.axf"
def create(self):
# 32-bit FPRs only
diff --git a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py
index cb2741e..947d061 100644
--- a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py
+++ b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py
@@ -4,6 +4,7 @@
xlen = 64
ram = 0x80000000
ram_size = 1024 * 1024
+ bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
instruction_hardware_breakpoint_count = 2
link_script_path = "HiFiveUnleashed-flash.lds"
reset_vectors = [0x1004]
@@ -12,6 +13,7 @@
xlen = 64
ram = 0x80000000
ram_size = 1024 * 1024
+ bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
instruction_hardware_breakpoint_count = 2
link_script_path = "HiFiveUnleashed-flash.lds"
reset_vectors = [0x1004]
@@ -19,4 +21,5 @@
class HiFiveUnleashedFlash(targets.Target):
support_hasel = False
harts = [E51(), U54(), U54(), U54(), U54()]
+ support_memory_sampling = False # Needs SBA
openocd_config_path = "HiFiveUnleashed.cfg"
diff --git a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg
index 3aa5538..3d20be0 100644
--- a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg
+++ b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg
@@ -55,6 +55,7 @@
foreach t [target names] {
targets $t
reg pc 0x08000000
+ arm semihosting enable
}
resume
wait_halt
diff --git a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py
index 9bf7cae..04f6cef 100644
--- a/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py
+++ b/src/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py
@@ -4,6 +4,7 @@
xlen = 64
ram = 0x80000000
ram_size = 1024 * 1024
+ bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
instruction_hardware_breakpoint_count = 2
reset_vectors = [0x1004]
misa = 0x8000000000101105
@@ -12,10 +13,12 @@
xlen = 64
ram = 0x80000000
ram_size = 1024 * 1024
+ bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
instruction_hardware_breakpoint_count = 2
reset_vectors = [0x1004]
misa = 0x800000000014112d
class HiFiveUnleashed(targets.Target):
support_hasel = False
+ support_memory_sampling = False # Needs SBA
harts = [E51(), U54(), U54(), U54(), U54()]
diff --git a/src/riscv-tests/debug/testlib.py b/src/riscv-tests/debug/testlib.py
index 36f1f17..b97b607 100644
--- a/src/riscv-tests/debug/testlib.py
+++ b/src/riscv-tests/debug/testlib.py
@@ -29,8 +29,19 @@
return relpath
return None
+class CompileError(Exception):
+ def __init__(self, stdout, stderr):
+ super().__init__()
+ self.stdout = stdout
+ self.stderr = stderr
+
+gcc_cmd = None
def compile(args): # pylint: disable=redefined-builtin
- cmd = ["riscv64-unknown-elf-gcc", "-g"]
+ if gcc_cmd:
+ cmd = [gcc_cmd]
+ else:
+ cmd = ["riscv64-unknown-elf-gcc"]
+ cmd.append("-g")
for arg in args:
found = find_file(arg)
if found:
@@ -43,10 +54,10 @@
stderr=subprocess.PIPE)
stdout, stderr = process.communicate()
if process.returncode:
- print(stdout, end=" ")
- print(stderr, end=" ")
+ print(stdout.decode('ascii'), end=" ")
+ print(stderr.decode('ascii'), end=" ")
header("")
- raise Exception("Compile failed!")
+ raise CompileError(stdout, stderr)
class Spike:
# pylint: disable=too-many-instance-attributes
@@ -54,7 +65,7 @@
def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None,
support_hasel=True, support_abstract_csr=True,
- support_haltgroups=True, vlen=128, elen=64, slen=128):
+ support_haltgroups=True, vlen=128, elen=64, harts=None):
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
@@ -67,23 +78,20 @@
self.support_haltgroups = support_haltgroups
self.vlen = vlen
self.elen = elen
- self.slen = slen
- if target.harts:
- harts = target.harts
- else:
- harts = [target]
+ self.harts = harts or target.harts or [target]
- cmd = self.command(target, harts, halted, timeout, with_jtag_gdb)
- self.infinite_loop = target.compile(harts[0],
+ cmd = self.command(target, halted, timeout, with_jtag_gdb)
+ self.infinite_loop = target.compile(self.harts[0],
"programs/checksum.c", "programs/tiny-malloc.c",
"programs/infinite_loop.S", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
cmd.append(self.infinite_loop)
self.logfile = tempfile.NamedTemporaryFile(prefix="spike-",
suffix=".log")
- self.logname = self.logfile.name
+ logname = self.logfile.name
+ self.lognames = [logname]
if print_log_names:
- real_stdout.write("Temporary spike log: %s\n" % self.logname)
+ real_stdout.write("Temporary spike log: %s\n" % logname)
self.logfile.write(("+ %s\n" % " ".join(cmd)).encode())
self.logfile.flush()
self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
@@ -93,41 +101,41 @@
self.port = None
for _ in range(30):
m = re.search(r"Listening for remote bitbang connection on "
- r"port (\d+).", open(self.logname).read())
+ r"port (\d+).", open(logname).read())
if m:
self.port = int(m.group(1))
os.environ['REMOTE_BITBANG_PORT'] = m.group(1)
break
time.sleep(0.11)
if not self.port:
- print_log(self.logname)
+ print_log(logname)
raise Exception("Didn't get spike message about bitbang "
"connection")
# pylint: disable=too-many-branches
- def command(self, target, harts, halted, timeout, with_jtag_gdb):
+ def command(self, target, halted, timeout, with_jtag_gdb):
# pylint: disable=no-self-use
if target.sim_cmd:
cmd = shlex.split(target.sim_cmd)
else:
cmd = ["spike"]
- cmd += ["-p%d" % len(harts)]
+ cmd += ["-p%d" % len(self.harts)]
- assert len(set(t.xlen for t in harts)) == 1, \
+ assert len(set(t.xlen for t in self.harts)) == 1, \
"All spike harts must have the same XLEN"
if self.isa:
isa = self.isa
else:
- isa = "RV%dG" % harts[0].xlen
+ isa = "RV%dG" % self.harts[0].xlen
cmd += ["--isa", isa]
cmd += ["--dm-auth"]
if not self.progbufsize is None:
cmd += ["--dm-progsize", str(self.progbufsize)]
- cmd += ["--dm-sba", "32"]
+ cmd += ["--dm-sba", "64"]
if not self.dmi_rti is None:
cmd += ["--dmi-rti", str(self.dmi_rti)]
@@ -145,15 +153,14 @@
cmd.append("--dm-no-halt-groups")
if 'V' in isa[2:]:
- cmd.append("--varch=vlen:%d,elen:%d,slen:%d" % (self.vlen,
- self.elen, self.slen))
+ cmd.append("--varch=vlen:%d,elen:%d" % (self.vlen, self.elen))
- assert len(set(t.ram for t in harts)) == 1, \
+ assert len(set(t.ram for t in self.harts)) == 1, \
"All spike harts must have the same RAM layout"
- assert len(set(t.ram_size for t in harts)) == 1, \
+ assert len(set(t.ram_size for t in self.harts)) == 1, \
"All spike harts must have the same RAM layout"
- os.environ['WORK_AREA'] = '0x%x' % harts[0].ram
- cmd += ["-m0x%x:0x%x" % (harts[0].ram, harts[0].ram_size)]
+ os.environ['WORK_AREA'] = '0x%x' % self.harts[0].ram
+ cmd += ["-m0x%x:0x%x" % (self.harts[0].ram, self.harts[0].ram_size)]
if timeout:
cmd = ["timeout", str(timeout)] + cmd
@@ -177,6 +184,48 @@
def wait(self, *args, **kwargs):
return self.process.wait(*args, **kwargs)
+class MultiSpike:
+ def __init__(self, spikes):
+ self.process = None
+
+ self.spikes = spikes
+ self.lognames = sum((spike.lognames for spike in spikes), [])
+ self.logfile = tempfile.NamedTemporaryFile(prefix="daisychain-",
+ suffix=".log")
+ self.lognames.append(self.logfile.name)
+
+ # Now create the daisy-chain process.
+ cmd = ["./rbb_daisychain.py", "0"] + \
+ [str(spike.port) for spike in spikes]
+ self.logfile.write(("+ %s\n" % cmd).encode())
+ self.logfile.flush()
+ self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
+ stdout=self.logfile, stderr=self.logfile)
+
+ self.port = None
+ for _ in range(30):
+ m = re.search(r"Listening on port (\d+).",
+ open(self.lognames[-1]).read())
+ if m:
+ self.port = int(m.group(1))
+ break
+ time.sleep(0.11)
+ if not self.port:
+ print_log(self.lognames[-1])
+ raise Exception("Didn't get daisy chain message about which port "
+ "it's listening on.")
+
+ os.environ['REMOTE_BITBANG_HOST'] = 'localhost'
+ os.environ['REMOTE_BITBANG_PORT'] = str(self.port)
+
+ def __del__(self):
+ if self.process:
+ try:
+ self.process.kill()
+ self.process.wait()
+ except OSError:
+ pass
+
class VcsSim:
logfile = tempfile.NamedTemporaryFile(prefix='simv', suffix='.log')
logname = logfile.name
@@ -234,7 +283,8 @@
logfile = tempfile.NamedTemporaryFile(prefix='openocd', suffix='.log')
logname = logfile.name
- def __init__(self, server_cmd=None, config=None, debug=False, timeout=60):
+ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60,
+ freertos=False):
self.timeout = timeout
if server_cmd:
@@ -263,12 +313,18 @@
self.config_file = find_file(config)
if self.config_file is None:
print("Unable to read file", config)
- exit(1)
+ sys.exit(1)
cmd += ["-f", self.config_file]
if debug:
cmd.append("-d")
+ extra_env = {}
+ if freertos:
+ extra_env['USE_FREERTOS'] = "1"
+ else:
+ extra_env['USE_FREERTOS'] = "0"
+
raw_logfile = open(Openocd.logname, "wb")
try:
spike_dasm = subprocess.Popen("spike-dasm", stdin=subprocess.PIPE,
@@ -281,17 +337,21 @@
env_entries = ("REMOTE_BITBANG_HOST", "REMOTE_BITBANG_PORT",
"WORK_AREA")
env_entries = [key for key in env_entries if key in os.environ]
- logfile.write(("+ %s%s\n" % (
- "".join("%s=%s " % (key, os.environ[key]) for key in env_entries),
- " ".join(map(pipes.quote, cmd)))).encode())
+ parts = [
+ " ".join("%s=%s" % (key, os.environ[key]) for key in env_entries),
+ " ".join("%s=%s" % (k, v) for k, v in extra_env.items()),
+ " ".join(map(pipes.quote, cmd))
+ ]
+ logfile.write(("+ %s\n" % " ".join(parts)).encode())
logfile.flush()
self.gdb_ports = []
- self.process = self.start(cmd, logfile)
+ self.process = self.start(cmd, logfile, extra_env)
- def start(self, cmd, logfile):
+ def start(self, cmd, logfile, extra_env):
+ combined_env = {**os.environ, **extra_env}
process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
- stdout=logfile, stderr=logfile)
+ stdout=logfile, stderr=logfile, env=combined_env)
try:
# Wait for OpenOCD to have made it through riscv_examine(). When
@@ -379,6 +439,11 @@
Exception.__init__(self)
self.address = address
+class CannotInsertBreakpoint(Exception):
+ def __init__(self, number):
+ Exception.__init__(self)
+ self.number = number
+
class CouldNotFetch(Exception):
def __init__(self, regname, explanation):
Exception.__init__(self)
@@ -390,6 +455,9 @@
Exception.__init__(self)
self.symbol = symbol
+ def __repr__(self):
+ return "NoSymbol(%r)" % self.symbol
+
Thread = collections.namedtuple('Thread', ('id', 'description', 'target_id',
'name', 'frame'))
@@ -412,6 +480,8 @@
lambda m: CouldNotFetch(m.group(1), m.group(2))),
(r"Cannot access memory at address (0x[0-9a-f]+)",
lambda m: CannotAccess(int(m.group(1), 0))),
+ (r"Cannot insert breakpoint (\d+).",
+ lambda m: CannotInsertBreakpoint(int(m.group(1)))),
(r'No symbol "(\w+)" in current context.',
lambda m: NoSymbol(m.group(1))),
(r'"([^"]*)"', lambda m: m.group(1)),
@@ -490,15 +560,14 @@
11, 149, 107, 163, 73, 47, 43, 173, 7, 109, 101, 103, 191, 2, 139,
97, 193, 157, 3, 29, 79, 113, 5, 89, 19, 37, 71, 179, 59, 137, 53)
- def __init__(self, ports,
- cmd="riscv64-unknown-elf-gdb",
- timeout=60, binary=None):
+ def __init__(self, target, ports, cmd=None, timeout=60, binaries=None):
assert ports
+ self.target = target
self.ports = ports
- self.cmd = cmd
+ self.cmd = cmd or "riscv64-unknown-elf-gdb"
self.timeout = timeout
- self.binary = binary
+ self.binaries = binaries or [None] * len(ports)
self.reset_delay_index = 0
self.stack = []
@@ -512,26 +581,30 @@
self.logfiles.append(logfile)
if print_log_names:
real_stdout.write("Temporary gdb log: %s\n" % logfile.name)
- child = pexpect.spawn(cmd)
+ child = pexpect.spawn(self.cmd)
child.logfile = logfile
- child.logfile.write(("+ %s\n" % cmd).encode())
+ child.logfile.write(("+ %s\n" % self.cmd).encode())
self.children.append(child)
self.active_child = self.children[0]
def connect(self):
- for port, child in zip(self.ports, self.children):
+ for port, child, binary in zip(self.ports, self.children,
+ self.binaries):
self.select_child(child)
self.wait()
- self.command("set style enabled off")
- self.command("set confirm off")
- self.command("set width 0")
- self.command("set height 0")
+ self.command("set style enabled off", reset_delays=None)
+ self.command("set confirm off", reset_delays=None)
+ self.command("set width 0", reset_delays=None)
+ self.command("set height 0", reset_delays=None)
# Force consistency.
- self.command("set print entry-values no")
- self.command("set remotetimeout %d" % self.timeout)
- self.command("target extended-remote localhost:%d" % port, ops=10)
- if self.binary:
- self.command("file %s" % self.binary)
+ self.command("set print entry-values no", reset_delays=None)
+ self.command("set remotetimeout %d" % self.timeout,
+ reset_delays=None)
+ self.command("target extended-remote localhost:%d" % port, ops=10,
+ reset_delays=None)
+ if binary:
+ output = self.command("file %s" % binary)
+ assertIn("Reading symbols", output)
threads = self.threads()
for t in threads:
hartid = None
@@ -593,11 +666,11 @@
len(self.reset_delays)
self.command("monitor riscv reset_delays %d" % reset_delays,
reset_delays=None)
- timeout = ops * self.timeout
+ timeout = max(1, ops) * self.timeout
self.active_child.sendline(command)
self.active_child.expect("\n", timeout=timeout)
self.active_child.expect(r"\(gdb\)", timeout=timeout)
- return self.active_child.before.strip().decode("utf-8")
+ return self.active_child.before.strip().decode("utf-8", errors="ignore")
def global_command(self, command):
"""Execute this command on every gdb that we control."""
@@ -606,6 +679,20 @@
self.select_child(child)
self.command(command)
+ def system_command(self, command, ops=20):
+ """Execute this command on every unique system that we control."""
+ done = set()
+ output = ""
+ with PrivateState(self):
+ for i, child in enumerate(self.children):
+ self.select_child(child)
+ if self.target.harts[i].system in done:
+ self.command("set $pc=_start")
+ else:
+ output += self.command(command, ops=ops)
+ done.add(self.target.harts[i].system)
+ return output
+
def c(self, wait=True, sync=True, checkOutput=True, ops=20):
"""
Dumb c command.
@@ -659,10 +746,16 @@
self.select_child(child)
self.interrupt()
- def x(self, address, size='w'):
- output = self.command("x/%s %s" % (size, address))
- value = int(output.split(':')[1].strip(), 0)
- return value
+ def x(self, address, size='w', count=1):
+ output = self.command("x/%d%s %s" % (count, size, address),
+ ops=count / 16)
+ values = []
+ for line in output.splitlines():
+ for value in line.split(':')[1].strip().split():
+ values.append(int(value, 0))
+ if len(values) == 1:
+ return values[0]
+ return values
def p_raw(self, obj):
output = self.command("p %s" % obj)
@@ -687,8 +780,8 @@
value = shlex.split(output.split('=')[-1].strip())[1]
return value
- def info_registers(self, group):
- output = self.command("info registers %s" % group, ops=5)
+ def info_registers(self, group="", ops=5):
+ output = self.command("info registers %s" % group, ops=ops)
result = {}
for line in output.splitlines():
m = re.match(r"(\w+)\s+({.*})(?:\s+(\(.*\)))?", line)
@@ -708,10 +801,10 @@
return output
def load(self):
- output = self.command("load", ops=1000)
+ output = self.system_command("load", ops=1000)
assert "failed" not in output
assert "Transfer rate" in output
- output = self.command("compare-sections", ops=1000)
+ output = self.system_command("compare-sections", ops=1000)
assert "matched" in output
assert "MIS" not in output
@@ -755,8 +848,6 @@
if m:
threads.append(Thread(*m.groups()))
assert threads
- #>>>if not threads:
- #>>> threads.append(Thread('1', '1', 'Default', '???'))
return threads
def thread(self, thread):
@@ -799,6 +890,8 @@
global gdb_cmd # pylint: disable=global-statement
gdb_cmd = parsed.gdb
+ global gcc_cmd # pylint: disable=global-statement
+ gcc_cmd = parsed.gcc
examine_added = False
for hart in target.harts:
@@ -882,6 +975,8 @@
help="Print out a list of tests, and exit immediately.")
parser.add_argument("test", nargs='*',
help="Run only tests that are named here.")
+ parser.add_argument("--gcc",
+ help="The command to use to start gcc.")
parser.add_argument("--gdb",
help="The command to use to start gdb.")
parser.add_argument("--misaval",
@@ -904,9 +999,10 @@
print()
def print_log(path):
- print_log_handle(path, open(path, "r"))
+ print_log_handle(path, open(path, "r", errors='ignore'))
class BaseTest:
+ # pylint: disable=too-many-instance-attributes
compiled = {}
def __init__(self, target, hart=None):
@@ -920,6 +1016,7 @@
self.binary = None
self.start = 0
self.logs = []
+ self.binaries = []
def early_applicable(self):
"""Return a false value if the test has determined it cannot run
@@ -927,24 +1024,33 @@
# pylint: disable=no-self-use
return True
+ def freertos(self):
+ """Return a true value if the test is running a FreeRTOS binary where
+ the debugger should expose FreeRTOS threads to gdb."""
+ # pylint: disable=no-self-use
+ return False
+
def setup(self):
pass
def compile(self):
compile_args = getattr(self, 'compile_args', None)
+ self.binaries = []
if compile_args:
- if compile_args not in BaseTest.compiled:
- BaseTest.compiled[compile_args] = \
- self.target.compile(self.hart, *compile_args)
- self.binary = BaseTest.compiled.get(compile_args)
+ for hart in self.target.harts:
+ key = (compile_args, hart.misa)
+ if key not in BaseTest.compiled:
+ BaseTest.compiled[key] = \
+ self.target.compile(hart, *compile_args)
+ self.binaries.append(BaseTest.compiled.get(key))
def classSetup(self):
self.compile()
self.target_process = self.target.create()
if self.target_process:
- self.logs.append(self.target_process.logname)
+ self.logs += self.target_process.lognames
try:
- self.server = self.target.server()
+ self.server = self.target.server(self)
self.logs.append(self.server.logname)
except Exception:
for log in self.logs:
@@ -960,7 +1066,7 @@
def run(self):
"""
- If compile_args is set, compile a program and set self.binary.
+ If compile_args is set, compile a program and set self.binaries.
Call setup().
@@ -1005,7 +1111,7 @@
# Get handles to logs before the files are deleted.
logs = []
for log in self.logs:
- logs.append((log, open(log, "r")))
+ logs.append((log, open(log, "r", errors='ignore')))
self.classTeardown()
for name, handle in logs:
@@ -1031,12 +1137,8 @@
def classSetup(self):
BaseTest.classSetup(self)
- if gdb_cmd:
- self.gdb = Gdb(self.server.gdb_ports, gdb_cmd,
- timeout=self.target.timeout_sec, binary=self.binary)
- else:
- self.gdb = Gdb(self.server.gdb_ports,
- timeout=self.target.timeout_sec, binary=self.binary)
+ self.gdb = Gdb(self.target, self.server.gdb_ports, cmd=gdb_cmd,
+ timeout=self.target.timeout_sec, binaries=self.binaries)
self.logs += self.gdb.lognames()
self.gdb.connect()
diff --git a/src/riscv-tests/env/encoding.h b/src/riscv-tests/env/encoding.h
index c109ce1..2aa895b 100644
--- a/src/riscv-tests/env/encoding.h
+++ b/src/riscv-tests/env/encoding.h
@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+/* See LICENSE for license details. */
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
@@ -12,7 +12,7 @@
#define MSTATUS_HPIE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
-#define MSTATUS_HPP 0x00000600
+#define MSTATUS_VS 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
@@ -32,6 +32,7 @@
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP 0x00000100
+#define SSTATUS_VS 0x00000600
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
#define SSTATUS_SUM 0x00040000
@@ -40,6 +41,9 @@
#define SSTATUS_UXL 0x0000000300000000
#define SSTATUS64_SD 0x8000000000000000
+#define USTATUS_UIE 0x00000001
+#define USTATUS_UPIE 0x00000010
+
#define DCSR_XDEBUGVER (3U<<30)
#define DCSR_NDRESET (1<<29)
#define DCSR_FULLRESET (1<<28)
@@ -95,12 +99,15 @@
#define MCONTROL_MATCH_MASK_LOW 4
#define MCONTROL_MATCH_MASK_HIGH 5
+#define MIP_USIP (1 << IRQ_U_SOFT)
#define MIP_SSIP (1 << IRQ_S_SOFT)
#define MIP_HSIP (1 << IRQ_H_SOFT)
#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_UTIP (1 << IRQ_U_TIMER)
#define MIP_STIP (1 << IRQ_S_TIMER)
#define MIP_HTIP (1 << IRQ_H_TIMER)
#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_UEIP (1 << IRQ_U_EXT)
#define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_HEIP (1 << IRQ_H_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
@@ -138,12 +145,15 @@
#define PMP_NA4 0x10
#define PMP_NAPOT 0x18
+#define IRQ_U_SOFT 0
#define IRQ_S_SOFT 1
#define IRQ_H_SOFT 2
#define IRQ_M_SOFT 3
+#define IRQ_U_TIMER 4
#define IRQ_S_TIMER 5
#define IRQ_H_TIMER 6
#define IRQ_M_TIMER 7
+#define IRQ_U_EXT 8
#define IRQ_S_EXT 9
#define IRQ_H_EXT 10
#define IRQ_M_EXT 11
@@ -156,16 +166,20 @@
#define EXT_IO_BASE 0x40000000
#define DRAM_BASE 0x80000000
-// page table entry (PTE) fields
-#define PTE_V 0x001 // Valid
-#define PTE_R 0x002 // Read
-#define PTE_W 0x004 // Write
-#define PTE_X 0x008 // Execute
-#define PTE_U 0x010 // User
-#define PTE_G 0x020 // Global
-#define PTE_A 0x040 // Accessed
-#define PTE_D 0x080 // Dirty
-#define PTE_SOFT 0x300 // Reserved for Software
+/* page table entry (PTE) fields */
+#define PTE_V 0x001 /* Valid */
+#define PTE_R 0x002 /* Read */
+#define PTE_W 0x004 /* Write */
+#define PTE_X 0x008 /* Execute */
+#define PTE_U 0x010 /* User */
+#define PTE_G 0x020 /* Global */
+#define PTE_A 0x040 /* Accessed */
+#define PTE_D 0x080 /* Dirty */
+#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */
+#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */
+#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */
+#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */
#define PTE_PPN_SHIFT 10
@@ -221,9 +235,55 @@
#endif
#endif
-/* Automatically generated by parse-opcodes. */
+/* Automatically generated by parse_opcodes. */
#ifndef RISCV_ENCODING_H
#define RISCV_ENCODING_H
+#define MATCH_SLLI_RV32 0x1013
+#define MASK_SLLI_RV32 0xfe00707f
+#define MATCH_SRLI_RV32 0x5013
+#define MASK_SRLI_RV32 0xfe00707f
+#define MATCH_SRAI_RV32 0x40005013
+#define MASK_SRAI_RV32 0xfe00707f
+#define MATCH_FRFLAGS 0x102073
+#define MASK_FRFLAGS 0xfffff07f
+#define MATCH_FSFLAGS 0x101073
+#define MASK_FSFLAGS 0xfff0707f
+#define MATCH_FSFLAGSI 0x105073
+#define MASK_FSFLAGSI 0xfff0707f
+#define MATCH_FRRM 0x202073
+#define MASK_FRRM 0xfffff07f
+#define MATCH_FSRM 0x201073
+#define MASK_FSRM 0xfff0707f
+#define MATCH_FSRMI 0x205073
+#define MASK_FSRMI 0xfff0707f
+#define MATCH_FSCSR 0x301073
+#define MASK_FSCSR 0xfff0707f
+#define MATCH_FRCSR 0x302073
+#define MASK_FRCSR 0xfffff07f
+#define MATCH_RDCYCLE 0xc0002073
+#define MASK_RDCYCLE 0xfffff07f
+#define MATCH_RDTIME 0xc0102073
+#define MASK_RDTIME 0xfffff07f
+#define MATCH_RDINSTRET 0xc0202073
+#define MASK_RDINSTRET 0xfffff07f
+#define MATCH_RDCYCLEH 0xc8002073
+#define MASK_RDCYCLEH 0xfffff07f
+#define MATCH_RDTIMEH 0xc8102073
+#define MASK_RDTIMEH 0xfffff07f
+#define MATCH_RDINSTRETH 0xc8202073
+#define MASK_RDINSTRETH 0xfffff07f
+#define MATCH_SCALL 0x73
+#define MASK_SCALL 0xffffffff
+#define MATCH_SBREAK 0x100073
+#define MASK_SBREAK 0xffffffff
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S 0xfff0707f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X 0xfff0707f
+#define MATCH_FENCE_TSO 0x8330000f
+#define MASK_FENCE_TSO 0xfff0707f
+#define MATCH_PAUSE 0x100000f
+#define MASK_PAUSE 0xffffffff
#define MATCH_BEQ 0x63
#define MASK_BEQ 0x707f
#define MATCH_BNE 0x1063
@@ -282,6 +342,26 @@
#define MASK_OR 0xfe00707f
#define MATCH_AND 0x7033
#define MASK_AND 0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB 0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH 0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW 0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU 0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU 0x707f
+#define MATCH_SB 0x23
+#define MASK_SB 0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH 0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW 0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE 0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I 0x707f
#define MATCH_ADDIW 0x1b
#define MASK_ADDIW 0x707f
#define MATCH_SLLIW 0x101b
@@ -300,32 +380,12 @@
#define MASK_SRLW 0xfe00707f
#define MATCH_SRAW 0x4000503b
#define MASK_SRAW 0xfe00707f
-#define MATCH_LB 0x3
-#define MASK_LB 0x707f
-#define MATCH_LH 0x1003
-#define MASK_LH 0x707f
-#define MATCH_LW 0x2003
-#define MASK_LW 0x707f
#define MATCH_LD 0x3003
#define MASK_LD 0x707f
-#define MATCH_LBU 0x4003
-#define MASK_LBU 0x707f
-#define MATCH_LHU 0x5003
-#define MASK_LHU 0x707f
#define MATCH_LWU 0x6003
#define MASK_LWU 0x707f
-#define MATCH_SB 0x23
-#define MASK_SB 0x707f
-#define MATCH_SH 0x1023
-#define MASK_SH 0x707f
-#define MATCH_SW 0x2023
-#define MASK_SW 0x707f
#define MATCH_SD 0x3023
#define MASK_SD 0x707f
-#define MATCH_FENCE 0xf
-#define MASK_FENCE 0x707f
-#define MATCH_FENCE_I 0x100f
-#define MASK_FENCE_I 0x707f
#define MATCH_MUL 0x2000033
#define MASK_MUL 0xfe00707f
#define MATCH_MULH 0x2001033
@@ -396,34 +456,6 @@
#define MASK_LR_D 0xf9f0707f
#define MATCH_SC_D 0x1800302f
#define MASK_SC_D 0xf800707f
-#define MATCH_ECALL 0x73
-#define MASK_ECALL 0xffffffff
-#define MATCH_EBREAK 0x100073
-#define MASK_EBREAK 0xffffffff
-#define MATCH_URET 0x200073
-#define MASK_URET 0xffffffff
-#define MATCH_SRET 0x10200073
-#define MASK_SRET 0xffffffff
-#define MATCH_MRET 0x30200073
-#define MASK_MRET 0xffffffff
-#define MATCH_DRET 0x7b200073
-#define MASK_DRET 0xffffffff
-#define MATCH_SFENCE_VMA 0x12000073
-#define MASK_SFENCE_VMA 0xfe007fff
-#define MATCH_WFI 0x10500073
-#define MASK_WFI 0xffffffff
-#define MATCH_CSRRW 0x1073
-#define MASK_CSRRW 0x707f
-#define MATCH_CSRRS 0x2073
-#define MASK_CSRRS 0x707f
-#define MATCH_CSRRC 0x3073
-#define MASK_CSRRC 0x707f
-#define MATCH_CSRRWI 0x5073
-#define MASK_CSRRWI 0x707f
-#define MATCH_CSRRSI 0x6073
-#define MASK_CSRRSI 0x707f
-#define MATCH_CSRRCI 0x7073
-#define MASK_CSRRCI 0x707f
#define MATCH_FADD_S 0x53
#define MASK_FADD_S 0xfe00007f
#define MATCH_FSUB_S 0x8000053
@@ -444,6 +476,46 @@
#define MASK_FMAX_S 0xfe00707f
#define MATCH_FSQRT_S 0x58000053
#define MASK_FSQRT_S 0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S 0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S 0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S 0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S 0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S 0xfff0007f
+#define MATCH_FMV_X_W 0xe0000053
+#define MASK_FMV_X_W 0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W 0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU 0xfff0007f
+#define MATCH_FMV_W_X 0xf0000053
+#define MASK_FMV_W_X 0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW 0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW 0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S 0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S 0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S 0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S 0x600007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S 0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S 0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L 0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU 0xfff0007f
#define MATCH_FADD_D 0x2000053
#define MASK_FADD_D 0xfe00007f
#define MATCH_FSUB_D 0xa000053
@@ -468,6 +540,46 @@
#define MASK_FCVT_D_S 0xfff0007f
#define MATCH_FSQRT_D 0x5a000053
#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D 0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D 0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D 0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D 0xfff0007f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W 0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU 0xfff0007f
+#define MATCH_FLD 0x3007
+#define MASK_FLD 0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD 0x707f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D 0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D 0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D 0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D 0x600007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D 0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D 0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D 0xfff0707f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L 0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU 0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X 0xfff0707f
#define MATCH_FADD_Q 0x6000053
#define MASK_FADD_Q 0xfe00007f
#define MATCH_FSUB_Q 0xe000053
@@ -496,118 +608,26 @@
#define MASK_FCVT_Q_D 0xfff0007f
#define MATCH_FSQRT_Q 0x5e000053
#define MASK_FSQRT_Q 0xfff0007f
-#define MATCH_FLE_S 0xa0000053
-#define MASK_FLE_S 0xfe00707f
-#define MATCH_FLT_S 0xa0001053
-#define MASK_FLT_S 0xfe00707f
-#define MATCH_FEQ_S 0xa0002053
-#define MASK_FEQ_S 0xfe00707f
-#define MATCH_FLE_D 0xa2000053
-#define MASK_FLE_D 0xfe00707f
-#define MATCH_FLT_D 0xa2001053
-#define MASK_FLT_D 0xfe00707f
-#define MATCH_FEQ_D 0xa2002053
-#define MASK_FEQ_D 0xfe00707f
#define MATCH_FLE_Q 0xa6000053
#define MASK_FLE_Q 0xfe00707f
#define MATCH_FLT_Q 0xa6001053
#define MASK_FLT_Q 0xfe00707f
#define MATCH_FEQ_Q 0xa6002053
#define MASK_FEQ_Q 0xfe00707f
-#define MATCH_FCVT_W_S 0xc0000053
-#define MASK_FCVT_W_S 0xfff0007f
-#define MATCH_FCVT_WU_S 0xc0100053
-#define MASK_FCVT_WU_S 0xfff0007f
-#define MATCH_FCVT_L_S 0xc0200053
-#define MASK_FCVT_L_S 0xfff0007f
-#define MATCH_FCVT_LU_S 0xc0300053
-#define MASK_FCVT_LU_S 0xfff0007f
-#define MATCH_FMV_X_W 0xe0000053
-#define MASK_FMV_X_W 0xfff0707f
-#define MATCH_FCLASS_S 0xe0001053
-#define MASK_FCLASS_S 0xfff0707f
-#define MATCH_FCVT_W_D 0xc2000053
-#define MASK_FCVT_W_D 0xfff0007f
-#define MATCH_FCVT_WU_D 0xc2100053
-#define MASK_FCVT_WU_D 0xfff0007f
-#define MATCH_FCVT_L_D 0xc2200053
-#define MASK_FCVT_L_D 0xfff0007f
-#define MATCH_FCVT_LU_D 0xc2300053
-#define MASK_FCVT_LU_D 0xfff0007f
-#define MATCH_FMV_X_D 0xe2000053
-#define MASK_FMV_X_D 0xfff0707f
-#define MATCH_FCLASS_D 0xe2001053
-#define MASK_FCLASS_D 0xfff0707f
#define MATCH_FCVT_W_Q 0xc6000053
#define MASK_FCVT_W_Q 0xfff0007f
#define MATCH_FCVT_WU_Q 0xc6100053
#define MASK_FCVT_WU_Q 0xfff0007f
-#define MATCH_FCVT_L_Q 0xc6200053
-#define MASK_FCVT_L_Q 0xfff0007f
-#define MATCH_FCVT_LU_Q 0xc6300053
-#define MASK_FCVT_LU_Q 0xfff0007f
-#define MATCH_FMV_X_Q 0xe6000053
-#define MASK_FMV_X_Q 0xfff0707f
#define MATCH_FCLASS_Q 0xe6001053
#define MASK_FCLASS_Q 0xfff0707f
-#define MATCH_FCVT_S_W 0xd0000053
-#define MASK_FCVT_S_W 0xfff0007f
-#define MATCH_FCVT_S_WU 0xd0100053
-#define MASK_FCVT_S_WU 0xfff0007f
-#define MATCH_FCVT_S_L 0xd0200053
-#define MASK_FCVT_S_L 0xfff0007f
-#define MATCH_FCVT_S_LU 0xd0300053
-#define MASK_FCVT_S_LU 0xfff0007f
-#define MATCH_FMV_W_X 0xf0000053
-#define MASK_FMV_W_X 0xfff0707f
-#define MATCH_FCVT_D_W 0xd2000053
-#define MASK_FCVT_D_W 0xfff0007f
-#define MATCH_FCVT_D_WU 0xd2100053
-#define MASK_FCVT_D_WU 0xfff0007f
-#define MATCH_FCVT_D_L 0xd2200053
-#define MASK_FCVT_D_L 0xfff0007f
-#define MATCH_FCVT_D_LU 0xd2300053
-#define MASK_FCVT_D_LU 0xfff0007f
-#define MATCH_FMV_D_X 0xf2000053
-#define MASK_FMV_D_X 0xfff0707f
#define MATCH_FCVT_Q_W 0xd6000053
#define MASK_FCVT_Q_W 0xfff0007f
#define MATCH_FCVT_Q_WU 0xd6100053
#define MASK_FCVT_Q_WU 0xfff0007f
-#define MATCH_FCVT_Q_L 0xd6200053
-#define MASK_FCVT_Q_L 0xfff0007f
-#define MATCH_FCVT_Q_LU 0xd6300053
-#define MASK_FCVT_Q_LU 0xfff0007f
-#define MATCH_FMV_Q_X 0xf6000053
-#define MASK_FMV_Q_X 0xfff0707f
-#define MATCH_FLW 0x2007
-#define MASK_FLW 0x707f
-#define MATCH_FLD 0x3007
-#define MASK_FLD 0x707f
#define MATCH_FLQ 0x4007
#define MASK_FLQ 0x707f
-#define MATCH_FSW 0x2027
-#define MASK_FSW 0x707f
-#define MATCH_FSD 0x3027
-#define MASK_FSD 0x707f
#define MATCH_FSQ 0x4027
#define MASK_FSQ 0x707f
-#define MATCH_FMADD_S 0x43
-#define MASK_FMADD_S 0x600007f
-#define MATCH_FMSUB_S 0x47
-#define MASK_FMSUB_S 0x600007f
-#define MATCH_FNMSUB_S 0x4b
-#define MASK_FNMSUB_S 0x600007f
-#define MATCH_FNMADD_S 0x4f
-#define MASK_FNMADD_S 0x600007f
-#define MATCH_FMADD_D 0x2000043
-#define MASK_FMADD_D 0x600007f
-#define MATCH_FMSUB_D 0x2000047
-#define MASK_FMSUB_D 0x600007f
-#define MATCH_FNMSUB_D 0x200004b
-#define MASK_FNMSUB_D 0x600007f
-#define MATCH_FNMADD_D 0x200004f
-#define MASK_FNMADD_D 0x600007f
#define MATCH_FMADD_Q 0x6000043
#define MASK_FMADD_Q 0x600007f
#define MATCH_FMSUB_Q 0x6000047
@@ -616,6 +636,50 @@
#define MASK_FNMSUB_Q 0x600007f
#define MATCH_FNMADD_Q 0x600004f
#define MASK_FNMADD_Q 0x600007f
+#define MATCH_FCVT_L_Q 0xc6200053
+#define MASK_FCVT_L_Q 0xfff0007f
+#define MATCH_FCVT_LU_Q 0xc6300053
+#define MASK_FCVT_LU_Q 0xfff0007f
+#define MATCH_FCVT_Q_L 0xd6200053
+#define MASK_FCVT_Q_L 0xfff0007f
+#define MATCH_FCVT_Q_LU 0xd6300053
+#define MASK_FCVT_Q_LU 0xfff0007f
+#define MATCH_FMV_X_Q 0xe6000053
+#define MASK_FMV_X_Q 0xfff0707f
+#define MATCH_FMV_Q_X 0xf6000053
+#define MASK_FMV_Q_X 0xfff0707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL 0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK 0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET 0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET 0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET 0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET 0xffffffff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA 0xfe007fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI 0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW 0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS 0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC 0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI 0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI 0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI 0x707f
+#define MATCH_HFENCE_VVMA 0x22000073
+#define MASK_HFENCE_VVMA 0xfe007fff
+#define MATCH_HFENCE_GVMA 0x62000073
+#define MASK_HFENCE_GVMA 0xfe007fff
#define MATCH_C_NOP 0x1
#define MASK_C_NOP 0xffff
#define MATCH_C_ADDI16SP 0x6101
@@ -626,16 +690,6 @@
#define MASK_C_JALR 0xf07f
#define MATCH_C_EBREAK 0x9002
#define MASK_C_EBREAK 0xffff
-#define MATCH_C_LD 0x6000
-#define MASK_C_LD 0xe003
-#define MATCH_C_SD 0xe000
-#define MASK_C_SD 0xe003
-#define MATCH_C_ADDIW 0x2001
-#define MASK_C_ADDIW 0xe003
-#define MATCH_C_LDSP 0x6002
-#define MASK_C_LDSP 0xe003
-#define MATCH_C_SDSP 0xe002
-#define MASK_C_SDSP 0xe003
#define MATCH_C_ADDI4SPN 0x0
#define MASK_C_ADDI4SPN 0xe003
#define MATCH_C_FLD 0x2000
@@ -672,10 +726,6 @@
#define MASK_C_OR 0xfc63
#define MATCH_C_AND 0x8c61
#define MASK_C_AND 0xfc63
-#define MATCH_C_SUBW 0x9c01
-#define MASK_C_SUBW 0xfc63
-#define MATCH_C_ADDW 0x9c21
-#define MASK_C_ADDW 0xfc63
#define MATCH_C_J 0xa001
#define MASK_C_J 0xe003
#define MATCH_C_BEQZ 0xc001
@@ -700,6 +750,34 @@
#define MASK_C_SWSP 0xe003
#define MATCH_C_FSWSP 0xe002
#define MASK_C_FSWSP 0xe003
+#define MATCH_C_SRLI_RV32 0x8001
+#define MASK_C_SRLI_RV32 0xfc03
+#define MATCH_C_SRAI_RV32 0x8401
+#define MASK_C_SRAI_RV32 0xfc03
+#define MATCH_C_SLLI_RV32 0x2
+#define MASK_C_SLLI_RV32 0xf003
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD 0xe003
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW 0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP 0xe003
+#define MATCH_C_LQ 0x2000
+#define MASK_C_LQ 0xe003
+#define MATCH_C_SQ 0xa000
+#define MASK_C_SQ 0xe003
+#define MATCH_C_LQSP 0x2002
+#define MASK_C_LQSP 0xe003
+#define MATCH_C_SQSP 0xa002
+#define MASK_C_SQSP 0xe003
#define MATCH_CUSTOM0 0xb
#define MASK_CUSTOM0 0x707f
#define MATCH_CUSTOM0_RS1 0x200b
@@ -748,9 +826,775 @@
#define MASK_CUSTOM3_RD_RS1 0x707f
#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define MATCH_VSETVLI 0x7057
+#define MASK_VSETVLI 0x8000707f
+#define MATCH_VSETVL 0x80007057
+#define MASK_VSETVL 0xfe00707f
+#define MATCH_VLB_V 0x10000007
+#define MASK_VLB_V 0x1df0707f
+#define MATCH_VLH_V 0x10005007
+#define MASK_VLH_V 0x1df0707f
+#define MATCH_VLW_V 0x10006007
+#define MASK_VLW_V 0x1df0707f
+#define MATCH_VLE_V 0x7007
+#define MASK_VLE_V 0x1df0707f
+#define MATCH_VLBU_V 0x7
+#define MASK_VLBU_V 0x1df0707f
+#define MATCH_VLHU_V 0x5007
+#define MASK_VLHU_V 0x1df0707f
+#define MATCH_VLWU_V 0x6007
+#define MASK_VLWU_V 0x1df0707f
+#define MATCH_VSB_V 0x27
+#define MASK_VSB_V 0x1df0707f
+#define MATCH_VSH_V 0x5027
+#define MASK_VSH_V 0x1df0707f
+#define MATCH_VSW_V 0x6027
+#define MASK_VSW_V 0x1df0707f
+#define MATCH_VSE_V 0x7027
+#define MASK_VSE_V 0x1df0707f
+#define MATCH_VLSB_V 0x18000007
+#define MASK_VLSB_V 0x1c00707f
+#define MATCH_VLSH_V 0x18005007
+#define MASK_VLSH_V 0x1c00707f
+#define MATCH_VLSW_V 0x18006007
+#define MASK_VLSW_V 0x1c00707f
+#define MATCH_VLSE_V 0x8007007
+#define MASK_VLSE_V 0x1c00707f
+#define MATCH_VLSBU_V 0x8000007
+#define MASK_VLSBU_V 0x1c00707f
+#define MATCH_VLSHU_V 0x8005007
+#define MASK_VLSHU_V 0x1c00707f
+#define MATCH_VLSWU_V 0x8006007
+#define MASK_VLSWU_V 0x1c00707f
+#define MATCH_VSSB_V 0x8000027
+#define MASK_VSSB_V 0x1c00707f
+#define MATCH_VSSH_V 0x8005027
+#define MASK_VSSH_V 0x1c00707f
+#define MATCH_VSSW_V 0x8006027
+#define MASK_VSSW_V 0x1c00707f
+#define MATCH_VSSE_V 0x8007027
+#define MASK_VSSE_V 0x1c00707f
+#define MATCH_VLXB_V 0x1c000007
+#define MASK_VLXB_V 0x1c00707f
+#define MATCH_VLXH_V 0x1c005007
+#define MASK_VLXH_V 0x1c00707f
+#define MATCH_VLXW_V 0x1c006007
+#define MASK_VLXW_V 0x1c00707f
+#define MATCH_VLXE_V 0xc007007
+#define MASK_VLXE_V 0x1c00707f
+#define MATCH_VLXBU_V 0xc000007
+#define MASK_VLXBU_V 0x1c00707f
+#define MATCH_VLXHU_V 0xc005007
+#define MASK_VLXHU_V 0x1c00707f
+#define MATCH_VLXWU_V 0xc006007
+#define MASK_VLXWU_V 0x1c00707f
+#define MATCH_VSXB_V 0xc000027
+#define MASK_VSXB_V 0x1c00707f
+#define MATCH_VSXH_V 0xc005027
+#define MASK_VSXH_V 0x1c00707f
+#define MATCH_VSXW_V 0xc006027
+#define MASK_VSXW_V 0x1c00707f
+#define MATCH_VSXE_V 0xc007027
+#define MASK_VSXE_V 0x1c00707f
+#define MATCH_VSUXB_V 0x1c000027
+#define MASK_VSUXB_V 0xfc00707f
+#define MATCH_VSUXH_V 0x1c005027
+#define MASK_VSUXH_V 0xfc00707f
+#define MATCH_VSUXW_V 0x1c006027
+#define MASK_VSUXW_V 0xfc00707f
+#define MATCH_VSUXE_V 0x1c007027
+#define MASK_VSUXE_V 0xfc00707f
+#define MATCH_VLBFF_V 0x11000007
+#define MASK_VLBFF_V 0x1df0707f
+#define MATCH_VLHFF_V 0x11005007
+#define MASK_VLHFF_V 0x1df0707f
+#define MATCH_VLWFF_V 0x11006007
+#define MASK_VLWFF_V 0x1df0707f
+#define MATCH_VLEFF_V 0x1007007
+#define MASK_VLEFF_V 0x1df0707f
+#define MATCH_VLBUFF_V 0x1000007
+#define MASK_VLBUFF_V 0x1df0707f
+#define MATCH_VLHUFF_V 0x1005007
+#define MASK_VLHUFF_V 0x1df0707f
+#define MATCH_VLWUFF_V 0x1006007
+#define MASK_VLWUFF_V 0x1df0707f
+#define MATCH_VL1R_V 0x2807007
+#define MASK_VL1R_V 0xfff0707f
+#define MATCH_VS1R_V 0x2807027
+#define MASK_VS1R_V 0xfff0707f
+#define MATCH_VFADD_VF 0x5057
+#define MASK_VFADD_VF 0xfc00707f
+#define MATCH_VFSUB_VF 0x8005057
+#define MASK_VFSUB_VF 0xfc00707f
+#define MATCH_VFMIN_VF 0x10005057
+#define MASK_VFMIN_VF 0xfc00707f
+#define MATCH_VFMAX_VF 0x18005057
+#define MASK_VFMAX_VF 0xfc00707f
+#define MATCH_VFSGNJ_VF 0x20005057
+#define MASK_VFSGNJ_VF 0xfc00707f
+#define MATCH_VFSGNJN_VF 0x24005057
+#define MASK_VFSGNJN_VF 0xfc00707f
+#define MATCH_VFSGNJX_VF 0x28005057
+#define MASK_VFSGNJX_VF 0xfc00707f
+#define MATCH_VFSLIDE1UP_VF 0x38005057
+#define MASK_VFSLIDE1UP_VF 0xfc00707f
+#define MATCH_VFSLIDE1DOWN_VF 0x3c005057
+#define MASK_VFSLIDE1DOWN_VF 0xfc00707f
+#define MATCH_VFMV_S_F 0x42005057
+#define MASK_VFMV_S_F 0xfff0707f
+#define MATCH_VFMERGE_VFM 0x5c005057
+#define MASK_VFMERGE_VFM 0xfe00707f
+#define MATCH_VFMV_V_F 0x5e005057
+#define MASK_VFMV_V_F 0xfff0707f
+#define MATCH_VMFEQ_VF 0x60005057
+#define MASK_VMFEQ_VF 0xfc00707f
+#define MATCH_VMFLE_VF 0x64005057
+#define MASK_VMFLE_VF 0xfc00707f
+#define MATCH_VMFLT_VF 0x6c005057
+#define MASK_VMFLT_VF 0xfc00707f
+#define MATCH_VMFNE_VF 0x70005057
+#define MASK_VMFNE_VF 0xfc00707f
+#define MATCH_VMFGT_VF 0x74005057
+#define MASK_VMFGT_VF 0xfc00707f
+#define MATCH_VMFGE_VF 0x7c005057
+#define MASK_VMFGE_VF 0xfc00707f
+#define MATCH_VFDIV_VF 0x80005057
+#define MASK_VFDIV_VF 0xfc00707f
+#define MATCH_VFRDIV_VF 0x84005057
+#define MASK_VFRDIV_VF 0xfc00707f
+#define MATCH_VFMUL_VF 0x90005057
+#define MASK_VFMUL_VF 0xfc00707f
+#define MATCH_VFRSUB_VF 0x9c005057
+#define MASK_VFRSUB_VF 0xfc00707f
+#define MATCH_VFMADD_VF 0xa0005057
+#define MASK_VFMADD_VF 0xfc00707f
+#define MATCH_VFNMADD_VF 0xa4005057
+#define MASK_VFNMADD_VF 0xfc00707f
+#define MATCH_VFMSUB_VF 0xa8005057
+#define MASK_VFMSUB_VF 0xfc00707f
+#define MATCH_VFNMSUB_VF 0xac005057
+#define MASK_VFNMSUB_VF 0xfc00707f
+#define MATCH_VFMACC_VF 0xb0005057
+#define MASK_VFMACC_VF 0xfc00707f
+#define MATCH_VFNMACC_VF 0xb4005057
+#define MASK_VFNMACC_VF 0xfc00707f
+#define MATCH_VFMSAC_VF 0xb8005057
+#define MASK_VFMSAC_VF 0xfc00707f
+#define MATCH_VFNMSAC_VF 0xbc005057
+#define MASK_VFNMSAC_VF 0xfc00707f
+#define MATCH_VFWADD_VF 0xc0005057
+#define MASK_VFWADD_VF 0xfc00707f
+#define MATCH_VFWSUB_VF 0xc8005057
+#define MASK_VFWSUB_VF 0xfc00707f
+#define MATCH_VFWADD_WF 0xd0005057
+#define MASK_VFWADD_WF 0xfc00707f
+#define MATCH_VFWSUB_WF 0xd8005057
+#define MASK_VFWSUB_WF 0xfc00707f
+#define MATCH_VFWMUL_VF 0xe0005057
+#define MASK_VFWMUL_VF 0xfc00707f
+#define MATCH_VFWMACC_VF 0xf0005057
+#define MASK_VFWMACC_VF 0xfc00707f
+#define MATCH_VFWNMACC_VF 0xf4005057
+#define MASK_VFWNMACC_VF 0xfc00707f
+#define MATCH_VFWMSAC_VF 0xf8005057
+#define MASK_VFWMSAC_VF 0xfc00707f
+#define MATCH_VFWNMSAC_VF 0xfc005057
+#define MASK_VFWNMSAC_VF 0xfc00707f
+#define MATCH_VFADD_VV 0x1057
+#define MASK_VFADD_VV 0xfc00707f
+#define MATCH_VFREDSUM_VS 0x4001057
+#define MASK_VFREDSUM_VS 0xfc00707f
+#define MATCH_VFSUB_VV 0x8001057
+#define MASK_VFSUB_VV 0xfc00707f
+#define MATCH_VFREDOSUM_VS 0xc001057
+#define MASK_VFREDOSUM_VS 0xfc00707f
+#define MATCH_VFMIN_VV 0x10001057
+#define MASK_VFMIN_VV 0xfc00707f
+#define MATCH_VFREDMIN_VS 0x14001057
+#define MASK_VFREDMIN_VS 0xfc00707f
+#define MATCH_VFMAX_VV 0x18001057
+#define MASK_VFMAX_VV 0xfc00707f
+#define MATCH_VFREDMAX_VS 0x1c001057
+#define MASK_VFREDMAX_VS 0xfc00707f
+#define MATCH_VFSGNJ_VV 0x20001057
+#define MASK_VFSGNJ_VV 0xfc00707f
+#define MATCH_VFSGNJN_VV 0x24001057
+#define MASK_VFSGNJN_VV 0xfc00707f
+#define MATCH_VFSGNJX_VV 0x28001057
+#define MASK_VFSGNJX_VV 0xfc00707f
+#define MATCH_VFMV_F_S 0x42001057
+#define MASK_VFMV_F_S 0xfe0ff07f
+#define MATCH_VMFEQ_VV 0x60001057
+#define MASK_VMFEQ_VV 0xfc00707f
+#define MATCH_VMFLE_VV 0x64001057
+#define MASK_VMFLE_VV 0xfc00707f
+#define MATCH_VMFLT_VV 0x6c001057
+#define MASK_VMFLT_VV 0xfc00707f
+#define MATCH_VMFNE_VV 0x70001057
+#define MASK_VMFNE_VV 0xfc00707f
+#define MATCH_VFDIV_VV 0x80001057
+#define MASK_VFDIV_VV 0xfc00707f
+#define MATCH_VFMUL_VV 0x90001057
+#define MASK_VFMUL_VV 0xfc00707f
+#define MATCH_VFMADD_VV 0xa0001057
+#define MASK_VFMADD_VV 0xfc00707f
+#define MATCH_VFNMADD_VV 0xa4001057
+#define MASK_VFNMADD_VV 0xfc00707f
+#define MATCH_VFMSUB_VV 0xa8001057
+#define MASK_VFMSUB_VV 0xfc00707f
+#define MATCH_VFNMSUB_VV 0xac001057
+#define MASK_VFNMSUB_VV 0xfc00707f
+#define MATCH_VFMACC_VV 0xb0001057
+#define MASK_VFMACC_VV 0xfc00707f
+#define MATCH_VFNMACC_VV 0xb4001057
+#define MASK_VFNMACC_VV 0xfc00707f
+#define MATCH_VFMSAC_VV 0xb8001057
+#define MASK_VFMSAC_VV 0xfc00707f
+#define MATCH_VFNMSAC_VV 0xbc001057
+#define MASK_VFNMSAC_VV 0xfc00707f
+#define MATCH_VFCVT_XU_F_V 0x88001057
+#define MASK_VFCVT_XU_F_V 0xfc0ff07f
+#define MATCH_VFCVT_X_F_V 0x88009057
+#define MASK_VFCVT_X_F_V 0xfc0ff07f
+#define MATCH_VFCVT_F_XU_V 0x88011057
+#define MASK_VFCVT_F_XU_V 0xfc0ff07f
+#define MATCH_VFCVT_F_X_V 0x88019057
+#define MASK_VFCVT_F_X_V 0xfc0ff07f
+#define MATCH_VFCVT_RTZ_XU_F_V 0x88031057
+#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f
+#define MATCH_VFCVT_RTZ_X_F_V 0x88039057
+#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f
+#define MATCH_VFWCVT_XU_F_V 0x88041057
+#define MASK_VFWCVT_XU_F_V 0xfc0ff07f
+#define MATCH_VFWCVT_X_F_V 0x88049057
+#define MASK_VFWCVT_X_F_V 0xfc0ff07f
+#define MATCH_VFWCVT_F_XU_V 0x88051057
+#define MASK_VFWCVT_F_XU_V 0xfc0ff07f
+#define MATCH_VFWCVT_F_X_V 0x88059057
+#define MASK_VFWCVT_F_X_V 0xfc0ff07f
+#define MATCH_VFWCVT_F_F_V 0x88061057
+#define MASK_VFWCVT_F_F_V 0xfc0ff07f
+#define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057
+#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f
+#define MATCH_VFWCVT_RTZ_X_F_V 0x88079057
+#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f
+#define MATCH_VFNCVT_XU_F_W 0x88081057
+#define MASK_VFNCVT_XU_F_W 0xfc0ff07f
+#define MATCH_VFNCVT_X_F_W 0x88089057
+#define MASK_VFNCVT_X_F_W 0xfc0ff07f
+#define MATCH_VFNCVT_F_XU_W 0x88091057
+#define MASK_VFNCVT_F_XU_W 0xfc0ff07f
+#define MATCH_VFNCVT_F_X_W 0x88099057
+#define MASK_VFNCVT_F_X_W 0xfc0ff07f
+#define MATCH_VFNCVT_F_F_W 0x880a1057
+#define MASK_VFNCVT_F_F_W 0xfc0ff07f
+#define MATCH_VFNCVT_ROD_F_F_W 0x880a9057
+#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f
+#define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057
+#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f
+#define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057
+#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f
+#define MATCH_VFSQRT_V 0x8c001057
+#define MASK_VFSQRT_V 0xfc0ff07f
+#define MATCH_VFCLASS_V 0x8c081057
+#define MASK_VFCLASS_V 0xfc0ff07f
+#define MATCH_VFWADD_VV 0xc0001057
+#define MASK_VFWADD_VV 0xfc00707f
+#define MATCH_VFWREDSUM_VS 0xc4001057
+#define MASK_VFWREDSUM_VS 0xfc00707f
+#define MATCH_VFWSUB_VV 0xc8001057
+#define MASK_VFWSUB_VV 0xfc00707f
+#define MATCH_VFWREDOSUM_VS 0xcc001057
+#define MASK_VFWREDOSUM_VS 0xfc00707f
+#define MATCH_VFWADD_WV 0xd0001057
+#define MASK_VFWADD_WV 0xfc00707f
+#define MATCH_VFWSUB_WV 0xd8001057
+#define MASK_VFWSUB_WV 0xfc00707f
+#define MATCH_VFWMUL_VV 0xe0001057
+#define MASK_VFWMUL_VV 0xfc00707f
+#define MATCH_VFDOT_VV 0xe4001057
+#define MASK_VFDOT_VV 0xfc00707f
+#define MATCH_VFWMACC_VV 0xf0001057
+#define MASK_VFWMACC_VV 0xfc00707f
+#define MATCH_VFWNMACC_VV 0xf4001057
+#define MASK_VFWNMACC_VV 0xfc00707f
+#define MATCH_VFWMSAC_VV 0xf8001057
+#define MASK_VFWMSAC_VV 0xfc00707f
+#define MATCH_VFWNMSAC_VV 0xfc001057
+#define MASK_VFWNMSAC_VV 0xfc00707f
+#define MATCH_VADD_VX 0x4057
+#define MASK_VADD_VX 0xfc00707f
+#define MATCH_VSUB_VX 0x8004057
+#define MASK_VSUB_VX 0xfc00707f
+#define MATCH_VRSUB_VX 0xc004057
+#define MASK_VRSUB_VX 0xfc00707f
+#define MATCH_VMINU_VX 0x10004057
+#define MASK_VMINU_VX 0xfc00707f
+#define MATCH_VMIN_VX 0x14004057
+#define MASK_VMIN_VX 0xfc00707f
+#define MATCH_VMAXU_VX 0x18004057
+#define MASK_VMAXU_VX 0xfc00707f
+#define MATCH_VMAX_VX 0x1c004057
+#define MASK_VMAX_VX 0xfc00707f
+#define MATCH_VAND_VX 0x24004057
+#define MASK_VAND_VX 0xfc00707f
+#define MATCH_VOR_VX 0x28004057
+#define MASK_VOR_VX 0xfc00707f
+#define MATCH_VXOR_VX 0x2c004057
+#define MASK_VXOR_VX 0xfc00707f
+#define MATCH_VRGATHER_VX 0x30004057
+#define MASK_VRGATHER_VX 0xfc00707f
+#define MATCH_VSLIDEUP_VX 0x38004057
+#define MASK_VSLIDEUP_VX 0xfc00707f
+#define MATCH_VSLIDEDOWN_VX 0x3c004057
+#define MASK_VSLIDEDOWN_VX 0xfc00707f
+#define MATCH_VADC_VXM 0x40004057
+#define MASK_VADC_VXM 0xfe00707f
+#define MATCH_VMADC_VXM 0x44004057
+#define MASK_VMADC_VXM 0xfc00707f
+#define MATCH_VSBC_VXM 0x48004057
+#define MASK_VSBC_VXM 0xfe00707f
+#define MATCH_VMSBC_VXM 0x4c004057
+#define MASK_VMSBC_VXM 0xfc00707f
+#define MATCH_VMERGE_VXM 0x5c004057
+#define MASK_VMERGE_VXM 0xfe00707f
+#define MATCH_VMV_V_X 0x5e004057
+#define MASK_VMV_V_X 0xfff0707f
+#define MATCH_VMSEQ_VX 0x60004057
+#define MASK_VMSEQ_VX 0xfc00707f
+#define MATCH_VMSNE_VX 0x64004057
+#define MASK_VMSNE_VX 0xfc00707f
+#define MATCH_VMSLTU_VX 0x68004057
+#define MASK_VMSLTU_VX 0xfc00707f
+#define MATCH_VMSLT_VX 0x6c004057
+#define MASK_VMSLT_VX 0xfc00707f
+#define MATCH_VMSLEU_VX 0x70004057
+#define MASK_VMSLEU_VX 0xfc00707f
+#define MATCH_VMSLE_VX 0x74004057
+#define MASK_VMSLE_VX 0xfc00707f
+#define MATCH_VMSGTU_VX 0x78004057
+#define MASK_VMSGTU_VX 0xfc00707f
+#define MATCH_VMSGT_VX 0x7c004057
+#define MASK_VMSGT_VX 0xfc00707f
+#define MATCH_VSADDU_VX 0x80004057
+#define MASK_VSADDU_VX 0xfc00707f
+#define MATCH_VSADD_VX 0x84004057
+#define MASK_VSADD_VX 0xfc00707f
+#define MATCH_VSSUBU_VX 0x88004057
+#define MASK_VSSUBU_VX 0xfc00707f
+#define MATCH_VSSUB_VX 0x8c004057
+#define MASK_VSSUB_VX 0xfc00707f
+#define MATCH_VSLL_VX 0x94004057
+#define MASK_VSLL_VX 0xfc00707f
+#define MATCH_VSMUL_VX 0x9c004057
+#define MASK_VSMUL_VX 0xfc00707f
+#define MATCH_VSRL_VX 0xa0004057
+#define MASK_VSRL_VX 0xfc00707f
+#define MATCH_VSRA_VX 0xa4004057
+#define MASK_VSRA_VX 0xfc00707f
+#define MATCH_VSSRL_VX 0xa8004057
+#define MASK_VSSRL_VX 0xfc00707f
+#define MATCH_VSSRA_VX 0xac004057
+#define MASK_VSSRA_VX 0xfc00707f
+#define MATCH_VNSRL_WX 0xb0004057
+#define MASK_VNSRL_WX 0xfc00707f
+#define MATCH_VNSRA_WX 0xb4004057
+#define MASK_VNSRA_WX 0xfc00707f
+#define MATCH_VNCLIPU_WX 0xb8004057
+#define MASK_VNCLIPU_WX 0xfc00707f
+#define MATCH_VNCLIP_WX 0xbc004057
+#define MASK_VNCLIP_WX 0xfc00707f
+#define MATCH_VQMACCU_VX 0xf0004057
+#define MASK_VQMACCU_VX 0xfc00707f
+#define MATCH_VQMACC_VX 0xf4004057
+#define MASK_VQMACC_VX 0xfc00707f
+#define MATCH_VQMACCUS_VX 0xf8004057
+#define MASK_VQMACCUS_VX 0xfc00707f
+#define MATCH_VQMACCSU_VX 0xfc004057
+#define MASK_VQMACCSU_VX 0xfc00707f
+#define MATCH_VADD_VV 0x57
+#define MASK_VADD_VV 0xfc00707f
+#define MATCH_VSUB_VV 0x8000057
+#define MASK_VSUB_VV 0xfc00707f
+#define MATCH_VMINU_VV 0x10000057
+#define MASK_VMINU_VV 0xfc00707f
+#define MATCH_VMIN_VV 0x14000057
+#define MASK_VMIN_VV 0xfc00707f
+#define MATCH_VMAXU_VV 0x18000057
+#define MASK_VMAXU_VV 0xfc00707f
+#define MATCH_VMAX_VV 0x1c000057
+#define MASK_VMAX_VV 0xfc00707f
+#define MATCH_VAND_VV 0x24000057
+#define MASK_VAND_VV 0xfc00707f
+#define MATCH_VOR_VV 0x28000057
+#define MASK_VOR_VV 0xfc00707f
+#define MATCH_VXOR_VV 0x2c000057
+#define MASK_VXOR_VV 0xfc00707f
+#define MATCH_VRGATHER_VV 0x30000057
+#define MASK_VRGATHER_VV 0xfc00707f
+#define MATCH_VADC_VVM 0x40000057
+#define MASK_VADC_VVM 0xfe00707f
+#define MATCH_VMADC_VVM 0x44000057
+#define MASK_VMADC_VVM 0xfc00707f
+#define MATCH_VSBC_VVM 0x48000057
+#define MASK_VSBC_VVM 0xfe00707f
+#define MATCH_VMSBC_VVM 0x4c000057
+#define MASK_VMSBC_VVM 0xfc00707f
+#define MATCH_VMERGE_VVM 0x5c000057
+#define MASK_VMERGE_VVM 0xfe00707f
+#define MATCH_VMV_V_V 0x5e000057
+#define MASK_VMV_V_V 0xfff0707f
+#define MATCH_VMSEQ_VV 0x60000057
+#define MASK_VMSEQ_VV 0xfc00707f
+#define MATCH_VMSNE_VV 0x64000057
+#define MASK_VMSNE_VV 0xfc00707f
+#define MATCH_VMSLTU_VV 0x68000057
+#define MASK_VMSLTU_VV 0xfc00707f
+#define MATCH_VMSLT_VV 0x6c000057
+#define MASK_VMSLT_VV 0xfc00707f
+#define MATCH_VMSLEU_VV 0x70000057
+#define MASK_VMSLEU_VV 0xfc00707f
+#define MATCH_VMSLE_VV 0x74000057
+#define MASK_VMSLE_VV 0xfc00707f
+#define MATCH_VSADDU_VV 0x80000057
+#define MASK_VSADDU_VV 0xfc00707f
+#define MATCH_VSADD_VV 0x84000057
+#define MASK_VSADD_VV 0xfc00707f
+#define MATCH_VSSUBU_VV 0x88000057
+#define MASK_VSSUBU_VV 0xfc00707f
+#define MATCH_VSSUB_VV 0x8c000057
+#define MASK_VSSUB_VV 0xfc00707f
+#define MATCH_VSLL_VV 0x94000057
+#define MASK_VSLL_VV 0xfc00707f
+#define MATCH_VSMUL_VV 0x9c000057
+#define MASK_VSMUL_VV 0xfc00707f
+#define MATCH_VSRL_VV 0xa0000057
+#define MASK_VSRL_VV 0xfc00707f
+#define MATCH_VSRA_VV 0xa4000057
+#define MASK_VSRA_VV 0xfc00707f
+#define MATCH_VSSRL_VV 0xa8000057
+#define MASK_VSSRL_VV 0xfc00707f
+#define MATCH_VSSRA_VV 0xac000057
+#define MASK_VSSRA_VV 0xfc00707f
+#define MATCH_VNSRL_WV 0xb0000057
+#define MASK_VNSRL_WV 0xfc00707f
+#define MATCH_VNSRA_WV 0xb4000057
+#define MASK_VNSRA_WV 0xfc00707f
+#define MATCH_VNCLIPU_WV 0xb8000057
+#define MASK_VNCLIPU_WV 0xfc00707f
+#define MATCH_VNCLIP_WV 0xbc000057
+#define MASK_VNCLIP_WV 0xfc00707f
+#define MATCH_VWREDSUMU_VS 0xc0000057
+#define MASK_VWREDSUMU_VS 0xfc00707f
+#define MATCH_VWREDSUM_VS 0xc4000057
+#define MASK_VWREDSUM_VS 0xfc00707f
+#define MATCH_VDOTU_VV 0xe0000057
+#define MASK_VDOTU_VV 0xfc00707f
+#define MATCH_VDOT_VV 0xe4000057
+#define MASK_VDOT_VV 0xfc00707f
+#define MATCH_VQMACCU_VV 0xf0000057
+#define MASK_VQMACCU_VV 0xfc00707f
+#define MATCH_VQMACC_VV 0xf4000057
+#define MASK_VQMACC_VV 0xfc00707f
+#define MATCH_VQMACCSU_VV 0xfc000057
+#define MASK_VQMACCSU_VV 0xfc00707f
+#define MATCH_VADD_VI 0x3057
+#define MASK_VADD_VI 0xfc00707f
+#define MATCH_VRSUB_VI 0xc003057
+#define MASK_VRSUB_VI 0xfc00707f
+#define MATCH_VAND_VI 0x24003057
+#define MASK_VAND_VI 0xfc00707f
+#define MATCH_VOR_VI 0x28003057
+#define MASK_VOR_VI 0xfc00707f
+#define MATCH_VXOR_VI 0x2c003057
+#define MASK_VXOR_VI 0xfc00707f
+#define MATCH_VRGATHER_VI 0x30003057
+#define MASK_VRGATHER_VI 0xfc00707f
+#define MATCH_VSLIDEUP_VI 0x38003057
+#define MASK_VSLIDEUP_VI 0xfc00707f
+#define MATCH_VSLIDEDOWN_VI 0x3c003057
+#define MASK_VSLIDEDOWN_VI 0xfc00707f
+#define MATCH_VADC_VIM 0x40003057
+#define MASK_VADC_VIM 0xfe00707f
+#define MATCH_VMADC_VIM 0x44003057
+#define MASK_VMADC_VIM 0xfc00707f
+#define MATCH_VMERGE_VIM 0x5c003057
+#define MASK_VMERGE_VIM 0xfe00707f
+#define MATCH_VMV_V_I 0x5e003057
+#define MASK_VMV_V_I 0xfff0707f
+#define MATCH_VMSEQ_VI 0x60003057
+#define MASK_VMSEQ_VI 0xfc00707f
+#define MATCH_VMSNE_VI 0x64003057
+#define MASK_VMSNE_VI 0xfc00707f
+#define MATCH_VMSLEU_VI 0x70003057
+#define MASK_VMSLEU_VI 0xfc00707f
+#define MATCH_VMSLE_VI 0x74003057
+#define MASK_VMSLE_VI 0xfc00707f
+#define MATCH_VMSGTU_VI 0x78003057
+#define MASK_VMSGTU_VI 0xfc00707f
+#define MATCH_VMSGT_VI 0x7c003057
+#define MASK_VMSGT_VI 0xfc00707f
+#define MATCH_VSADDU_VI 0x80003057
+#define MASK_VSADDU_VI 0xfc00707f
+#define MATCH_VSADD_VI 0x84003057
+#define MASK_VSADD_VI 0xfc00707f
+#define MATCH_VSLL_VI 0x94003057
+#define MASK_VSLL_VI 0xfc00707f
+#define MATCH_VMV1R_V 0x9e003057
+#define MASK_VMV1R_V 0xfe0ff07f
+#define MATCH_VMV2R_V 0x9e00b057
+#define MASK_VMV2R_V 0xfe0ff07f
+#define MATCH_VMV4R_V 0x9e01b057
+#define MASK_VMV4R_V 0xfe0ff07f
+#define MATCH_VMV8R_V 0x9e03b057
+#define MASK_VMV8R_V 0xfe0ff07f
+#define MATCH_VSRL_VI 0xa0003057
+#define MASK_VSRL_VI 0xfc00707f
+#define MATCH_VSRA_VI 0xa4003057
+#define MASK_VSRA_VI 0xfc00707f
+#define MATCH_VSSRL_VI 0xa8003057
+#define MASK_VSSRL_VI 0xfc00707f
+#define MATCH_VSSRA_VI 0xac003057
+#define MASK_VSSRA_VI 0xfc00707f
+#define MATCH_VNSRL_WI 0xb0003057
+#define MASK_VNSRL_WI 0xfc00707f
+#define MATCH_VNSRA_WI 0xb4003057
+#define MASK_VNSRA_WI 0xfc00707f
+#define MATCH_VNCLIPU_WI 0xb8003057
+#define MASK_VNCLIPU_WI 0xfc00707f
+#define MATCH_VNCLIP_WI 0xbc003057
+#define MASK_VNCLIP_WI 0xfc00707f
+#define MATCH_VREDSUM_VS 0x2057
+#define MASK_VREDSUM_VS 0xfc00707f
+#define MATCH_VREDAND_VS 0x4002057
+#define MASK_VREDAND_VS 0xfc00707f
+#define MATCH_VREDOR_VS 0x8002057
+#define MASK_VREDOR_VS 0xfc00707f
+#define MATCH_VREDXOR_VS 0xc002057
+#define MASK_VREDXOR_VS 0xfc00707f
+#define MATCH_VREDMINU_VS 0x10002057
+#define MASK_VREDMINU_VS 0xfc00707f
+#define MATCH_VREDMIN_VS 0x14002057
+#define MASK_VREDMIN_VS 0xfc00707f
+#define MATCH_VREDMAXU_VS 0x18002057
+#define MASK_VREDMAXU_VS 0xfc00707f
+#define MATCH_VREDMAX_VS 0x1c002057
+#define MASK_VREDMAX_VS 0xfc00707f
+#define MATCH_VAADDU_VV 0x20002057
+#define MASK_VAADDU_VV 0xfc00707f
+#define MATCH_VAADD_VV 0x24002057
+#define MASK_VAADD_VV 0xfc00707f
+#define MATCH_VASUBU_VV 0x28002057
+#define MASK_VASUBU_VV 0xfc00707f
+#define MATCH_VASUB_VV 0x2c002057
+#define MASK_VASUB_VV 0xfc00707f
+#define MATCH_VMV_X_S 0x42002057
+#define MASK_VMV_X_S 0xfe0ff07f
+#define MATCH_VCOMPRESS_VM 0x5e002057
+#define MASK_VCOMPRESS_VM 0xfe00707f
+#define MATCH_VMANDNOT_MM 0x60002057
+#define MASK_VMANDNOT_MM 0xfc00707f
+#define MATCH_VMAND_MM 0x64002057
+#define MASK_VMAND_MM 0xfc00707f
+#define MATCH_VMOR_MM 0x68002057
+#define MASK_VMOR_MM 0xfc00707f
+#define MATCH_VMXOR_MM 0x6c002057
+#define MASK_VMXOR_MM 0xfc00707f
+#define MATCH_VMORNOT_MM 0x70002057
+#define MASK_VMORNOT_MM 0xfc00707f
+#define MATCH_VMNAND_MM 0x74002057
+#define MASK_VMNAND_MM 0xfc00707f
+#define MATCH_VMNOR_MM 0x78002057
+#define MASK_VMNOR_MM 0xfc00707f
+#define MATCH_VMXNOR_MM 0x7c002057
+#define MASK_VMXNOR_MM 0xfc00707f
+#define MATCH_VMSBF_M 0x5000a057
+#define MASK_VMSBF_M 0xfc0ff07f
+#define MATCH_VMSOF_M 0x50012057
+#define MASK_VMSOF_M 0xfc0ff07f
+#define MATCH_VMSIF_M 0x5001a057
+#define MASK_VMSIF_M 0xfc0ff07f
+#define MATCH_VIOTA_M 0x50082057
+#define MASK_VIOTA_M 0xfc0ff07f
+#define MATCH_VID_V 0x5008a057
+#define MASK_VID_V 0xfdfff07f
+#define MATCH_VPOPC_M 0x40082057
+#define MASK_VPOPC_M 0xfc0ff07f
+#define MATCH_VFIRST_M 0x4008a057
+#define MASK_VFIRST_M 0xfc0ff07f
+#define MATCH_VDIVU_VV 0x80002057
+#define MASK_VDIVU_VV 0xfc00707f
+#define MATCH_VDIV_VV 0x84002057
+#define MASK_VDIV_VV 0xfc00707f
+#define MATCH_VREMU_VV 0x88002057
+#define MASK_VREMU_VV 0xfc00707f
+#define MATCH_VREM_VV 0x8c002057
+#define MASK_VREM_VV 0xfc00707f
+#define MATCH_VMULHU_VV 0x90002057
+#define MASK_VMULHU_VV 0xfc00707f
+#define MATCH_VMUL_VV 0x94002057
+#define MASK_VMUL_VV 0xfc00707f
+#define MATCH_VMULHSU_VV 0x98002057
+#define MASK_VMULHSU_VV 0xfc00707f
+#define MATCH_VMULH_VV 0x9c002057
+#define MASK_VMULH_VV 0xfc00707f
+#define MATCH_VMADD_VV 0xa4002057
+#define MASK_VMADD_VV 0xfc00707f
+#define MATCH_VNMSUB_VV 0xac002057
+#define MASK_VNMSUB_VV 0xfc00707f
+#define MATCH_VMACC_VV 0xb4002057
+#define MASK_VMACC_VV 0xfc00707f
+#define MATCH_VNMSAC_VV 0xbc002057
+#define MASK_VNMSAC_VV 0xfc00707f
+#define MATCH_VWADDU_VV 0xc0002057
+#define MASK_VWADDU_VV 0xfc00707f
+#define MATCH_VWADD_VV 0xc4002057
+#define MASK_VWADD_VV 0xfc00707f
+#define MATCH_VWSUBU_VV 0xc8002057
+#define MASK_VWSUBU_VV 0xfc00707f
+#define MATCH_VWSUB_VV 0xcc002057
+#define MASK_VWSUB_VV 0xfc00707f
+#define MATCH_VWADDU_WV 0xd0002057
+#define MASK_VWADDU_WV 0xfc00707f
+#define MATCH_VWADD_WV 0xd4002057
+#define MASK_VWADD_WV 0xfc00707f
+#define MATCH_VWSUBU_WV 0xd8002057
+#define MASK_VWSUBU_WV 0xfc00707f
+#define MATCH_VWSUB_WV 0xdc002057
+#define MASK_VWSUB_WV 0xfc00707f
+#define MATCH_VWMULU_VV 0xe0002057
+#define MASK_VWMULU_VV 0xfc00707f
+#define MATCH_VWMULSU_VV 0xe8002057
+#define MASK_VWMULSU_VV 0xfc00707f
+#define MATCH_VWMUL_VV 0xec002057
+#define MASK_VWMUL_VV 0xfc00707f
+#define MATCH_VWMACCU_VV 0xf0002057
+#define MASK_VWMACCU_VV 0xfc00707f
+#define MATCH_VWMACC_VV 0xf4002057
+#define MASK_VWMACC_VV 0xfc00707f
+#define MATCH_VWMACCSU_VV 0xfc002057
+#define MASK_VWMACCSU_VV 0xfc00707f
+#define MATCH_VAADDU_VX 0x20006057
+#define MASK_VAADDU_VX 0xfc00707f
+#define MATCH_VAADD_VX 0x24006057
+#define MASK_VAADD_VX 0xfc00707f
+#define MATCH_VASUBU_VX 0x28006057
+#define MASK_VASUBU_VX 0xfc00707f
+#define MATCH_VASUB_VX 0x2c006057
+#define MASK_VASUB_VX 0xfc00707f
+#define MATCH_VMV_S_X 0x42006057
+#define MASK_VMV_S_X 0xfff0707f
+#define MATCH_VSLIDE1UP_VX 0x38006057
+#define MASK_VSLIDE1UP_VX 0xfc00707f
+#define MATCH_VSLIDE1DOWN_VX 0x3c006057
+#define MASK_VSLIDE1DOWN_VX 0xfc00707f
+#define MATCH_VDIVU_VX 0x80006057
+#define MASK_VDIVU_VX 0xfc00707f
+#define MATCH_VDIV_VX 0x84006057
+#define MASK_VDIV_VX 0xfc00707f
+#define MATCH_VREMU_VX 0x88006057
+#define MASK_VREMU_VX 0xfc00707f
+#define MATCH_VREM_VX 0x8c006057
+#define MASK_VREM_VX 0xfc00707f
+#define MATCH_VMULHU_VX 0x90006057
+#define MASK_VMULHU_VX 0xfc00707f
+#define MATCH_VMUL_VX 0x94006057
+#define MASK_VMUL_VX 0xfc00707f
+#define MATCH_VMULHSU_VX 0x98006057
+#define MASK_VMULHSU_VX 0xfc00707f
+#define MATCH_VMULH_VX 0x9c006057
+#define MASK_VMULH_VX 0xfc00707f
+#define MATCH_VMADD_VX 0xa4006057
+#define MASK_VMADD_VX 0xfc00707f
+#define MATCH_VNMSUB_VX 0xac006057
+#define MASK_VNMSUB_VX 0xfc00707f
+#define MATCH_VMACC_VX 0xb4006057
+#define MASK_VMACC_VX 0xfc00707f
+#define MATCH_VNMSAC_VX 0xbc006057
+#define MASK_VNMSAC_VX 0xfc00707f
+#define MATCH_VWADDU_VX 0xc0006057
+#define MASK_VWADDU_VX 0xfc00707f
+#define MATCH_VWADD_VX 0xc4006057
+#define MASK_VWADD_VX 0xfc00707f
+#define MATCH_VWSUBU_VX 0xc8006057
+#define MASK_VWSUBU_VX 0xfc00707f
+#define MATCH_VWSUB_VX 0xcc006057
+#define MASK_VWSUB_VX 0xfc00707f
+#define MATCH_VWADDU_WX 0xd0006057
+#define MASK_VWADDU_WX 0xfc00707f
+#define MATCH_VWADD_WX 0xd4006057
+#define MASK_VWADD_WX 0xfc00707f
+#define MATCH_VWSUBU_WX 0xd8006057
+#define MASK_VWSUBU_WX 0xfc00707f
+#define MATCH_VWSUB_WX 0xdc006057
+#define MASK_VWSUB_WX 0xfc00707f
+#define MATCH_VWMULU_VX 0xe0006057
+#define MASK_VWMULU_VX 0xfc00707f
+#define MATCH_VWMULSU_VX 0xe8006057
+#define MASK_VWMULSU_VX 0xfc00707f
+#define MATCH_VWMUL_VX 0xec006057
+#define MASK_VWMUL_VX 0xfc00707f
+#define MATCH_VWMACCU_VX 0xf0006057
+#define MASK_VWMACCU_VX 0xfc00707f
+#define MATCH_VWMACC_VX 0xf4006057
+#define MASK_VWMACC_VX 0xfc00707f
+#define MATCH_VWMACCUS_VX 0xf8006057
+#define MASK_VWMACCUS_VX 0xfc00707f
+#define MATCH_VWMACCSU_VX 0xfc006057
+#define MASK_VWMACCSU_VX 0xfc00707f
+#define MATCH_VAMOSWAPW_V 0x800602f
+#define MASK_VAMOSWAPW_V 0xf800707f
+#define MATCH_VAMOADDW_V 0x602f
+#define MASK_VAMOADDW_V 0xf800707f
+#define MATCH_VAMOXORW_V 0x2000602f
+#define MASK_VAMOXORW_V 0xf800707f
+#define MATCH_VAMOANDW_V 0x6000602f
+#define MASK_VAMOANDW_V 0xf800707f
+#define MATCH_VAMOORW_V 0x4000602f
+#define MASK_VAMOORW_V 0xf800707f
+#define MATCH_VAMOMINW_V 0x8000602f
+#define MASK_VAMOMINW_V 0xf800707f
+#define MATCH_VAMOMAXW_V 0xa000602f
+#define MASK_VAMOMAXW_V 0xf800707f
+#define MATCH_VAMOMINUW_V 0xc000602f
+#define MASK_VAMOMINUW_V 0xf800707f
+#define MATCH_VAMOMAXUW_V 0xe000602f
+#define MASK_VAMOMAXUW_V 0xf800707f
+#define MATCH_VAMOSWAPE_V 0x800702f
+#define MASK_VAMOSWAPE_V 0xf800707f
+#define MATCH_VAMOADDE_V 0x702f
+#define MASK_VAMOADDE_V 0xf800707f
+#define MATCH_VAMOXORE_V 0x2000702f
+#define MASK_VAMOXORE_V 0xf800707f
+#define MATCH_VAMOANDE_V 0x6000702f
+#define MASK_VAMOANDE_V 0xf800707f
+#define MATCH_VAMOORE_V 0x4000702f
+#define MASK_VAMOORE_V 0xf800707f
+#define MATCH_VAMOMINE_V 0x8000702f
+#define MASK_VAMOMINE_V 0xf800707f
+#define MATCH_VAMOMAXE_V 0xa000702f
+#define MASK_VAMOMAXE_V 0xf800707f
+#define MATCH_VAMOMINUE_V 0xc000702f
+#define MASK_VAMOMINUE_V 0xf800707f
+#define MATCH_VAMOMAXUE_V 0xe000702f
+#define MASK_VAMOMAXUE_V 0xf800707f
+#define MATCH_VMVNFR_V 0x9e003057
+#define MASK_VMVNFR_V 0xfe00707f
#define CSR_FFLAGS 0x1
#define CSR_FRM 0x2
#define CSR_FCSR 0x3
+#define CSR_USTATUS 0x0
+#define CSR_UIE 0x4
+#define CSR_UTVEC 0x5
+#define CSR_VSTART 0x8
+#define CSR_VXSAT 0x9
+#define CSR_VXRM 0xa
+#define CSR_VCSR 0xf
+#define CSR_USCRATCH 0x40
+#define CSR_UEPC 0x41
+#define CSR_UCAUSE 0x42
+#define CSR_UTVAL 0x43
+#define CSR_UIP 0x44
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
@@ -783,7 +1627,12 @@
#define CSR_HPMCOUNTER29 0xc1d
#define CSR_HPMCOUNTER30 0xc1e
#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_VL 0xc20
+#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
#define CSR_SSTATUS 0x100
+#define CSR_SEDELEG 0x102
+#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
@@ -793,6 +1642,43 @@
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
#define CSR_SATP 0x180
+#define CSR_VSSTATUS 0x200
+#define CSR_VSIE 0x204
+#define CSR_VSTVEC 0x205
+#define CSR_VSSCRATCH 0x240
+#define CSR_VSEPC 0x241
+#define CSR_VSCAUSE 0x242
+#define CSR_VSTVAL 0x243
+#define CSR_VSIP 0x244
+#define CSR_VSATP 0x280
+#define CSR_HSTATUS 0x600
+#define CSR_HEDELEG 0x602
+#define CSR_HIDELEG 0x603
+#define CSR_HIE 0x604
+#define CSR_HTIMEDELTA 0x605
+#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
+#define CSR_HTVAL 0x643
+#define CSR_HIP 0x644
+#define CSR_HVIP 0x645
+#define CSR_HTINST 0x64a
+#define CSR_HGATP 0x680
+#define CSR_HGEIP 0xe12
+#define CSR_UTVT 0x7
+#define CSR_UNXTI 0x45
+#define CSR_UINTSTATUS 0x46
+#define CSR_USCRATCHCSW 0x48
+#define CSR_USCRATCHCSWL 0x49
+#define CSR_STVT 0x107
+#define CSR_SNXTI 0x145
+#define CSR_SINTSTATUS 0x146
+#define CSR_SSCRATCHCSW 0x148
+#define CSR_SSCRATCHCSWL 0x149
+#define CSR_MTVT 0x307
+#define CSR_MNXTI 0x345
+#define CSR_MINTSTATUS 0x346
+#define CSR_MSCRATCHCSW 0x348
+#define CSR_MSCRATCHCSWL 0x349
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
@@ -800,11 +1686,14 @@
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
+#define CSR_MCOUNTINHIBIT 0x320
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+#define CSR_MTINST 0x34a
+#define CSR_MTVAL2 0x34b
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
@@ -831,7 +1720,8 @@
#define CSR_TDATA3 0x7a3
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
#define CSR_MCYCLE 0xb00
#define CSR_MINSTRET 0xb02
#define CSR_MHPMCOUNTER3 0xb03
@@ -896,6 +1786,7 @@
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
+#define CSR_HTIMEDELTAH 0x615
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
@@ -928,6 +1819,7 @@
#define CSR_HPMCOUNTER29H 0xc9d
#define CSR_HPMCOUNTER30H 0xc9e
#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MSTATUSH 0x310
#define CSR_MCYCLEH 0xb80
#define CSR_MINSTRETH 0xb82
#define CSR_MHPMCOUNTER3H 0xb83
@@ -976,6 +1868,29 @@
#define CAUSE_STORE_PAGE_FAULT 0xf
#endif
#ifdef DECLARE_INSN
+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO)
+DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE)
DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
@@ -1005,6 +1920,16 @@
DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
DECLARE_INSN(or, MATCH_OR, MASK_OR)
DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
@@ -1014,19 +1939,9 @@
DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-DECLARE_INSN(lw, MATCH_LW, MASK_LW)
DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-DECLARE_INSN(sw, MATCH_SW, MASK_SW)
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
@@ -1062,20 +1977,6 @@
DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
-DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
-DECLARE_INSN(uret, MATCH_URET, MASK_URET)
-DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
-DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
-DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
-DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
-DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
@@ -1086,6 +1987,26 @@
DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
@@ -1098,6 +2019,26 @@
DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
@@ -1112,76 +2053,47 @@
DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
-DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
-DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
-DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
-DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
-DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
-DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
-DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
-DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
-DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
-DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
-DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
-DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
-DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
-DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA)
+DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA)
DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
-DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
@@ -1200,8 +2112,6 @@
DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
-DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
-DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
@@ -1214,6 +2124,20 @@
DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(c_srli_rv32, MATCH_C_SRLI_RV32, MASK_C_SRLI_RV32)
+DECLARE_INSN(c_srai_rv32, MATCH_C_SRAI_RV32, MASK_C_SRAI_RV32)
+DECLARE_INSN(c_slli_rv32, MATCH_C_SLLI_RV32, MASK_C_SLLI_RV32)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ)
+DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ)
+DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP)
+DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP)
DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
@@ -1238,11 +2162,400 @@
DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI)
+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
+DECLARE_INSN(vlb_v, MATCH_VLB_V, MASK_VLB_V)
+DECLARE_INSN(vlh_v, MATCH_VLH_V, MASK_VLH_V)
+DECLARE_INSN(vlw_v, MATCH_VLW_V, MASK_VLW_V)
+DECLARE_INSN(vle_v, MATCH_VLE_V, MASK_VLE_V)
+DECLARE_INSN(vlbu_v, MATCH_VLBU_V, MASK_VLBU_V)
+DECLARE_INSN(vlhu_v, MATCH_VLHU_V, MASK_VLHU_V)
+DECLARE_INSN(vlwu_v, MATCH_VLWU_V, MASK_VLWU_V)
+DECLARE_INSN(vsb_v, MATCH_VSB_V, MASK_VSB_V)
+DECLARE_INSN(vsh_v, MATCH_VSH_V, MASK_VSH_V)
+DECLARE_INSN(vsw_v, MATCH_VSW_V, MASK_VSW_V)
+DECLARE_INSN(vse_v, MATCH_VSE_V, MASK_VSE_V)
+DECLARE_INSN(vlsb_v, MATCH_VLSB_V, MASK_VLSB_V)
+DECLARE_INSN(vlsh_v, MATCH_VLSH_V, MASK_VLSH_V)
+DECLARE_INSN(vlsw_v, MATCH_VLSW_V, MASK_VLSW_V)
+DECLARE_INSN(vlse_v, MATCH_VLSE_V, MASK_VLSE_V)
+DECLARE_INSN(vlsbu_v, MATCH_VLSBU_V, MASK_VLSBU_V)
+DECLARE_INSN(vlshu_v, MATCH_VLSHU_V, MASK_VLSHU_V)
+DECLARE_INSN(vlswu_v, MATCH_VLSWU_V, MASK_VLSWU_V)
+DECLARE_INSN(vssb_v, MATCH_VSSB_V, MASK_VSSB_V)
+DECLARE_INSN(vssh_v, MATCH_VSSH_V, MASK_VSSH_V)
+DECLARE_INSN(vssw_v, MATCH_VSSW_V, MASK_VSSW_V)
+DECLARE_INSN(vsse_v, MATCH_VSSE_V, MASK_VSSE_V)
+DECLARE_INSN(vlxb_v, MATCH_VLXB_V, MASK_VLXB_V)
+DECLARE_INSN(vlxh_v, MATCH_VLXH_V, MASK_VLXH_V)
+DECLARE_INSN(vlxw_v, MATCH_VLXW_V, MASK_VLXW_V)
+DECLARE_INSN(vlxe_v, MATCH_VLXE_V, MASK_VLXE_V)
+DECLARE_INSN(vlxbu_v, MATCH_VLXBU_V, MASK_VLXBU_V)
+DECLARE_INSN(vlxhu_v, MATCH_VLXHU_V, MASK_VLXHU_V)
+DECLARE_INSN(vlxwu_v, MATCH_VLXWU_V, MASK_VLXWU_V)
+DECLARE_INSN(vsxb_v, MATCH_VSXB_V, MASK_VSXB_V)
+DECLARE_INSN(vsxh_v, MATCH_VSXH_V, MASK_VSXH_V)
+DECLARE_INSN(vsxw_v, MATCH_VSXW_V, MASK_VSXW_V)
+DECLARE_INSN(vsxe_v, MATCH_VSXE_V, MASK_VSXE_V)
+DECLARE_INSN(vsuxb_v, MATCH_VSUXB_V, MASK_VSUXB_V)
+DECLARE_INSN(vsuxh_v, MATCH_VSUXH_V, MASK_VSUXH_V)
+DECLARE_INSN(vsuxw_v, MATCH_VSUXW_V, MASK_VSUXW_V)
+DECLARE_INSN(vsuxe_v, MATCH_VSUXE_V, MASK_VSUXE_V)
+DECLARE_INSN(vlbff_v, MATCH_VLBFF_V, MASK_VLBFF_V)
+DECLARE_INSN(vlhff_v, MATCH_VLHFF_V, MASK_VLHFF_V)
+DECLARE_INSN(vlwff_v, MATCH_VLWFF_V, MASK_VLWFF_V)
+DECLARE_INSN(vleff_v, MATCH_VLEFF_V, MASK_VLEFF_V)
+DECLARE_INSN(vlbuff_v, MATCH_VLBUFF_V, MASK_VLBUFF_V)
+DECLARE_INSN(vlhuff_v, MATCH_VLHUFF_V, MASK_VLHUFF_V)
+DECLARE_INSN(vlwuff_v, MATCH_VLWUFF_V, MASK_VLWUFF_V)
+DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V)
+DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V)
+DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF)
+DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF)
+DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF)
+DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF)
+DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF)
+DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF)
+DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF)
+DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF)
+DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF)
+DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F)
+DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM)
+DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F)
+DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF)
+DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF)
+DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF)
+DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF)
+DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF)
+DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF)
+DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF)
+DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF)
+DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF)
+DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF)
+DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF)
+DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF)
+DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF)
+DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF)
+DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF)
+DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF)
+DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF)
+DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF)
+DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF)
+DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF)
+DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF)
+DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF)
+DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF)
+DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF)
+DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF)
+DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF)
+DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF)
+DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV)
+DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS)
+DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV)
+DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS)
+DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV)
+DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS)
+DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV)
+DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS)
+DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV)
+DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV)
+DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV)
+DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S)
+DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV)
+DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV)
+DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV)
+DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV)
+DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV)
+DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV)
+DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV)
+DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV)
+DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV)
+DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV)
+DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV)
+DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV)
+DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV)
+DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV)
+DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V)
+DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V)
+DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V)
+DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V)
+DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V)
+DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V)
+DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V)
+DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V)
+DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V)
+DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V)
+DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V)
+DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V)
+DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V)
+DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W)
+DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W)
+DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W)
+DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W)
+DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W)
+DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W)
+DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W)
+DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W)
+DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V)
+DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V)
+DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV)
+DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS)
+DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV)
+DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS)
+DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV)
+DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV)
+DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV)
+DECLARE_INSN(vfdot_vv, MATCH_VFDOT_VV, MASK_VFDOT_VV)
+DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV)
+DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV)
+DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV)
+DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV)
+DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX)
+DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX)
+DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX)
+DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX)
+DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX)
+DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX)
+DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX)
+DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX)
+DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX)
+DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX)
+DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX)
+DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX)
+DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX)
+DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM)
+DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM)
+DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM)
+DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM)
+DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM)
+DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X)
+DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX)
+DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX)
+DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX)
+DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX)
+DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX)
+DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX)
+DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX)
+DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX)
+DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX)
+DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX)
+DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX)
+DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX)
+DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX)
+DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX)
+DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX)
+DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX)
+DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX)
+DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX)
+DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX)
+DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX)
+DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX)
+DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX)
+DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX)
+DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX)
+DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX)
+DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX)
+DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV)
+DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV)
+DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV)
+DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV)
+DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV)
+DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV)
+DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV)
+DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV)
+DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV)
+DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV)
+DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM)
+DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM)
+DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM)
+DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM)
+DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM)
+DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V)
+DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV)
+DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV)
+DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV)
+DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV)
+DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV)
+DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV)
+DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV)
+DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV)
+DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV)
+DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV)
+DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV)
+DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV)
+DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV)
+DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV)
+DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV)
+DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV)
+DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV)
+DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV)
+DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV)
+DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV)
+DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS)
+DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS)
+DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV)
+DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV)
+DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV)
+DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV)
+DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV)
+DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI)
+DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI)
+DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI)
+DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI)
+DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI)
+DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI)
+DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI)
+DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI)
+DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM)
+DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM)
+DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM)
+DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I)
+DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI)
+DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI)
+DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI)
+DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI)
+DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI)
+DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI)
+DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI)
+DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI)
+DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI)
+DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V)
+DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V)
+DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V)
+DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V)
+DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI)
+DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI)
+DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI)
+DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI)
+DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI)
+DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI)
+DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI)
+DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI)
+DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS)
+DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS)
+DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS)
+DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS)
+DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS)
+DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS)
+DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS)
+DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS)
+DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV)
+DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV)
+DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV)
+DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV)
+DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S)
+DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM)
+DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM)
+DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM)
+DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM)
+DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM)
+DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM)
+DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM)
+DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM)
+DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM)
+DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M)
+DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
+DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)
+DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M)
+DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V)
+DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
+DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
+DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV)
+DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV)
+DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV)
+DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV)
+DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV)
+DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV)
+DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV)
+DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV)
+DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV)
+DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV)
+DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV)
+DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV)
+DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV)
+DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV)
+DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV)
+DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV)
+DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV)
+DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV)
+DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV)
+DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV)
+DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV)
+DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV)
+DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV)
+DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV)
+DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV)
+DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV)
+DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX)
+DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX)
+DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX)
+DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX)
+DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X)
+DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX)
+DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX)
+DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX)
+DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX)
+DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX)
+DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX)
+DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX)
+DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX)
+DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX)
+DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX)
+DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX)
+DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX)
+DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX)
+DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX)
+DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX)
+DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX)
+DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX)
+DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX)
+DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX)
+DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX)
+DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX)
+DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX)
+DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX)
+DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX)
+DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX)
+DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX)
+DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX)
+DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX)
+DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX)
+DECLARE_INSN(vamoswapw_v, MATCH_VAMOSWAPW_V, MASK_VAMOSWAPW_V)
+DECLARE_INSN(vamoaddw_v, MATCH_VAMOADDW_V, MASK_VAMOADDW_V)
+DECLARE_INSN(vamoxorw_v, MATCH_VAMOXORW_V, MASK_VAMOXORW_V)
+DECLARE_INSN(vamoandw_v, MATCH_VAMOANDW_V, MASK_VAMOANDW_V)
+DECLARE_INSN(vamoorw_v, MATCH_VAMOORW_V, MASK_VAMOORW_V)
+DECLARE_INSN(vamominw_v, MATCH_VAMOMINW_V, MASK_VAMOMINW_V)
+DECLARE_INSN(vamomaxw_v, MATCH_VAMOMAXW_V, MASK_VAMOMAXW_V)
+DECLARE_INSN(vamominuw_v, MATCH_VAMOMINUW_V, MASK_VAMOMINUW_V)
+DECLARE_INSN(vamomaxuw_v, MATCH_VAMOMAXUW_V, MASK_VAMOMAXUW_V)
+DECLARE_INSN(vamoswape_v, MATCH_VAMOSWAPE_V, MASK_VAMOSWAPE_V)
+DECLARE_INSN(vamoadde_v, MATCH_VAMOADDE_V, MASK_VAMOADDE_V)
+DECLARE_INSN(vamoxore_v, MATCH_VAMOXORE_V, MASK_VAMOXORE_V)
+DECLARE_INSN(vamoande_v, MATCH_VAMOANDE_V, MASK_VAMOANDE_V)
+DECLARE_INSN(vamoore_v, MATCH_VAMOORE_V, MASK_VAMOORE_V)
+DECLARE_INSN(vamomine_v, MATCH_VAMOMINE_V, MASK_VAMOMINE_V)
+DECLARE_INSN(vamomaxe_v, MATCH_VAMOMAXE_V, MASK_VAMOMAXE_V)
+DECLARE_INSN(vamominue_v, MATCH_VAMOMINUE_V, MASK_VAMOMINUE_V)
+DECLARE_INSN(vamomaxue_v, MATCH_VAMOMAXUE_V, MASK_VAMOMAXUE_V)
+DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V)
#endif
#ifdef DECLARE_CSR
DECLARE_CSR(fflags, CSR_FFLAGS)
DECLARE_CSR(frm, CSR_FRM)
DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(ustatus, CSR_USTATUS)
+DECLARE_CSR(uie, CSR_UIE)
+DECLARE_CSR(utvec, CSR_UTVEC)
+DECLARE_CSR(vstart, CSR_VSTART)
+DECLARE_CSR(vxsat, CSR_VXSAT)
+DECLARE_CSR(vxrm, CSR_VXRM)
+DECLARE_CSR(vcsr, CSR_VCSR)
+DECLARE_CSR(uscratch, CSR_USCRATCH)
+DECLARE_CSR(uepc, CSR_UEPC)
+DECLARE_CSR(ucause, CSR_UCAUSE)
+DECLARE_CSR(utval, CSR_UTVAL)
+DECLARE_CSR(uip, CSR_UIP)
DECLARE_CSR(cycle, CSR_CYCLE)
DECLARE_CSR(time, CSR_TIME)
DECLARE_CSR(instret, CSR_INSTRET)
@@ -1275,7 +2588,12 @@
DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(vl, CSR_VL)
+DECLARE_CSR(vtype, CSR_VTYPE)
+DECLARE_CSR(vlenb, CSR_VLENB)
DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sedeleg, CSR_SEDELEG)
+DECLARE_CSR(sideleg, CSR_SIDELEG)
DECLARE_CSR(sie, CSR_SIE)
DECLARE_CSR(stvec, CSR_STVEC)
DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
@@ -1285,6 +2603,43 @@
DECLARE_CSR(stval, CSR_STVAL)
DECLARE_CSR(sip, CSR_SIP)
DECLARE_CSR(satp, CSR_SATP)
+DECLARE_CSR(vsstatus, CSR_VSSTATUS)
+DECLARE_CSR(vsie, CSR_VSIE)
+DECLARE_CSR(vstvec, CSR_VSTVEC)
+DECLARE_CSR(vsscratch, CSR_VSSCRATCH)
+DECLARE_CSR(vsepc, CSR_VSEPC)
+DECLARE_CSR(vscause, CSR_VSCAUSE)
+DECLARE_CSR(vstval, CSR_VSTVAL)
+DECLARE_CSR(vsip, CSR_VSIP)
+DECLARE_CSR(vsatp, CSR_VSATP)
+DECLARE_CSR(hstatus, CSR_HSTATUS)
+DECLARE_CSR(hedeleg, CSR_HEDELEG)
+DECLARE_CSR(hideleg, CSR_HIDELEG)
+DECLARE_CSR(hie, CSR_HIE)
+DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
+DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
+DECLARE_CSR(hgeie, CSR_HGEIE)
+DECLARE_CSR(htval, CSR_HTVAL)
+DECLARE_CSR(hip, CSR_HIP)
+DECLARE_CSR(hvip, CSR_HVIP)
+DECLARE_CSR(htinst, CSR_HTINST)
+DECLARE_CSR(hgatp, CSR_HGATP)
+DECLARE_CSR(hgeip, CSR_HGEIP)
+DECLARE_CSR(utvt, CSR_UTVT)
+DECLARE_CSR(unxti, CSR_UNXTI)
+DECLARE_CSR(uintstatus, CSR_UINTSTATUS)
+DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW)
+DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL)
+DECLARE_CSR(stvt, CSR_STVT)
+DECLARE_CSR(snxti, CSR_SNXTI)
+DECLARE_CSR(sintstatus, CSR_SINTSTATUS)
+DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW)
+DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL)
+DECLARE_CSR(mtvt, CSR_MTVT)
+DECLARE_CSR(mnxti, CSR_MNXTI)
+DECLARE_CSR(mintstatus, CSR_MINTSTATUS)
+DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW)
+DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL)
DECLARE_CSR(mstatus, CSR_MSTATUS)
DECLARE_CSR(misa, CSR_MISA)
DECLARE_CSR(medeleg, CSR_MEDELEG)
@@ -1292,11 +2647,14 @@
DECLARE_CSR(mie, CSR_MIE)
DECLARE_CSR(mtvec, CSR_MTVEC)
DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT)
DECLARE_CSR(mscratch, CSR_MSCRATCH)
DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE)
DECLARE_CSR(mtval, CSR_MTVAL)
DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(mtinst, CSR_MTINST)
+DECLARE_CSR(mtval2, CSR_MTVAL2)
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
@@ -1323,7 +2681,8 @@
DECLARE_CSR(tdata3, CSR_TDATA3)
DECLARE_CSR(dcsr, CSR_DCSR)
DECLARE_CSR(dpc, CSR_DPC)
-DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
DECLARE_CSR(mcycle, CSR_MCYCLE)
DECLARE_CSR(minstret, CSR_MINSTRET)
DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
@@ -1388,6 +2747,7 @@
DECLARE_CSR(marchid, CSR_MARCHID)
DECLARE_CSR(mimpid, CSR_MIMPID)
DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
DECLARE_CSR(cycleh, CSR_CYCLEH)
DECLARE_CSR(timeh, CSR_TIMEH)
DECLARE_CSR(instreth, CSR_INSTRETH)
@@ -1420,6 +2780,7 @@
DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mstatush, CSR_MSTATUSH)
DECLARE_CSR(mcycleh, CSR_MCYCLEH)
DECLARE_CSR(minstreth, CSR_MINSTRETH)
DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
diff --git a/src/riscv-tests/env/p/riscv_test.h b/src/riscv-tests/env/p/riscv_test.h
index 3fbcb50..a08f49e 100644
--- a/src/riscv-tests/env/p/riscv_test.h
+++ b/src/riscv-tests/env/p/riscv_test.h
@@ -18,6 +18,11 @@
RVTEST_FP_ENABLE; \
.endm
+#define RVTEST_RV64UV \
+ .macro init; \
+ RVTEST_VECTOR_ENABLE; \
+ .endm
+
#define RVTEST_RV32U \
.macro init; \
.endm
@@ -27,6 +32,11 @@
RVTEST_FP_ENABLE; \
.endm
+#define RVTEST_RV32UV \
+ .macro init; \
+ RVTEST_VECTOR_ENABLE; \
+ .endm
+
#define RVTEST_RV64M \
.macro init; \
RVTEST_ENABLE_MACHINE; \
@@ -53,10 +63,44 @@
# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
#endif
+#define INIT_XREG \
+ li x1, 0; \
+ li x2, 0; \
+ li x3, 0; \
+ li x4, 0; \
+ li x5, 0; \
+ li x6, 0; \
+ li x7, 0; \
+ li x8, 0; \
+ li x9, 0; \
+ li x10, 0; \
+ li x11, 0; \
+ li x12, 0; \
+ li x13, 0; \
+ li x14, 0; \
+ li x15, 0; \
+ li x16, 0; \
+ li x17, 0; \
+ li x18, 0; \
+ li x19, 0; \
+ li x20, 0; \
+ li x21, 0; \
+ li x22, 0; \
+ li x23, 0; \
+ li x24, 0; \
+ li x25, 0; \
+ li x26, 0; \
+ li x27, 0; \
+ li x28, 0; \
+ li x29, 0; \
+ li x30, 0; \
+ li x31, 0;
+
#define INIT_PMP \
la t0, 1f; \
csrw mtvec, t0; \
- li t0, -1; /* Set up a PMP to permit all accesses */ \
+ /* Set up a PMP to permit all accesses */ \
+ li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1; \
csrw pmpaddr0, t0; \
li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
csrw pmpcfg0, t0; \
@@ -66,16 +110,16 @@
#define INIT_SATP \
la t0, 1f; \
csrw mtvec, t0; \
- csrwi sptbr, 0; \
+ csrwi satp, 0; \
.align 2; \
1:
#define DELEGATE_NO_TRAPS \
+ csrwi mie, 0; \
la t0, 1f; \
csrw mtvec, t0; \
csrwi medeleg, 0; \
csrwi mideleg, 0; \
- csrwi mie, 0; \
.align 2; \
1:
@@ -94,6 +138,13 @@
csrs mstatus, a0; \
csrwi fcsr, 0
+#define RVTEST_VECTOR_ENABLE \
+ li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \
+ (MSTATUS_FS & (MSTATUS_FS >> 1)); \
+ csrs mstatus, a0; \
+ csrwi fcsr, 0; \
+ csrwi vcsr, 0;
+
#define RISCV_MULTICORE_DISABLE \
csrr a0, mhartid; \
1: bnez a0, 1b
@@ -141,8 +192,9 @@
sw TESTNUM, tohost, t5; \
j write_tohost; \
reset_vector: \
+ INIT_XREG; \
RISCV_MULTICORE_DISABLE; \
- INIT_SATP; \
+ INIT_SATP; \
INIT_PMP; \
DELEGATE_NO_TRAPS; \
li TESTNUM, 0; \
@@ -160,8 +212,6 @@
(1 << CAUSE_USER_ECALL) | \
(1 << CAUSE_BREAKPOINT); \
csrw medeleg, t0; \
- csrr t1, medeleg; \
- bne t0, t1, other_exception; \
1: csrwi mstatus, 0; \
init; \
EXTRA_INIT; \
@@ -186,6 +236,8 @@
#define RVTEST_PASS \
fence; \
li TESTNUM, 1; \
+ li a7, 93; \
+ li a0, 0; \
ecall
#define TESTNUM gp
@@ -194,6 +246,8 @@
1: beqz TESTNUM, 1b; \
sll TESTNUM, TESTNUM, 1; \
or TESTNUM, TESTNUM, 1; \
+ li a7, 93; \
+ addi a0, TESTNUM, 0; \
ecall
//-----------------------------------------------------------------------
diff --git a/src/riscv-tests/env/v/entry.S b/src/riscv-tests/env/v/entry.S
index 9719662..49b2d3e 100644
--- a/src/riscv-tests/env/v/entry.S
+++ b/src/riscv-tests/env/v/entry.S
@@ -14,17 +14,52 @@
.section ".text.init","ax",@progbits
.globl _start
+ .align 2
_start:
j handle_reset
/* NMI vector */
+ .align 2
nmi_vector:
j wtf
+ .align 2
trap_vector:
j wtf
handle_reset:
+ li x1, 0
+ li x2, 0
+ li x3, 0
+ li x4, 0
+ li x5, 0
+ li x6, 0
+ li x7, 0
+ li x8, 0
+ li x9, 0
+ li x10, 0
+ li x11, 0
+ li x12, 0
+ li x13, 0
+ li x14, 0
+ li x15, 0
+ li x16, 0
+ li x17, 0
+ li x18, 0
+ li x19, 0
+ li x20, 0
+ li x21, 0
+ li x22, 0
+ li x23, 0
+ li x24, 0
+ li x25, 0
+ li x26, 0
+ li x27, 0
+ li x28, 0
+ li x29, 0
+ li x30, 0
+ li x31, 0
+
la t0, trap_vector
csrw mtvec, t0
la sp, STACK_TOP - SIZEOF_TRAPFRAME_T
@@ -32,6 +67,7 @@
slli t0, t0, 12
add sp, sp, t0
csrw mscratch, sp
+ call extra_boot
la a0, userstart
j vm_boot
@@ -73,6 +109,7 @@
sret
.global trap_entry
+ .align 2
trap_entry:
csrrw sp, sscratch, sp
@@ -116,7 +153,7 @@
STORE t0,32*REGBYTES(sp)
csrr t0,sepc
STORE t0,33*REGBYTES(sp)
- csrr t0,sbadaddr
+ csrr t0,stval
STORE t0,34*REGBYTES(sp)
csrr t0,scause
STORE t0,35*REGBYTES(sp)
diff --git a/src/riscv-tests/env/v/riscv_test.h b/src/riscv-tests/env/v/riscv_test.h
index 8ca9ffd..c74e05d 100644
--- a/src/riscv-tests/env/v/riscv_test.h
+++ b/src/riscv-tests/env/v/riscv_test.h
@@ -12,9 +12,18 @@
#undef RVTEST_FP_ENABLE
#define RVTEST_FP_ENABLE fssr x0
+#undef RVTEST_VECTOR_ENABLE
+#define RVTEST_VECTOR_ENABLE \
+ csrwi fcsr, 0; \
+ csrwi vcsr, 0;
+
#undef RVTEST_CODE_BEGIN
#define RVTEST_CODE_BEGIN \
.text; \
+ .global extra_boot; \
+extra_boot: \
+ EXTRA_INIT \
+ ret; \
.global userstart; \
userstart: \
init
diff --git a/src/riscv-tests/env/v/vm.c b/src/riscv-tests/env/v/vm.c
index a2e5533..9802fb7 100644
--- a/src/riscv-tests/env/v/vm.c
+++ b/src/riscv-tests/env/v/vm.c
@@ -6,11 +6,19 @@
#include "riscv_test.h"
+#if __riscv_xlen == 32
+# define SATP_MODE_CHOICE SATP_MODE_SV32
+#elif defined(Sv48)
+# define SATP_MODE_CHOICE SATP_MODE_SV48
+#else
+# define SATP_MODE_CHOICE SATP_MODE_SV39
+#endif
+
void trap_entry();
void pop_tf(trapframe_t*);
-volatile uint64_t tohost;
-volatile uint64_t fromhost;
+extern volatile uint64_t tohost;
+extern volatile uint64_t fromhost;
static void do_tohost(uint64_t tohost_value)
{
@@ -62,13 +70,21 @@
#define l1pt pt[0]
#define user_l2pt pt[1]
-#if __riscv_xlen == 64
+#if SATP_MODE_CHOICE == SATP_MODE_SV48
+# define NPT 6
+# define kernel_l2pt pt[2]
+# define kernel_l3pt pt[3]
+# define user_l3pt pt[4]
+# define user_llpt pt[5]
+#elif SATP_MODE_CHOICE == SATP_MODE_SV39
# define NPT 4
-#define kernel_l2pt pt[2]
-# define user_l3pt pt[3]
-#else
+# define kernel_l2pt pt[2]
+# define user_llpt pt[3]
+#elif SATP_MODE_CHOICE == SATP_MODE_SV32
# define NPT 2
-# define user_l3pt user_l2pt
+# define user_llpt user_l2pt
+#else
+# error Unknown SATP_MODE_CHOICE
#endif
pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE)));
@@ -100,10 +116,10 @@
if (node->addr)
{
// check accessed and dirty bits
- assert(user_l3pt[addr/PGSIZE] & PTE_A);
+ assert(user_llpt[addr/PGSIZE] & PTE_A);
uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) {
- assert(user_l3pt[addr/PGSIZE] & PTE_D);
+ assert(user_llpt[addr/PGSIZE] & PTE_D);
memcpy((void*)addr, uva2kva(addr), PGSIZE);
}
write_csr(sstatus, sstatus);
@@ -125,12 +141,12 @@
assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
addr = addr/PGSIZE*PGSIZE;
- if (user_l3pt[addr/PGSIZE]) {
- if (!(user_l3pt[addr/PGSIZE] & PTE_A)) {
- user_l3pt[addr/PGSIZE] |= PTE_A;
+ if (user_llpt[addr/PGSIZE]) {
+ if (!(user_llpt[addr/PGSIZE] & PTE_A)) {
+ user_llpt[addr/PGSIZE] |= PTE_A;
} else {
- assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
- user_l3pt[addr/PGSIZE] |= PTE_D;
+ assert(!(user_llpt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
+ user_llpt[addr/PGSIZE] |= PTE_D;
}
flush_page(addr);
return;
@@ -143,7 +159,7 @@
freelist_tail = 0;
uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X;
- user_l3pt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
+ user_llpt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
flush_page(addr);
assert(user_mapping[addr/PGSIZE].addr == 0);
@@ -153,10 +169,10 @@
memcpy((void*)addr, uva2kva(addr), PGSIZE);
write_csr(sstatus, sstatus);
- user_l3pt[addr/PGSIZE] = new_pte;
+ user_llpt[addr/PGSIZE] = new_pte;
flush_page(addr);
- __builtin___clear_cache(0,0);
+ asm volatile ("fence.i");
}
void handle_trap(trapframe_t* tf)
@@ -194,7 +210,7 @@
static void coherence_torture()
{
// cause coherence misses without affecting program semantics
- unsigned int random = ENTROPY;
+ uint64_t random = ENTROPY;
while (1) {
uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4);
#ifdef __riscv_atomic
@@ -209,7 +225,7 @@
void vm_boot(uintptr_t test_addr)
{
- unsigned int random = ENTROPY;
+ uint64_t random = ENTROPY;
if (read_csr(mhartid) > 0)
coherence_torture();
@@ -221,27 +237,38 @@
// map user to lowermost megapage
l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
// map kernel to uppermost megapage
-#if __riscv_xlen == 64
+#if SATP_MODE_CHOICE == SATP_MODE_SV48
+ l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+ kernel_l2pt[PTES_PER_PT-1] = ((pte_t)kernel_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+ kernel_l3pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
+ user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+ user_l3pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+#elif SATP_MODE_CHOICE == SATP_MODE_SV39
l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
- user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
- uintptr_t vm_choice = SATP_MODE_SV39;
-#else
+ user_l2pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+#elif SATP_MODE_CHOICE == SATP_MODE_SV32
l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
- uintptr_t vm_choice = SATP_MODE_SV32;
+#else
+# error
#endif
- write_csr(sptbr, ((uintptr_t)l1pt >> PGSHIFT) |
- (vm_choice * (SATP_MODE & ~(SATP_MODE<<1))));
+ uintptr_t vm_choice = SATP_MODE_CHOICE;
+ uintptr_t satp_value = ((uintptr_t)l1pt >> PGSHIFT)
+ | (vm_choice * (SATP_MODE & ~(SATP_MODE<<1)));
+ write_csr(satp, satp_value);
+ if (read_csr(satp) != satp_value)
+ assert(!"unsupported satp mode");
// Set up PMPs if present, ignoring illegal instruction trap if not.
uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
+ uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1;
asm volatile ("la t0, 1f\n\t"
"csrrw t0, mtvec, t0\n\t"
"csrw pmpaddr0, %1\n\t"
"csrw pmpcfg0, %0\n\t"
".align 2\n\t"
- "1:"
- : : "r" (pmpc), "r" (-1UL) : "t0");
+ "1: csrw mtvec, t0"
+ : : "r" (pmpc), "r" (pmpa) : "t0");
// set up supervisor trap handling
write_csr(stvec, pa2kva(trap_entry));
@@ -251,8 +278,8 @@
(1 << CAUSE_FETCH_PAGE_FAULT) |
(1 << CAUSE_LOAD_PAGE_FAULT) |
(1 << CAUSE_STORE_PAGE_FAULT));
- // FPU on; accelerator on; allow supervisor access to user memory access
- write_csr(mstatus, MSTATUS_FS | MSTATUS_XS);
+ // FPU on; accelerator on; vector unit on
+ write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_VS);
write_csr(mie, 0);
random = 1 + (random % MAX_TEST_PAGES);
diff --git a/src/riscv-tests/isa/Makefile b/src/riscv-tests/isa/Makefile
index 4e1ba20..a514cb2 100644
--- a/src/riscv-tests/isa/Makefile
+++ b/src/riscv-tests/isa/Makefile
@@ -13,7 +13,9 @@
include $(src_dir)/rv64ua/Makefrag
include $(src_dir)/rv64uf/Makefrag
include $(src_dir)/rv64ud/Makefrag
+include $(src_dir)/rv64uzfh/Makefrag
include $(src_dir)/rv64si/Makefrag
+include $(src_dir)/rv64ssvnapot/Makefrag
include $(src_dir)/rv64mi/Makefrag
endif
include $(src_dir)/rv32ui/Makefrag
@@ -22,6 +24,7 @@
include $(src_dir)/rv32ua/Makefrag
include $(src_dir)/rv32uf/Makefrag
include $(src_dir)/rv32ud/Makefrag
+include $(src_dir)/rv32uzfh/Makefrag
include $(src_dir)/rv32si/Makefrag
include $(src_dir)/rv32mi/Makefrag
@@ -67,7 +70,11 @@
.PHONY: $(1)
+COMPILER_SUPPORTS_$(1) := $$(shell $$(RISCV_GCC) $(2) -c -x c /dev/null -o /dev/null 2> /dev/null; echo $$$$?)
+
+ifeq ($$(COMPILER_SUPPORTS_$(1)),0)
tests += $$($(1)_tests)
+endif
endef
@@ -77,6 +84,7 @@
$(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
$(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
$(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32))
$(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32))
$(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32))
ifeq ($(XLEN),64)
@@ -86,14 +94,16 @@
$(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64))
$(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64))
$(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64))
$(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64))
$(eval $(call compile_template,rv64mi,-march=rv64g -mabi=lp64))
endif
tests_dump = $(addsuffix .dump, $(tests))
tests_hex = $(addsuffix .hex, $(tests))
-tests_out = $(addsuffix .out, $(spike_tests))
-tests32_out = $(addsuffix .out32, $(spike32_tests))
+tests_out = $(addsuffix .out, $(filter rv64%,$(tests)))
+tests32_out = $(addsuffix .out32, $(filter rv32%,$(tests)))
run: $(tests_out) $(tests32_out)
diff --git a/src/riscv-tests/isa/macros/scalar/test_macros.h b/src/riscv-tests/isa/macros/scalar/test_macros.h
index ed4cab0..a8a78a7 100644
--- a/src/riscv-tests/isa/macros/scalar/test_macros.h
+++ b/src/riscv-tests/isa/macros/scalar/test_macros.h
@@ -374,11 +374,35 @@
# Tests floating-point instructions
#-----------------------------------------------------------------------
+#define qNaNh 0h:7e00
+#define sNaNh 0h:7c01
#define qNaNf 0f:7fc00000
#define sNaNf 0f:7f800001
#define qNaN 0d:7ff8000000000000
#define sNaN 0d:7ff0000000000001
+#define TEST_FP_OP_H_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ flh f0, 0(a0); \
+ flh f1, 2(a0); \
+ flh f2, 4(a0); \
+ lh a3, 6(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .align 1; \
+ test_ ## testnum ## _data: \
+ .float16 val1; \
+ .float16 val2; \
+ .float16 val3; \
+ .result; \
+ .popsection
+
#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
test_ ## testnum: \
li TESTNUM, testnum; \
@@ -460,6 +484,19 @@
TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
+#define TEST_FCVT_H_S( testnum, result, val1 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \
+ fcvt.s.h f3, f0; fcvt.h.s f3, f3; fmv.x.h a0, f3)
+
+#define TEST_FCVT_H_D( testnum, result, val1 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \
+ fcvt.d.h f3, f0; fcvt.h.d f3, f3; fmv.x.h a0, f3)
+
+
+#define TEST_FP_OP1_H( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.h a0, f3;)
+
#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.s a0, f3)
@@ -477,6 +514,10 @@
TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.s a0, f3)
+#define TEST_FP_OP1_H_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.h a0, f3)
+
#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
@@ -490,6 +531,10 @@
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
inst f3, f0, f1; fmv.x.s a0, f3)
+#define TEST_FP_OP2_H( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, 0.0, \
+ inst f3, f0, f1; fmv.x.h a0, f3)
+
#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
@@ -503,6 +548,10 @@
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
inst f3, f0, f1, f2; fmv.x.s a0, f3)
+#define TEST_FP_OP3_H( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, val3, \
+ inst f3, f0, f1, f2; fmv.x.h a0, f3)
+
#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
@@ -516,6 +565,10 @@
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
inst a0, f0, rm)
+#define TEST_FP_INT_OP_H( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+ inst a0, f0, rm)
+
#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst a0, f0, f1; li t2, 0)
@@ -528,6 +581,10 @@
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
inst a0, f0, f1)
+#define TEST_FP_CMP_OP_H( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, val1, val2, 0.0, \
+ inst a0, f0, f1)
+
#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
inst a0, f0, f1; li t2, 0)
@@ -571,6 +628,22 @@
.float result; \
.popsection
+#define TEST_INT_FP_OP_H( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ lh a3, 0(a0); \
+ li a0, val1; \
+ inst f0, a0; \
+ fsflags x0; \
+ fmv.x.h a0, f0; \
+ bne a0, a3, fail; \
+ .pushsection .data; \
+ .align 1; \
+ test_ ## testnum ## _data: \
+ .float16 result; \
+ .popsection
+
#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
diff --git a/src/riscv-tests/isa/rv32mi/Makefrag b/src/riscv-tests/isa/rv32mi/Makefrag
index 5ee7edc..2142570 100644
--- a/src/riscv-tests/isa/rv32mi/Makefrag
+++ b/src/riscv-tests/isa/rv32mi/Makefrag
@@ -14,5 +14,3 @@
shamt \
rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests))
-
-spike32_tests += $(rv32mi_p_tests)
diff --git a/src/riscv-tests/isa/rv32mi/shamt.S b/src/riscv-tests/isa/rv32mi/shamt.S
index 622fde4..c4d154c 100644
--- a/src/riscv-tests/isa/rv32mi/shamt.S
+++ b/src/riscv-tests/isa/rv32mi/shamt.S
@@ -21,6 +21,7 @@
TEST_PASSFAIL
+.align 2
.global mtvec_handler
mtvec_handler:
# Trapping on test 3 is good.
diff --git a/src/riscv-tests/isa/rv32si/Makefrag b/src/riscv-tests/isa/rv32si/Makefrag
index f423788..1392c24 100644
--- a/src/riscv-tests/isa/rv32si/Makefrag
+++ b/src/riscv-tests/isa/rv32si/Makefrag
@@ -11,5 +11,3 @@
wfi \
rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
-
-spike32_tests += $(rv32si_p_tests)
diff --git a/src/riscv-tests/isa/rv32ua/Makefrag b/src/riscv-tests/isa/rv32ua/Makefrag
index 575dc6a..3f35810 100644
--- a/src/riscv-tests/isa/rv32ua/Makefrag
+++ b/src/riscv-tests/isa/rv32ua/Makefrag
@@ -8,5 +8,3 @@
rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests))
rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests))
-
-spike32_tests += $(rv32ua_p_tests) $(rv32ua_v_tests)
diff --git a/src/riscv-tests/isa/rv32uc/Makefrag b/src/riscv-tests/isa/rv32uc/Makefrag
index 0586843..674ece8 100644
--- a/src/riscv-tests/isa/rv32uc/Makefrag
+++ b/src/riscv-tests/isa/rv32uc/Makefrag
@@ -7,5 +7,3 @@
rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests))
rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests))
-
-spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests)
diff --git a/src/riscv-tests/isa/rv32ud/Makefrag b/src/riscv-tests/isa/rv32ud/Makefrag
index 998078d..1a38cec 100644
--- a/src/riscv-tests/isa/rv32ud/Makefrag
+++ b/src/riscv-tests/isa/rv32ud/Makefrag
@@ -11,5 +11,3 @@
rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests))
rv32ud_v_tests = $(addprefix rv32ud-v-, $(rv32ud_sc_tests))
-
-spike32_tests += $(rv32ud_p_tests) $(rv32ud_v_tests)
diff --git a/src/riscv-tests/isa/rv32uf/Makefrag b/src/riscv-tests/isa/rv32uf/Makefrag
index 7dde664..e82705f 100644
--- a/src/riscv-tests/isa/rv32uf/Makefrag
+++ b/src/riscv-tests/isa/rv32uf/Makefrag
@@ -8,5 +8,3 @@
rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests))
rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests))
-
-spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests)
diff --git a/src/riscv-tests/isa/rv32ui/Makefrag b/src/riscv-tests/isa/rv32ui/Makefrag
index 7903b15..48a3a91 100644
--- a/src/riscv-tests/isa/rv32ui/Makefrag
+++ b/src/riscv-tests/isa/rv32ui/Makefrag
@@ -23,5 +23,3 @@
rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
-
-spike32_tests += $(rv32ui_p_tests) $(rv32ui_v_tests)
diff --git a/src/riscv-tests/isa/rv32um/Makefrag b/src/riscv-tests/isa/rv32um/Makefrag
index 1391c6a..688cb5a 100644
--- a/src/riscv-tests/isa/rv32um/Makefrag
+++ b/src/riscv-tests/isa/rv32um/Makefrag
@@ -9,5 +9,3 @@
rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))
rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests))
-
-spike32_tests += $(rv32um_p_tests) $(rv32um_v_tests)
diff --git a/src/riscv-tests/isa/rv32uzfh/Makefrag b/src/riscv-tests/isa/rv32uzfh/Makefrag
new file mode 100644
index 0000000..f24cdf2
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/Makefrag
@@ -0,0 +1,10 @@
+#=======================================================================
+# Makefrag for rv32uzfh tests
+#-----------------------------------------------------------------------
+
+rv32uzfh_sc_tests = \
+ fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+ ldst move recoding \
+
+rv32uzfh_p_tests = $(addprefix rv32uzfh-p-, $(rv32uzfh_sc_tests))
+rv32uzfh_v_tests = $(addprefix rv32uzfh-v-, $(rv32uzfh_sc_tests))
diff --git a/src/riscv-tests/isa/rv32uzfh/fadd.S b/src/riscv-tests/isa/rv32uzfh/fadd.S
new file mode 100644
index 0000000..11dba9d
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fadd.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fclass.S b/src/riscv-tests/isa/rv32uzfh/fclass.S
new file mode 100644
index 0000000..b1fcf24
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fclass.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fclass.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fcmp.S b/src/riscv-tests/isa/rv32uzfh/fcmp.S
new file mode 100644
index 0000000..9793dea
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fcmp.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fcmp.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fcvt.S b/src/riscv-tests/isa/rv32uzfh/fcvt.S
new file mode 100644
index 0000000..2b5bf5a
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fcvt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uzfh/fcvt.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fcvt_w.S b/src/riscv-tests/isa/rv32uzfh/fcvt_w.S
new file mode 100644
index 0000000..d532b35
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fcvt_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uzfh/fcvt_w.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fdiv.S b/src/riscv-tests/isa/rv32uzfh/fdiv.S
new file mode 100644
index 0000000..2bf43a7
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fdiv.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fdiv.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fmadd.S b/src/riscv-tests/isa/rv32uzfh/fmadd.S
new file mode 100644
index 0000000..2a5ea91
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fmadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fmadd.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/fmin.S b/src/riscv-tests/isa/rv32uzfh/fmin.S
new file mode 100644
index 0000000..360e02f
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/fmin.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fmin.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/ldst.S b/src/riscv-tests/isa/rv32uzfh/ldst.S
new file mode 100644
index 0000000..7f09872
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a0, 0xcafe4000, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); lw a0, 20(a1))
+ TEST_CASE(3, a0, 0xabadbf80, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); lw a0, 24(a1))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+.word 0xbf80bf80
+.word 0x40004000
+.word 0x40404040
+.word 0xc080c080
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv32uzfh/move.S b/src/riscv-tests/isa/rv32uzfh/move.S
new file mode 100644
index 0000000..b399a76
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/move.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/move.S"
diff --git a/src/riscv-tests/isa/rv32uzfh/recoding.S b/src/riscv-tests/isa/rv32uzfh/recoding.S
new file mode 100644
index 0000000..271a5cb
--- /dev/null
+++ b/src/riscv-tests/isa/rv32uzfh/recoding.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/recoding.S"
diff --git a/src/riscv-tests/isa/rv64mi/Makefrag b/src/riscv-tests/isa/rv64mi/Makefrag
index c81c24e..645622b 100644
--- a/src/riscv-tests/isa/rv64mi/Makefrag
+++ b/src/riscv-tests/isa/rv64mi/Makefrag
@@ -14,5 +14,3 @@
sbreak \
rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests))
-
-spike_tests += $(rv64mi_p_tests)
diff --git a/src/riscv-tests/isa/rv64mi/illegal.S b/src/riscv-tests/isa/rv64mi/illegal.S
index 5531570..fb6643b 100644
--- a/src/riscv-tests/isa/rv64mi/illegal.S
+++ b/src/riscv-tests/isa/rv64mi/illegal.S
@@ -59,14 +59,18 @@
1:
# Make sure WFI doesn't trap when TW=0.
wfi
-bad3:
- .word 0
- j fail
-bad4:
- # Make sure WFI does trap when TW=1.
- wfi
- j fail
+ # Check if paging is supported (Set SUM & MXR and read it back)
+ and t0, t0, zero
+ li t0, (SSTATUS_SUM | SSTATUS_MXR)
+ csrc sstatus, t0
+ and t1, t1, zero
+ li t1, (SSTATUS_SUM | SSTATUS_MXR)
+ csrs sstatus, t1
+ csrr t2, sstatus
+ and t2, t2, t0
+ beqz t2, bare_s_1
+ csrc sstatus, t0
# Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
sfence.vma
@@ -83,6 +87,7 @@
csrr t0, sptbr
j fail
+test_tsr:
# Make sure SRET doesn't trap when TSR=0.
la t0, bad8
csrw sepc, t0
@@ -102,7 +107,26 @@
sret
1:
j fail
+ j skip_bare_s
+bare_s_1:
+ # Make sure SFENCE.VMA trap when TVM=0.
+ sfence.vma
+ j fail
+
+bare_s_2:
+ # Set TVM=1. TVM should stay 0 and SFENCE.VMA should still trap
+ sfence.vma
+ j fail
+
+ # And access to satp should not trap
+ csrr t0, sptbr
+bare_s_3:
+ .word 0
+ j fail
+ j test_tsr
+
+skip_bare_s:
TEST_PASSFAIL
.align 8
@@ -144,10 +168,6 @@
la t1, bad2
beq t0, t1, 2f
- la t1, bad3
- beq t0, t1, 3f
- la t1, bad4
- beq t0, t1, 4f
la t1, bad5
beq t0, t1, 5f
la t1, bad6
@@ -158,20 +178,20 @@
beq t0, t1, 8f
la t1, bad9
beq t0, t1, 9f
+ la t1, bare_s_1
+ beq t0, t1, 5f
+ la t1, bare_s_2
+ beq t0, t1, 7f
+ la t1, bare_s_3
+ beq t0, t1, 7f
j fail
2:
-4:
6:
7:
addi t0, t0, 8
csrw mepc, t0
mret
-3:
- li t1, MSTATUS_TW
- csrs mstatus, t1
- j 2b
-
5:
li t1, MSTATUS_TVM
csrs mstatus, t1
diff --git a/src/riscv-tests/isa/rv64mi/mcsr.S b/src/riscv-tests/isa/rv64mi/mcsr.S
index e0256e7..03cf29a 100644
--- a/src/riscv-tests/isa/rv64mi/mcsr.S
+++ b/src/riscv-tests/isa/rv64mi/mcsr.S
@@ -28,7 +28,7 @@
csrr a0, marchid
csrr a0, mvendorid
- # Check that writing hte following CSRs doesn't cause an exception
+ # Check that writing the following CSRs doesn't cause an exception
li t0, 0
csrs mtvec, t0
csrs mepc, t0
diff --git a/src/riscv-tests/isa/rv64si/Makefrag b/src/riscv-tests/isa/rv64si/Makefrag
index f01a332..604005c 100644
--- a/src/riscv-tests/isa/rv64si/Makefrag
+++ b/src/riscv-tests/isa/rv64si/Makefrag
@@ -12,5 +12,3 @@
sbreak \
rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests))
-
-spike_tests += $(rv64si_p_tests)
diff --git a/src/riscv-tests/isa/rv64si/csr.S b/src/riscv-tests/isa/rv64si/csr.S
index 09494ef..0ba1e1f 100644
--- a/src/riscv-tests/isa/rv64si/csr.S
+++ b/src/riscv-tests/isa/rv64si/csr.S
@@ -46,8 +46,17 @@
#endif
#endif
+ # Make sure reading the cycle counter in four ways doesn't trap.
+#ifdef __MACHINE_MODE
+ TEST_CASE(25, x0, 0, csrrc x0, cycle, x0);
+ TEST_CASE(26, x0, 0, csrrs x0, cycle, x0);
+ TEST_CASE(27, x0, 0, csrrci x0, cycle, 0);
+ TEST_CASE(28, x0, 0, csrrsi x0, cycle, 0);
+#endif
+
TEST_CASE(20, a0, 0, csrw sscratch, zero; csrr a0, sscratch);
TEST_CASE(21, a0, 0, csrrwi a0, sscratch, 0; csrrwi a0, sscratch, 0xF);
+ TEST_CASE(22, a0, 0x1f, csrrsi x0, sscratch, 0x10; csrr a0, sscratch);
csrwi sscratch, 3
TEST_CASE( 2, a0, 3, csrr a0, sscratch);
@@ -86,6 +95,19 @@
srli a0, a0, 20 # a0 = a0 >> 20
andi a0, a0, 1 # a0 = a0 & 1
beqz a0, finish # if no user mode, skip the rest of these checks
+
+ # Enable access to the cycle counter
+ csrwi mcounteren, 1
+
+ # Figure out if 'S' is set in misa
+ csrr a0, misa # a0 = csr(misa)
+ srli a0, a0, 18 # a0 = a0 >> 20
+ andi a0, a0, 1 # a0 = a0 & 1
+ beqz a0, 1f
+
+ # Enable access to the cycle counter
+ csrwi scounteren, 1
+1:
#endif /* __MACHINE_MODE */
# jump to user land
diff --git a/src/riscv-tests/isa/rv64si/sbreak.S b/src/riscv-tests/isa/rv64si/sbreak.S
index 31efff8..475bf65 100644
--- a/src/riscv-tests/isa/rv64si/sbreak.S
+++ b/src/riscv-tests/isa/rv64si/sbreak.S
@@ -17,6 +17,7 @@
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
+ #define stvec mtvec
#define sepc mepc
#define sret mret
#define stvec_handler mtvec_handler
@@ -35,6 +36,13 @@
stvec_handler:
li t1, CAUSE_BREAKPOINT
csrr t0, scause
+ # Check if CLIC mode
+ csrr t2, stvec
+ andi t2, t2, 2
+ # Skip masking if non-CLIC mode
+ beqz t2, skip_mask
+ andi t0, t0, 255
+skip_mask:
bne t0, t1, fail
la t1, do_break
csrr t0, sepc
diff --git a/src/riscv-tests/isa/rv64si/scall.S b/src/riscv-tests/isa/rv64si/scall.S
index 9956e03..eb6f1e6 100644
--- a/src/riscv-tests/isa/rv64si/scall.S
+++ b/src/riscv-tests/isa/rv64si/scall.S
@@ -17,6 +17,7 @@
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
+ #define stvec mtvec
#define sepc mepc
#define sret mret
#define stvec_handler mtvec_handler
@@ -67,6 +68,13 @@
.global stvec_handler
stvec_handler:
csrr t0, scause
+ # Check if CLIC mode
+ csrr t2, stvec
+ andi t2, t2, 2
+ # Skip masking if non-CLIC mode
+ beqz t2, skip_mask
+ andi t0, t0, 255
+skip_mask:
bne t0, t1, fail
la t2, do_scall
csrr t0, sepc
diff --git a/src/riscv-tests/isa/rv64ssvnapot/Makefrag b/src/riscv-tests/isa/rv64ssvnapot/Makefrag
new file mode 100644
index 0000000..79e1f2a
--- /dev/null
+++ b/src/riscv-tests/isa/rv64ssvnapot/Makefrag
@@ -0,0 +1,8 @@
+#=======================================================================
+# Makefrag for rv64ssvnapot tests
+#-----------------------------------------------------------------------
+
+rv64ssvnapot_sc_tests = \
+ napot \
+
+rv64ssvnapot_p_tests = $(addprefix rv64ssvnapot-p-, $(rv64ssvnapot_sc_tests))
diff --git a/src/riscv-tests/isa/rv64ssvnapot/napot.S b/src/riscv-tests/isa/rv64ssvnapot/napot.S
new file mode 100644
index 0000000..92d2b49
--- /dev/null
+++ b/src/riscv-tests/isa/rv64ssvnapot/napot.S
@@ -0,0 +1,172 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# napot.S
+#-----------------------------------------------------------------------------
+#
+# Test Svnapot
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+#if (DRAM_BASE >> 30 << 30) != DRAM_BASE
+# error This test requires DRAM_BASE be SV39 superpage-aligned
+#endif
+
+#if __riscv_xlen != 64
+# error This test requires RV64
+#endif
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+ # Construct the page table
+
+#define MY_VA 0x40201010
+ # VPN 2 == VPN 1 == VPN 0 == 0x1
+ # Page offset == 0x10
+
+ ####
+
+ # Level 0 PTE contents
+
+ # PPN
+ la a0, my_data
+ srl a0, a0, 12
+
+ # adjust the PPN to be in NAPOT form
+ li a1, ~0xF
+ and a0, a0, a1
+ ori a0, a0, 0x8
+
+ # attributes
+ sll a0, a0, PTE_PPN_SHIFT
+ li a1, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D | PTE_N
+ or a0, a0, a1
+
+ # Level 0 PTE address
+ la a1, page_table
+ addi a1, a1, ((MY_VA >> 12) & 0x1FF) * 8
+
+ # Level 0 PTE store
+ sd a0, (a1)
+
+ ####
+
+ # Level 1 PTE contents
+ la a0, page_table
+ srl a0, a0, 12
+ sll a0, a0, PTE_PPN_SHIFT
+ li a1, PTE_V
+ or a0, a0, a1
+
+ # Level 1 PTE address
+ la a1, page_table
+ addi a1, a1, ((MY_VA >> 21) & 0x1FF) * 8
+ li a2, 1 << 12
+ add a1, a1, a2
+
+ # Level 1 PTE store
+ sd a0, (a1)
+
+ ####
+
+ # Level 2 PTE contents
+ la a0, page_table
+ li a1, 1 << 12
+ add a0, a0, a1
+ srl a0, a0, 12
+ sll a0, a0, PTE_PPN_SHIFT
+ li a1, PTE_V
+ or a0, a0, a1
+
+ # Level 2 PTE address
+ la a1, page_table
+ addi a1, a1, ((MY_VA >> 30) & 0x1FF) * 8
+ li a2, 2 << 12
+ add a1, a1, a2
+
+ # Level 2 PTE store
+ sd a0, (a1)
+
+ ####
+
+ # Do a load from the PA that would be written if the PTE were misinterpreted as non-NAPOT
+ la a0, my_data
+ li a1, ~0xFFFF
+ and a0, a0, a1
+ li a1, 0x8000 | (MY_VA & 0xFFF)
+ or a3, a0, a1
+ li a1, 0
+ sw a1, (a3)
+
+ ####
+ li TESTNUM, 1
+
+ ## Turn on VM
+ la a1, page_table
+ li a2, 2 << 12
+ add a1, a1, a2
+ srl a1, a1, 12
+ li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
+ or a0, a0, a1
+ csrw satp, a0
+ sfence.vma
+
+ # Set up MPRV with MPP=S and SUM=1, so loads and stores use S-mode and S can access U pages
+ li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV | MSTATUS_SUM
+ csrs mstatus, a1
+
+ # Do a store to MY_VA
+ li a0, MY_VA
+ li a1, 42
+ sw a1, (a0)
+
+ # Clear MPRV
+ li a1, MSTATUS_MPRV
+ csrc mstatus, a1
+
+ # Do a load from the PA that would be written if the PTE were misinterpreted as non-NAPOT
+ lw a1, (a3)
+
+ # Check the result
+ li a0, 42
+ beq a1, a0, die
+
+ # Do a load from the PA for MY_VA
+ la a0, my_data
+ li a1, MY_VA & 0xFFFF
+ add a0, a0, a1
+ lw a1, (a0)
+ li a2, 42
+
+ # Check the result
+ bne a1, a2, die
+
+ ####
+
+ RVTEST_PASS
+
+ TEST_PASSFAIL
+
+ .align 2
+ .global mtvec_handler
+mtvec_handler:
+die:
+ RVTEST_FAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+.align 20
+page_table: .dword 0
+
+.align 20
+my_data: .dword 0
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64ua/Makefrag b/src/riscv-tests/isa/rv64ua/Makefrag
index 3af8856..f0e8ad6 100644
--- a/src/riscv-tests/isa/rv64ua/Makefrag
+++ b/src/riscv-tests/isa/rv64ua/Makefrag
@@ -9,5 +9,3 @@
rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests))
rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests))
-
-spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests)
diff --git a/src/riscv-tests/isa/rv64ua/lrsc.S b/src/riscv-tests/isa/rv64ua/lrsc.S
index c7589d7..5711f8d 100644
--- a/src/riscv-tests/isa/rv64ua/lrsc.S
+++ b/src/riscv-tests/isa/rv64ua/lrsc.S
@@ -37,14 +37,20 @@
lw a4, foo; \
)
-# make sure that sc with the wrong reservation fails.
-# TODO is this actually mandatory behavior?
-TEST_CASE( 4, a4, 1, \
- la a0, foo; \
- la a1, fooTest3; \
- lr.w a1, (a1); \
- sc.w a4, a1, (a0); \
-)
+#
+# Disable test case 4 for now. It assumes a <1K reservation granule, when
+# in reality any size granule is valid. After discussion in issue #315,
+# decided to simply disable the test for now.
+# (See https://github.com/riscv/riscv-tests/issues/315)
+#
+## make sure that sc with the wrong reservation fails.
+## TODO is this actually mandatory behavior?
+#TEST_CASE( 4, a4, 1, \
+# la a0, foo; \
+# la a1, fooTest3; \
+# lr.w a1, (a1); \
+# sc.w a4, a1, (a0); \
+#)
#define LOG_ITERATIONS 10
diff --git a/src/riscv-tests/isa/rv64uc/Makefrag b/src/riscv-tests/isa/rv64uc/Makefrag
index f5e49b7..557ca6c 100644
--- a/src/riscv-tests/isa/rv64uc/Makefrag
+++ b/src/riscv-tests/isa/rv64uc/Makefrag
@@ -7,5 +7,3 @@
rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests))
rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests))
-
-spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests)
diff --git a/src/riscv-tests/isa/rv64ud/Makefrag b/src/riscv-tests/isa/rv64ud/Makefrag
index 9cffb5d..de456cd 100644
--- a/src/riscv-tests/isa/rv64ud/Makefrag
+++ b/src/riscv-tests/isa/rv64ud/Makefrag
@@ -8,5 +8,3 @@
rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests))
rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests))
-
-spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests)
diff --git a/src/riscv-tests/isa/rv64ud/structural.S b/src/riscv-tests/isa/rv64ud/structural.S
index 3cf87aa..726275a 100644
--- a/src/riscv-tests/isa/rv64ud/structural.S
+++ b/src/riscv-tests/isa/rv64ud/structural.S
@@ -19,7 +19,9 @@
li x2, 0x3FF0000000000000
li x1, 0x3F800000
-#define TEST(nops, errcode) \
+#define TEST(testnum, nops) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
fmv.d.x f4, x0 ;\
fmv.s.x f3, x0 ;\
fmv.d.x f2, x2 ;\
@@ -32,21 +34,21 @@
fmv.x.d x4, f4 ;\
fmv.x.s x5, f3 ;\
beq x1, x5, 2f ;\
- RVTEST_FAIL ;\
+ j fail;\
2:beq x2, x4, 2f ;\
- RVTEST_FAIL; \
+ j fail; \
2:fmv.d.x f2, zero ;\
fmv.s.x f1, zero ;\
-TEST(;,2)
-TEST(nop,4)
-TEST(nop;nop,6)
-TEST(nop;nop;nop,8)
-TEST(nop;nop;nop;nop,10)
-TEST(nop;nop;nop;nop;nop,12)
-TEST(nop;nop;nop;nop;nop;nop,14)
+TEST(1,;)
+TEST(2,nop)
+TEST(3,nop;nop)
+TEST(4,nop;nop;nop)
+TEST(5,nop;nop;nop;nop)
+TEST(6,nop;nop;nop;nop;nop)
+TEST(7,nop;nop;nop;nop;nop;nop)
-RVTEST_PASS
+TEST_PASSFAIL
RVTEST_CODE_END
diff --git a/src/riscv-tests/isa/rv64uf/Makefrag b/src/riscv-tests/isa/rv64uf/Makefrag
index 33c11db..2b67905 100644
--- a/src/riscv-tests/isa/rv64uf/Makefrag
+++ b/src/riscv-tests/isa/rv64uf/Makefrag
@@ -8,5 +8,3 @@
rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
-
-spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests)
diff --git a/src/riscv-tests/isa/rv64ui/Makefrag b/src/riscv-tests/isa/rv64ui/Makefrag
index 1867ea5..b5bf7ba 100644
--- a/src/riscv-tests/isa/rv64ui/Makefrag
+++ b/src/riscv-tests/isa/rv64ui/Makefrag
@@ -23,5 +23,3 @@
rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
-
-spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests)
diff --git a/src/riscv-tests/isa/rv64ui/fence_i.S b/src/riscv-tests/isa/rv64ui/fence_i.S
index 2893c5e..e6a6912 100644
--- a/src/riscv-tests/isa/rv64ui/fence_i.S
+++ b/src/riscv-tests/isa/rv64ui/fence_i.S
@@ -24,7 +24,7 @@
fence.i
la a5, 2f
-jalr a6, a5, 0
+jalr t1, a5, 0
TEST_CASE( 2, a3, 444, nop )
# test prefetcher hit
@@ -38,7 +38,7 @@
.align 6
la a5, 3f
-jalr a6, a5, 0
+jalr t1, a5, 0
TEST_CASE( 3, a3, 777, nop )
TEST_PASSFAIL
@@ -54,9 +54,9 @@
addi a3, a3, 333
2: addi a3, a3, 222
-jalr a5, a6, 0
+jalr a5, t1, 0
3: addi a3, a3, 555
-jalr a5, a6, 0
+jalr a5, t1, 0
RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64um/Makefrag b/src/riscv-tests/isa/rv64um/Makefrag
index 360bd7a..2a9e66d 100644
--- a/src/riscv-tests/isa/rv64um/Makefrag
+++ b/src/riscv-tests/isa/rv64um/Makefrag
@@ -9,5 +9,3 @@
rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests))
rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests))
-
-spike_tests += $(rv64um_p_tests) $(rv64um_v_tests)
diff --git a/src/riscv-tests/isa/rv64uzfh/Makefrag b/src/riscv-tests/isa/rv64uzfh/Makefrag
new file mode 100644
index 0000000..af247fd
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/Makefrag
@@ -0,0 +1,10 @@
+#=======================================================================
+# Makefrag for rv64uzfh tests
+#-----------------------------------------------------------------------
+
+rv64uzfh_sc_tests = \
+ fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+ ldst move recoding \
+
+rv64uzfh_p_tests = $(addprefix rv64uzfh-p-, $(rv64uzfh_sc_tests))
+rv64uzfh_v_tests = $(addprefix rv64uzfh-v-, $(rv64uzfh_sc_tests))
diff --git a/src/riscv-tests/isa/rv64uzfh/fadd.S b/src/riscv-tests/isa/rv64uzfh/fadd.S
new file mode 100644
index 0000000..6ca7f33
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fadd.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f{add|sub|mul}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_H( 2, fadd.h, 0, 3.5, 2.5, 1.0 );
+ TEST_FP_OP2_H( 3, fadd.h, 1, -1234, -1235.1, 1.1 );
+ TEST_FP_OP2_H( 4, fadd.h, 1, 3.14, 3.13, 0.01 );
+
+ TEST_FP_OP2_H( 5, fsub.h, 0, 1.5, 2.5, 1.0 );
+ TEST_FP_OP2_H( 6, fsub.h, 1, -1234, -1235.1, -1.1 );
+ TEST_FP_OP2_H( 7, fsub.h, 1, 3.14, 3.15, 0.01 );
+
+ TEST_FP_OP2_H( 8, fmul.h, 0, 2.5, 2.5, 1.0 );
+ TEST_FP_OP2_H( 9, fmul.h, 0, 1235.1, -1235.1, -1.0 );
+ TEST_FP_OP2_H(10, fmul.h, 1, 1.1, 11.0, 0.1 );
+
+ # Is the canonical NaN generated for Inf - Inf?
+ TEST_FP_OP2_H(11, fsub.h, 0x10, qNaNh, Inf, Inf);
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fclass.S b/src/riscv-tests/isa/rv64uzfh/fclass.S
new file mode 100644
index 0000000..86af7e5
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fclass.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ #define TEST_FCLASS_H(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.h.x fa0, a0; \
+ fclass.h a0, fa0)
+
+ TEST_FCLASS_H( 2, 1 << 0, 0xfc00 )
+ TEST_FCLASS_H( 3, 1 << 1, 0xbc00 )
+ TEST_FCLASS_H( 4, 1 << 2, 0x83ff )
+ TEST_FCLASS_H( 5, 1 << 3, 0x8000 )
+ TEST_FCLASS_H( 6, 1 << 4, 0x0000 )
+ TEST_FCLASS_H( 7, 1 << 5, 0x03ff )
+ TEST_FCLASS_H( 8, 1 << 6, 0x3c00 )
+ TEST_FCLASS_H( 9, 1 << 7, 0x7c00 )
+ TEST_FCLASS_H(10, 1 << 8, 0x7c01 )
+ TEST_FCLASS_H(11, 1 << 9, 0x7e00 )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fcmp.S b/src/riscv-tests/isa/rv64uzfh/fcmp.S
new file mode 100644
index 0000000..9f8a4e3
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fcmp.S
@@ -0,0 +1,37 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcmp.S
+#-----------------------------------------------------------------------------
+#
+# Test f{eq|lt|le}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_CMP_OP_H( 2, feq.h, 0x00, 1, -1.36, -1.36)
+ TEST_FP_CMP_OP_H( 3, fle.h, 0x00, 1, -1.36, -1.36)
+ TEST_FP_CMP_OP_H( 4, flt.h, 0x00, 0, -1.36, -1.36)
+
+ TEST_FP_CMP_OP_H( 5, feq.h, 0x00, 0, -1.37, -1.36)
+ TEST_FP_CMP_OP_H( 6, fle.h, 0x00, 1, -1.37, -1.36)
+ TEST_FP_CMP_OP_H( 7, flt.h, 0x00, 1, -1.37, -1.36)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fcvt.S b/src/riscv-tests/isa/rv64uzfh/fcvt.S
new file mode 100644
index 0000000..5f130e1
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fcvt.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt.h.{wu|w|lu|l}, fcvt.h.d, and fcvt.d.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_INT_FP_OP_H( 2, fcvt.h.w, 2.0, 2);
+ TEST_INT_FP_OP_H( 3, fcvt.h.w, -2.0, -2);
+
+ TEST_INT_FP_OP_H( 4, fcvt.h.wu, 2.0, 2);
+ TEST_INT_FP_OP_H( 5, fcvt.h.wu, 0h:7c00, -2);
+
+#if __riscv_xlen >= 64
+ TEST_INT_FP_OP_H( 6, fcvt.h.l, 2.0, 2);
+ TEST_INT_FP_OP_H( 7, fcvt.h.l, -2.0, -2);
+
+ TEST_INT_FP_OP_H( 8, fcvt.h.lu, 2.0, 2);
+ TEST_INT_FP_OP_H( 9, fcvt.h.lu, 0h:7c00, -2);
+#endif
+
+ TEST_FCVT_H_S( 10, -1.5, -1.5)
+
+#if __riscv_xlen >= 64
+ TEST_FCVT_H_D( 11, -1.5, -1.5)
+#endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fcvt_w.S b/src/riscv-tests/isa/rv64uzfh/fcvt_w.S
new file mode 100644
index 0000000..013ecac
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fcvt_w.S
@@ -0,0 +1,104 @@
+# See LICENSE for license details.
+#*****************************************************************************
+# fcvt_w.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt{wu|w|lu|l}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_INT_OP_H( 2, fcvt.w.h, 0x01, -1, -1.1, rtz);
+ TEST_FP_INT_OP_H( 3, fcvt.w.h, 0x00, -1, -1.0, rtz);
+ TEST_FP_INT_OP_H( 4, fcvt.w.h, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_H( 5, fcvt.w.h, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_H( 6, fcvt.w.h, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_H( 7, fcvt.w.h, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_H( 8, fcvt.w.h, 0x00, -2054, 0h:e803, rtz);
+ TEST_FP_INT_OP_H( 9, fcvt.w.h, 0x00, 2054, 0h:6803, rtz);
+
+ TEST_FP_INT_OP_H(12, fcvt.wu.h, 0x10, 0, -3.0, rtz);
+ TEST_FP_INT_OP_H(13, fcvt.wu.h, 0x10, 0, -1.0, rtz);
+ TEST_FP_INT_OP_H(14, fcvt.wu.h, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_H(15, fcvt.wu.h, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_H(16, fcvt.wu.h, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_H(17, fcvt.wu.h, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_H(18, fcvt.wu.h, 0x10, 0, 0h:e803, rtz);
+ TEST_FP_INT_OP_H(19, fcvt.wu.h, 0x00, 2054, 0h:6803, rtz);
+
+#if __riscv_xlen >= 64
+ TEST_FP_INT_OP_H(22, fcvt.l.h, 0x01, -1, -1.1, rtz);
+ TEST_FP_INT_OP_H(23, fcvt.l.h, 0x00, -1, -1.0, rtz);
+ TEST_FP_INT_OP_H(24, fcvt.l.h, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_H(25, fcvt.l.h, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_H(26, fcvt.l.h, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_H(27, fcvt.l.h, 0x01, 1, 1.1, rtz);
+
+ TEST_FP_INT_OP_H(32, fcvt.lu.h, 0x10, 0, -3.0, rtz);
+ TEST_FP_INT_OP_H(33, fcvt.lu.h, 0x10, 0, -1.0, rtz);
+ TEST_FP_INT_OP_H(34, fcvt.lu.h, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_H(35, fcvt.lu.h, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_H(36, fcvt.lu.h, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_H(37, fcvt.lu.h, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_H(38, fcvt.lu.h, 0x10, 0, 0h:e483, rtz);
+#endif
+
+ # test negative NaN, negative infinity conversion
+ TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.h x1, f1)
+ TEST_CASE( 43, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.h x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE( 44, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.h x1, f1)
+ TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.h x1, f1)
+#endif
+
+ # test positive NaN, positive infinity conversion
+ TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.h x1, f1)
+ TEST_CASE( 53, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.h x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE( 54, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.h x1, f1)
+ TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.h x1, f1)
+#endif
+
+ # test NaN, infinity conversions to unsigned integer
+ TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.h x1, f1)
+ TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.h x1, f1)
+ TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.h x1, f1)
+ TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.h x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.h x1, f1)
+ TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.h x1, f1)
+ TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.h x1, f1)
+ TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.h x1, f1)
+#endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+# -NaN, NaN, -inf, +inf
+#tdat:
+#.word 0xffffffff
+#.word 0x7fffffff
+#.word 0xff800000
+#.word 0x7f800000
+
+tdat:
+.word 0xffffffff
+.word 0xffff7fff
+.word 0xfffffc00
+.word 0xffff7c00
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fdiv.S b/src/riscv-tests/isa/rv64uzfh/fdiv.S
new file mode 100644
index 0000000..894ebfc
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fdiv.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test f{div|sqrt}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_H(2, fdiv.h, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
+ TEST_FP_OP2_H(3, fdiv.h, 1,-0.9991093838555584, -1234, 1235.1 );
+ TEST_FP_OP2_H(4, fdiv.h, 0, 3.14159265, 3.14159265, 1.0 );
+
+ TEST_FP_OP1_H(5, fsqrt.h, 1, 1.7724538498928541, 3.14159265 );
+ TEST_FP_OP1_H(6, fsqrt.h, 0, 100, 10000 );
+
+ TEST_FP_OP1_H_DWORD_RESULT(7, fsqrt.h, 0x10, 0x00007e00, -1.0 );
+
+ TEST_FP_OP1_H(8, fsqrt.h, 1, 13.076696, 171.0);
+
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fmadd.S b/src/riscv-tests/isa/rv64uzfh/fmadd.S
new file mode 100644
index 0000000..2b49763
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fmadd.S
@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f[n]m{add|sub}.h and f[n]m{add|sub}.h instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP3_H( 2, fmadd.h, 0, 3.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_H( 3, fmadd.h, 1, 13.2, -1.0, -12.1, 1.1 );
+ TEST_FP_OP3_H( 4, fmadd.h, 0, -12.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_H( 5, fnmadd.h, 0, -3.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_H( 6, fnmadd.h, 1, -13.2, -1.0, -12.1, 1.1 );
+ TEST_FP_OP3_H( 7, fnmadd.h, 0, 12.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_H( 8, fmsub.h, 0, 1.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_H( 9, fmsub.h, 1, 11, -1.0, -12.1, 1.1 );
+ TEST_FP_OP3_H(10, fmsub.h, 0, -8.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_H(11, fnmsub.h, 0, -1.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_H(12, fnmsub.h, 1, -11, -1.0, -12.1, 1.1 );
+ TEST_FP_OP3_H(13, fnmsub.h, 0, 8.0, 2.0, -5.0, -2.0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/fmin.S b/src/riscv-tests/isa/rv64uzfh/fmin.S
new file mode 100644
index 0000000..3feec99
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/fmin.S
@@ -0,0 +1,54 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test f{min|max}.h instructinos.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_H( 2, fmin.h, 0, 1.0, 2.5, 1.0 );
+ TEST_FP_OP2_H( 3, fmin.h, 0, -1235.1, -1235.1, 1.1 );
+ TEST_FP_OP2_H( 4, fmin.h, 0, -1235.1, 1.1, -1235.1 );
+ TEST_FP_OP2_H( 5, fmin.h, 0, -1235.1, NaN, -1235.1 );
+ TEST_FP_OP2_H( 6, fmin.h, 0, 0.00000001, 3.14159265, 0.00000001 );
+ TEST_FP_OP2_H( 7, fmin.h, 0, -2.0, -1.0, -2.0 );
+
+ TEST_FP_OP2_H(12, fmax.h, 0, 2.5, 2.5, 1.0 );
+ TEST_FP_OP2_H(13, fmax.h, 0, 1.1, -1235.1, 1.1 );
+ TEST_FP_OP2_H(14, fmax.h, 0, 1.1, 1.1, -1235.1 );
+ TEST_FP_OP2_H(15, fmax.h, 0, -1235.1, NaN, -1235.1 );
+ TEST_FP_OP2_H(16, fmax.h, 0, 3.14159265, 3.14159265, 0.00000001 );
+ TEST_FP_OP2_H(17, fmax.h, 0, -1.0, -1.0, -2.0 );
+
+ # FMIN(hNaN, x) = x
+ TEST_FP_OP2_H(20, fmax.h, 0x10, 1.0, sNaNh, 1.0);
+ # FMIN(hNaN, hNaN) = canonical NaN
+ TEST_FP_OP2_H(21, fmax.h, 0x00, qNaNh, NaN, NaN);
+
+ # -0.0 < +0.0
+ TEST_FP_OP2_H(30, fmin.h, 0, -0.0, -0.0, 0.0 );
+ TEST_FP_OP2_H(31, fmin.h, 0, -0.0, 0.0, -0.0 );
+ TEST_FP_OP2_H(32, fmax.h, 0, 0.0, -0.0, 0.0 );
+ TEST_FP_OP2_H(33, fmax.h, 0, 0.0, 0.0, -0.0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/ldst.S b/src/riscv-tests/isa/rv64uzfh/ldst.S
new file mode 100644
index 0000000..ff1cdab
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a0, 0xcafe1000deadbeef, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); ld a0, 16(a1))
+ TEST_CASE(3, a0, 0x1337d00dabad0001, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); ld a0, 24(a1))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+.word 0xbf800001
+.word 0x40001000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/move.S b/src/riscv-tests/isa/rv64uzfh/move.S
new file mode 100644
index 0000000..20021df
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/move.S
@@ -0,0 +1,58 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# move.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that the fmv.h.x, fmv.x.h, and fsgnj[x|n].d instructions
+# and the fcsr work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0)
+ TEST_CASE(3, a0, 0x34, frsr a0)
+ TEST_CASE(4, a0, 0x14, frflags a0)
+ TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2)
+ TEST_CASE(6, a0, 0x54, frsr a0)
+ TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4)
+ TEST_CASE(8, a0, 0x50, frsr a0)
+
+#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \
+ TEST_CASE(n, a0, 0x1234 | (-(new_sign) << 15), \
+ li a1, ((rs1_sign) << 15) | 0x1234; \
+ li a2, -(rs2_sign); \
+ fmv.h.x f1, a1; \
+ fmv.h.x f2, a2; \
+ insn f0, f1, f2; \
+ fmv.x.h a0, f0)
+
+ TEST_FSGNJS(10, fsgnj.h, 0, 0, 0)
+ TEST_FSGNJS(11, fsgnj.h, 1, 0, 1)
+ TEST_FSGNJS(12, fsgnj.h, 0, 1, 0)
+ TEST_FSGNJS(13, fsgnj.h, 1, 1, 1)
+
+ TEST_FSGNJS(20, fsgnjn.h, 1, 0, 0)
+ TEST_FSGNJS(21, fsgnjn.h, 0, 0, 1)
+ TEST_FSGNJS(22, fsgnjn.h, 1, 1, 0)
+ TEST_FSGNJS(23, fsgnjn.h, 0, 1, 1)
+
+ TEST_FSGNJS(30, fsgnjx.h, 0, 0, 0)
+ TEST_FSGNJS(31, fsgnjx.h, 1, 0, 1)
+ TEST_FSGNJS(32, fsgnjx.h, 1, 1, 0)
+ TEST_FSGNJS(33, fsgnjx.h, 0, 1, 1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/src/riscv-tests/isa/rv64uzfh/recoding.S b/src/riscv-tests/isa/rv64uzfh/recoding.S
new file mode 100644
index 0000000..802be66
--- /dev/null
+++ b/src/riscv-tests/isa/rv64uzfh/recoding.S
@@ -0,0 +1,46 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# recoding.S
+#-----------------------------------------------------------------------------
+#
+# Test corner cases of John Hauser's microarchitectural recoding scheme.
+# There are twice as many recoded values as IEEE-754 values; some of these
+# extras are redundant (e.g. Inf) and others are illegal (subnormals with
+# too many bits set).
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ # Make sure infinities with different mantissas compare as equal.
+ flw f0, minf, a0
+ flw f1, three, a0
+ fmul.s f1, f1, f0
+ TEST_CASE( 2, a0, 1, feq.s a0, f0, f1)
+ TEST_CASE( 3, a0, 1, fle.s a0, f0, f1)
+ TEST_CASE( 4, a0, 0, flt.s a0, f0, f1)
+
+ # Likewise, but for zeroes.
+ fcvt.s.w f0, x0
+ li a0, 1
+ fcvt.s.w f1, a0
+ fmul.s f1, f1, f0
+ TEST_CASE(5, a0, 1, feq.s a0, f0, f1)
+ TEST_CASE(6, a0, 1, fle.s a0, f0, f1)
+ TEST_CASE(7, a0, 0, flt.s a0, f0, f1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+minf: .float -Inf
+three: .float 3.0
+
+RVTEST_DATA_END
diff --git a/src/riscv-ubuntu/README.md b/src/riscv-ubuntu/README.md
new file mode 100644
index 0000000..a46bb3c
--- /dev/null
+++ b/src/riscv-ubuntu/README.md
@@ -0,0 +1,206 @@
+---
+title: Linux x86-ubuntu image
+tags:
+ - riscv
+ - fullsystem
+layout: default
+permalink: resources/riscv-ubuntu
+shortdoc: >
+ Resources to build a generic riscv-ubuntu disk image.
+author: ["Hoa Nguyen"]
+---
+
+This document provides instructions to create the "riscv-ubuntu" image and
+points to the gem5 component that would work with the disk image. The
+riscv-ubuntu disk image is based on Ubuntu's preinstalled server image for
+RISC-V SiFive HiFive Unmatched available at
+(https://cdimage.ubuntu.com/releases/20.04.3/release/).
+The `.bashrc` file would be modified in such a way that it executes
+a script passed from the gem5 configuration files (using the `m5 readfile`
+instruction).
+
+We assume the following directory structure while following the instructions in this README file:
+
+```
+riscv-ubuntu/
+ |___ gem5/ # gem5 source code (to be cloned here)
+ |
+ |___ riscv-gnu-toolchain/
+ |
+ |___ qemu/
+ |
+ |___ disk-image/
+ | |___ shared/ # Auxiliary files needed for disk creation
+ | |___ riscv-ubuntu/
+ | |___ exit.sh # Exits the simulated guest upon booting
+ |
+ |___ ubuntu.img # The disk image
+ |
+ |___ README.md # This README file
+```
+
+# Installing the RISCV toolchain and QEMU
+
+```sh
+# Install QEMU dependencies
+sudo apt-get install ninja-build
+
+cd riscv-ubuntu/
+
+# QEMU
+git clone https://github.com/qemu/qemu
+cd qemu
+git checkout 0021c4765a6b83e5b09409b75d50c6caaa6971b9
+./configure --target-list=riscv64-softmmu
+make -j $(nproc)
+make install
+
+cd ..
+
+# RISCV toolchain
+git clone https://github.com/riscv-collab/riscv-gnu-toolchain --recursive
+cd riscv-gnu-toolchain
+git checkout 1a36b5dc44d71ab6a583db5f4f0062c2a4ad963b
+# --prefix parameter specifying the installation location
+./configure --prefix=/opt/riscv
+make linux -j $(nproc)
+
+cd ..
+```
+
+# Downloading the Preinstalled Disk Image
+
+There are more versions of Ubuntu that are supported for RISCV, they
+are available at (https://wiki.ubuntu.com/RISC-V).
+In the following command, we will use the Ubuntu 20.04.3 disk image.
+
+```sh
+# downloading the disk image
+wget https://cdimage.ubuntu.com/releases/20.04.3/release/ubuntu-20.04.3-preinstalled-server-riscv64+unmatched.img.xz
+# unpacking/decompressing the disk image
+xz -dk ubuntu-20.04.3-preinstalled-server-riscv64+unmatched.img.xz
+# renaming the disk image
+mv ubuntu-20.04.3-preinstalled-server-riscv64+unmatched.img ubuntu.img
+# adding 10GB to the disk
+qemu-img resize -f raw ubuntu.img +10G
+```
+
+# Installing Ubuntu Packages Containing Necessary Files for Booting the Disk Image with QEMU
+
+According to (https://wiki.ubuntu.com/RISC-V),
+
+> Prerequisites:
+>
+> apt install qemu-system-misc opensbi u-boot-qemu qemu-utils
+>
+> Hirsute's version of u-boot-qemu is required at the moment to boot hirsute images.
+
+To use Hirsute's version of u-boot-qemu, we will download the package from here,
+(https://packages.ubuntu.com/hirsute/u-boot-qemu). The following command will
+download and install the package.
+
+```sh
+wget http://mirrors.kernel.org/ubuntu/pool/main/u/u-boot/u-boot-qemu_2021.01+dfsg-3ubuntu9_all.deb
+dpkg -i u-boot-qemu_2021.01+dfsg-3ubuntu9_all.deb
+apt-get install -f
+```
+
+The following command will install the rest of the dependencies,
+```sh
+apt install qemu-system-misc opensbi qemu-utils
+```
+
+# Download gem5 and Compiling m5
+
+```sh
+# Within the `src/riscv-ubuntu` directory.
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5/util/m5
+scons build/riscv/out/m5
+cd ../../..
+```
+
+**Note**: the default cross-compiler is `riscv64-unknown-linux-gnu-`.
+To change the cross-compiler, you can set the cross-compiler using the scons
+sticky variable `riscv.CROSS_COMPILE`. For example,
+```sh
+scons riscv.CROSS_COMPILE=riscv64-linux-gnu- build/riscv/out/m5
+```
+
+# Booting the Disk Image with QEMU
+
+The following qemu command will boot the system using the disk image and the
+bootloader downloaded earlier.
+```sh
+./qemu/build/qemu-system-riscv64 -machine virt -nographic \
+ -m 16384 -smp 8 \
+ -bios /usr/lib/riscv64-linux-gnu/opensbi/generic/fw_jump.elf \
+ -kernel /usr/lib/u-boot/qemu-riscv64_smode/uboot.elf \
+ -device virtio-net-device,netdev=eth0 \
+ -netdev user,id=eth0,hostfwd=tcp::5555-:22 \
+ -drive file=ubuntu.img,format=raw,if=virtio
+```
+**Note:** the above command will forward the guest's port 22 to the host's
+port 5555. This is done so that we can transfer and install benchmarks
+to the guest system from the host via SSH (and using `scp`).
+
+On the first boot, the guest OS will ask to input username and password.
+The default username and password is,
+```
+Username: ubuntu
+Password: ubuntu
+```
+
+After changing the password and login to the guest OS, you can stop cloud-init
+and launch the SSH server,
+
+```sh
+sudo touch /etc/cloud/cloud-init.disabled # stop cloud-init
+/etc/init.d/ssh start # start the SSH server
+sudo apt-get update
+sudo apt-get upgrade
+```
+
+
+
+**Notes:** it is strongly recommended to use key-based authentication to
+SSH to the guest.
+
+# Install the Benchmark
+
+From host, copy the auto log-in script and the benchmark using `scp`,
+```sh
+cd riscv-ubuntu/
+scp -P 5555 gem5/util/m5/build/riscv/out/m5 ubuntu@localhost:/home/ubuntu/
+scp -P 5555 disk-image/shared/serial-getty@.service ubuntu@localhost:/home/ubuntu/
+scp -P 5555 disk-image/riscv-ubuntu/gem5_init.sh ubuntu@localhost:/home/ubuntu/
+```
+
+Connecting to the guest,
+```sh
+ssh -p 5555 ubuntu@localhost
+```
+
+In the guest,
+```sh
+sudo -i
+# input password
+
+mv /home/ubuntu/serial-getty@.service /lib/systemd/system/
+
+mv /home/ubuntu/m5 /sbin
+ln -s /sbin/m5 /sbin/gem5
+
+mv /home/ubuntu/gem5_init.sh /root/
+chmod +x /root/gem5_init.sh
+echo "/root/gem5_init.sh" >> /root/.bashrc
+```
+
+# Pre-built disk image
+
+A pre-build, gzipped, disk image is available at <http://dist.gem5.org/dist/develop/images/riscv/ubuntu-20-04/riscv-ubuntu.img.gz>. **Note**: The password set for the `ubuntu` user is `helloworld`.
+
+# Using the Disk Image
+This disk image is used in the following gem5 example RISCV config files, found within the gem5 repository:
+* `gem5/configs/example/gem5_library/riscv-fs.py`, which simulates a full system running with RISCV ISA.
+* `gem5/configs/example/gem5_library/riscv-ubuntu-run.py`, which simulates a full system with RISCV based Ubuntu 20.04 disk-image. Upon successful start-up, a `m5_exit instruction encountered` is encountered. The simulation ends then.
diff --git a/src/riscv-ubuntu/disk-image/riscv-ubuntu/gem5_init.sh b/src/riscv-ubuntu/disk-image/riscv-ubuntu/gem5_init.sh
new file mode 100755
index 0000000..bbdbbfb
--- /dev/null
+++ b/src/riscv-ubuntu/disk-image/riscv-ubuntu/gem5_init.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+
+# Copyright (c) 2021 The University of Texas at Austin.
+# SPDX-License-Identifier: BSD 3-Clause
+
+echo "Starting gem5 init... reading run script file."
+if ! m5 readfile > /tmp/script; then
+ echo "Failed to run m5 readfile, exiting!"
+ rm -f /tmp/script
+ if ! m5 exit; then
+ # Useful for booting the disk image in (e.g.,) qemu for debugging
+ echo "m5 exit failed, dropping to shell."
+ /bin/sh
+ fi
+else
+ echo "Running m5 script from /tmp/script"
+ chmod 755 /tmp/script
+ /tmp/script
+ echo "Done running script, exiting."
+ rm -f /tmp/script
+ m5 exit
+fi
diff --git a/src/boot-exit/disk-image/shared/serial-getty@.service b/src/riscv-ubuntu/disk-image/shared/serial-getty@.service
similarity index 100%
copy from src/boot-exit/disk-image/shared/serial-getty@.service
copy to src/riscv-ubuntu/disk-image/shared/serial-getty@.service
diff --git a/src/spec-2006/README.md b/src/spec-2006/README.md
index a6ca257..2444dd8 100644
--- a/src/spec-2006/README.md
+++ b/src/spec-2006/README.md
@@ -11,8 +11,8 @@
---
This document aims to provide instructions to create a gem5-compatible disk
-image containing the SPEC 2006 benchmark suite and also to provide necessary
-configuration files.
+image containing the SPEC 2006 benchmark suite. It also demonstrates how to
+simulate the SPEC CPU2006 benchmarks using an example configuration script.
## Building the Disk Image
Creating a disk-image for SPEC 2006 requires the benchmark suite ISO file.
@@ -39,10 +39,6 @@
| |___ spec-2006.json # the Packer script
| |___ CPU2006v1.0.1.iso # SPEC 2006 ISO (add here)
|
- |___ configs
- | |___ system
- | |___ run_spec.py # gem5 config file
- |
|___ vmlinux-4.19.83 # download link below
|
|___ README.md
@@ -66,94 +62,76 @@
./build.sh # the script downloading packer binary and building the disk image
```
-## gem5 Configuration Scripts
-gem5 scripts which configure the system and run the simulation are available
-in `configs/`.
-The main script `run_spec.py` expects following arguments:
+## Simulating SPEC CPU2006 using an example script
-`usage: run_spec.py [-h] [-l] [-z] kernel disk cpu mem_sys benchmark size`
-
-`-h`: show this help message and exit.
-
-`-l`, `--no-copy-logs`: optional, to not copy SPEC run logs to the host system,
-logs are copied by default, and are available in the result folder.
-
-`-z`, `--allow-listeners`: optional, to turn on GDB listening ports, the ports
-are off by default.
-
-`kernel`: required, a positional argument specifying the path to the Linux
-kernel. We have tested using version 4.19.83, which can be downloaded from
-<http://dist.gem5.org/dist/v21-1/kernels/x86/static/vmlinux-4.19.83>. Info on
-building Linux kernels for gem5 can be found in `src/linux-kernel`
-
-`disk`: required, a positional argument specifying the path to the disk image
-containing SPEC 2006 benchmark suite.
-
-`cpu`: required, a positional argument specifying the name of either a
-detailed CPU model or KVM CPU model.
-
-The available CPU models are,
-
-| cpu | Corresponding CPU model in gem5 |
-| ---------| ------------------------------- |
-| `kvm` | |
-| `o3` | DerivO3CPU |
-| `atomic` | AtomicSimpleCPU |
-| `timing` | TimingSimpleCPU |
-
-`mem_sys`: required, a positional argument specifying the memory system.
-The available memory systems are,
-
-| mem\_sys | Notes |
-| --------------------- | ---------------------- |
-| `classic` | classic memory system |
-| `MI_example` | Ruby memory system |
-| `MESI_Two_Level` | Ruby memory system |
-| `MOESI_CMP_directory` | Ruby memory system |
-
-`benchmark`: required, a positional argument specifying the name of the SPEC
-2006 workload to run. The available benchmarks are,
-
-* 401.bzip2
-* 403.gcc
-* 410.bwaves
-* 416.gamess
-* 429.mcf
-* 433.milc
-* 434.zeusmp
-* 435.gromacs
-* 436.cactusADM
-* 437.leslie3d
-* 444.namd
-* 445.gobmk
-* 453.povray
-* 454.calculix
-* 456.hmmer
-* 458.sjeng
-* 459.GemsFDTD
-* 462.libquantum
-* 464.h264ref
-* 465.tonto
-* 470.lbm
-* 471.omnetpp
-* 473.astar
-* 481.wrf
-* 482.sphinx3
-* 998.specrand
-* 999.specrand
-
-`size`: required, a positional argument specifying the input data size. Valid
-values are `test`, `train`, and `ref`.
-
-As a minimum the following parameters must be specified:
+An example script with a pre-configured system is available in the following directory within the gem5 repository:
```
-<gem5 X86 binary> --outdir <output directory> configs/run_spec.py <kernel> <disk> <cpu> <mem_sys> <benchmark> <size>
+gem5/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
```
-**Note**: `--outdir` is a required argument when running the gem5 binary with SPEC 2006.
-The path to the output directory must be an absoblute path.
+The example script specifies a system with the following parameters:
+* A `SimpleSwitchableProcessor` (`KVM` for startup and `TIMING` for ROI execution). There are 2 CPU cores, each clocked at 3 GHz.
+* 2 Level `MESI_Two_Level` cache with 32 kB L1I and L1D size, and, 256 kB L2 size. The L1 cache(s) has associativity of 8, and, the L2 cache has associativity 16. There are 2 L2 cache banks.
+* The system has 3 GB `SingleChannelDDR4_2400` memory.
+* The script uses `x86-linux-kernel-4.19.83` and the disk image created from following the instructions in this `README.md`.
+* The user inputs the path to the built disk image, along with the root partition.
+* The script then uses `CustomResource` class to use the `spec-2006` disk-image.
+
+The example script must be run with the `X86_MESI_Two_Level` binary. To build:
+
+```sh
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+scons build/X86/gem5.opt -j<proc>
+```
+Once compiled, you may use the example configuration file to run the SPEC CPU2006 benchmark programs using the following command:
+
+```sh
+# In the gem5 directory
+build/X86/gem5.opt \
+configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py \
+--image <path_to_built_spec-2006_disk_image> \
+--partition <root_partition_to_mount> \
+--benchmark <benchmark_program> \
+--size <workload_size>
+```
+
+Description of the four arguments, provided in the above command are:
+* **--image** refers to the full path of the the SPEC CPU2006 disk-image, built using the instructions specified above.
+* **--partition** refers to the root partition of the disk-image to mount. If the disk has no partitions, then pass `--partition ""`. Otherwise, pass an integer specifying the partition number. Set `--partition 1` if the above instructions to build the disk-image are followed.
+* **--benchmark**, which refers to one of 26 benchmark programs, provided in the SPEC CPU2006 Benchmark Suite. For more information on the workloads can be found at <https://www.spec.org/cpu2006/>. The list of benchmark programs include:
+ * 401.bzip2
+ * 403.gcc
+ * 410.bwaves
+ * 416.gamess
+ * 429.mcf
+ * 433.milc
+ * 434.zeusmp
+ * 435.gromacs
+ * 436.cactusADM
+ * 437.leslie3d
+ * 444.namd
+ * 445.gobmk
+ * 453.povray
+ * 454.calculix
+ * 456.hmmer
+ * 458.sjeng
+ * 459.GemsFDTD
+ * 462.libquantum
+ * 464.h264ref
+ * 465.tonto
+ * 470.lbm
+ * 471.omnetpp
+ * 473.astar
+ * 481.wrf
+ * 482.sphinx3
+ * 998.specrand
+ * 999.specrand
+* **--size**, which refers to the workload size to simulate. Valid choices for `--size` are `test`, `train` and `ref`.
+
+The output directory, where the simulation statistics will be redirected to, will have a new folder named `speclogs_<Day><Month><Date><Hour><Minute><Second>`. The time is of execution is appended to avoid conflicts while coping the files. The output files, generated on the disk-image in the folder `speclogs` will be copied to this aforementioned directory.
## Working Status
Status of these benchmarks runs with respect to gem5-20, linux kernel version
4.19.83 and gcc version 7.5.0 can be found
diff --git a/src/spec-2006/configs/run_spec.py b/src/spec-2006/configs/run_spec.py
deleted file mode 100644
index 6d17bd9..0000000
--- a/src/spec-2006/configs/run_spec.py
+++ /dev/null
@@ -1,301 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2020 The Regents of the University of California.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power, Ayaz Akram, Hoa Nguyen
-
-""" Script to run a SPEC benchmark in full system mode with gem5.
-
- Inputs:
- * This script expects the following as arguments:
- ** kernel:
- This is a positional argument specifying the path to
- vmlinux.
- ** disk:
- This is a positional argument specifying the path to the
- disk image containing the installed SPEC benchmarks.
- ** cpu:
- This is a positional argument specifying the name of the
- detailed CPU model. The names of the available CPU models
- are available in the getDetailedCPUModel(cpu_name) function.
- The function should be modified to add new CPU models.
- Currently, the available CPU models are:
- - kvm: this is not a detailed CPU model, ideal for testing.
- - o3: DerivO3CPU.
- - atomic: AtomicSimpleCPU.
- - timing: TimingSimpleCPU.
- ** benchmark:
- This is a positional argument specifying the name of the
- SPEC benchmark to run. Most SPEC benchmarks are available.
- Please follow this link to check the availability of the
- benchmarks. The working benchmark matrix is near the end
- of the page:
- (SPEC 2006) https://gem5art.readthedocs.io/en/latest/tutorials/spec2006-tutorial.html#appendix-i-working-spec-2006-benchmarks-x-cpu-model-table
- (SPEC 2017) https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html#appendix-i-working-spec-2017-benchmarks-x-cpu-model-table
- ** size:
- This is a positional argument specifying the size of the
- benchmark. The available sizes are: ref, test, train.
- ** --no-copy-logs:
- This is an optional argument specifying the reports of
- the benchmark run is not copied to the output folder.
- The reports are copied by default.
- ** --allow-listeners:
- This is an optional argument specifying gem5 to open GDB
- listening ports. Usually, the ports are opened for debugging
- purposes.
- By default, the ports are off.
-"""
-import os
-
-import m5
-import m5.ticks
-from m5.objects import *
-
-import argparse
-
-from system import *
-
-def writeBenchScript(dir, benchmark_name, size, output_path):
- """
- This method creates a script in dir which will be eventually
- passed to the simulated system (to run a specific benchmark
- at bootup).
- """
- input_file_name = '{}/run_{}_{}'.format(dir, benchmark_name, size)
- with open(input_file_name, "w") as f:
- f.write('{} {} {}'.format(benchmark_name, size, output_path))
- return input_file_name
-
-def parse_arguments():
- parser = argparse.ArgumentParser(description=
- "gem5 config file to run SPEC benchmarks")
- parser.add_argument("kernel", type = str, help = "Path to vmlinux")
- parser.add_argument("disk", type = str,
- help = "Path to the disk image containing SPEC benchmarks")
- parser.add_argument("cpu", type = str, help = "Name of the detailed CPU")
- parser.add_argument("mem_sys", type = str, help = "Name of the memory system")
- parser.add_argument("benchmark", type = str,
- help = "Name of the SPEC benchmark")
- parser.add_argument("size", type = str,
- help = "Available sizes: test, train, ref")
- parser.add_argument("-l", "--no-copy-logs", default = False,
- action = "store_true",
- help = "Not to copy SPEC run logs to the host system;"
- "Logs are copied by default")
- parser.add_argument("-z", "--allow-listeners", default = False,
- action = "store_true",
- help = "Turn on ports;"
- "The ports are off by default")
- return parser.parse_args()
-
-def getDetailedCPUModel(cpu_name):
- '''
- Return the CPU model corresponding to the cpu_name.
- '''
- available_models = {"kvm": X86KvmCPU,
- "o3": DerivO3CPU,
- "atomic": AtomicSimpleCPU,
- "timing": TimingSimpleCPU
- }
- try:
- available_models["FlexCPU"] = FlexCPU
- except NameError:
- # FlexCPU is not defined
- pass
- # https://docs.python.org/3/library/stdtypes.html#dict.get
- # dict.get() returns None if the key does not exist
- return available_models.get(cpu_name)
-
-def getBenchmarkName(benchmark_name):
- if benchmark_name.endswith("(base)"):
- benchmark_name = benchmark_name[:-6]
- return benchmark_name
-
-def create_system(linux_kernel_path, disk_image_path, detailed_cpu_model, memory_system):
- # create the system we are going to simulate
- ruby_protocols = [ "MI_example", "MESI_Two_Level", "MOESI_CMP_directory"]
- if memory_system == 'classic':
- system = MySystem(kernel = linux_kernel_path,
- disk = disk_image_path,
- num_cpus = 1, # run the benchmark in a single thread
- no_kvm = False,
- TimingCPUModel = detailed_cpu_model)
- elif memory_system in ruby_protocols:
- system = MyRubySystem(kernel = linux_kernel_path,
- disk = disk_image_path,
- num_cpus = 1, # run the benchmark in a single thread
- mem_sys = memory_system,
- no_kvm = False,
- TimingCPUModel = detailed_cpu_model)
- else:
- m5.fatal("Bad option for mem_sys, should be "
- "{}, or 'classic'".format(', '.join(ruby_protocols)))
-
- # For workitems to work correctly
- # This will cause the simulator to exit simulation when the first work
- # item is reached and when the first work item is finished.
- system.work_begin_exit_count = 1
- system.work_end_exit_count = 1
-
- # set up the root SimObject and start the simulation
- root = Root(full_system = True, system = system)
-
- if system.getHostParallel():
- # Required for running kvm on multiple host cores.
- # Uses gem5's parallel event queue feature
- # Note: The simulator is quite picky about this number!
- root.sim_quantum = int(1e9) # 1 ms
-
- return root, system
-
-
-def boot_linux():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Booting Linux")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while booting linux: {}".format(exit_cause))
- exit(1)
- print("Done booting Linux")
- return success, exit_cause
-
-def run_spec_benchmark():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Start running benchmark")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while running benchmark: {}".format(exit_cause))
- exit(1)
- print("Benchmark done")
- return success, exit_cause
-
-def copy_spec_logs():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Copying SPEC logs")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while copying SPEC log files: {}".format(exit_cause))
- exit(1)
- print("Copying done")
- return success, exit_cause
-
-if __name__ == "__m5_main__":
- args = parse_arguments()
-
- cpu_name = args.cpu
- mem_sys = args.mem_sys
- benchmark_name = getBenchmarkName(args.benchmark)
- benchmark_size = args.size
- linux_kernel_path = args.kernel
- disk_image_path = args.disk
- no_copy_logs = args.no_copy_logs
- allow_listeners = args.allow_listeners
-
- if not no_copy_logs and not os.path.isabs(m5.options.outdir):
- print("Please specify the --outdir (output directory) of gem5"
- " in the form of an absolute path")
- print("An example: build/X86/gem5.opt --outdir /home/user/m5out/"
- " configs-spec-tests/run_spec ...")
- exit(1)
-
- output_dir = os.path.join(m5.options.outdir, "speclogs")
-
- # Get the DetailedCPU class from its name
- detailed_cpu = getDetailedCPUModel(cpu_name)
- if detailed_cpu == None:
- print("'{}' is not define in the config script.".format(cpu_name))
- print("Change getDeatiledCPUModel() in run_spec.py "
- "to add more CPU Models.")
- exit(1)
-
- if not benchmark_size in ["ref", "train", "test"]:
- print("Benchmark size must be one of the following: ref, train, test")
- exit(1)
-
- root, system = create_system(linux_kernel_path, disk_image_path,
- detailed_cpu, mem_sys)
-
- # Create and pass a script to the simulated system to run the required
- # benchmark
- system.readfile = writeBenchScript(m5.options.outdir, benchmark_name,
- benchmark_size, output_dir)
-
- # needed for long running jobs
- if not allow_listeners:
- m5.disableAllListeners()
-
- # instantiate all of the objects we've created above
- m5.instantiate()
-
- # booting linux
- success, exit_cause = boot_linux()
-
- # reset stats
- print("Reset stats")
- m5.stats.reset()
-
- # switch from KVM to detailed CPU
- if not cpu_name == "kvm":
- print("Switching to detailed CPU")
- system.switchCpus(system.cpu, system.detailed_cpu)
- print("Switching done")
-
- # running benchmark
- print("Benchmark: {}; Size: {}".format(benchmark_name, benchmark_size))
- success, exit_cause = run_spec_benchmark()
-
- # output the stats after the benchmark is complete
- print("Output stats")
- m5.stats.dump()
-
- if not no_copy_logs:
- # create the output folder
- if not os.path.exists(output_dir):
- os.makedirs(output_dir)
-
- # switch from detailed CPU to KVM
- if not cpu_name == "kvm":
- print("Switching to KVM")
- system.switchCpus(system.detailed_cpu, system.cpu)
- print("Switching done")
-
- # copying logs
- success, exit_cause = copy_spec_logs()
diff --git a/src/spec-2006/configs/system/MESI_Two_Level.py b/src/spec-2006/configs/system/MESI_Two_Level.py
deleted file mode 100644
index 17df7c0..0000000
--- a/src/spec-2006/configs/system/MESI_Two_Level.py
+++ /dev/null
@@ -1,340 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2020 The Regents of the University of California.
-# All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MESI TWO Level protocol
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MESITwoLevelCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
- fatal("This system assumes MESI_Two_Level!")
-
- super(MESITwoLevelCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MESI_Two_Level example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU core.
- # The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in range(self._numL2Caches)] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False)
- self.l2_select_num_bits = int(math.log(num_l2Caches , 2))
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.enable_prefetch = False
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.out_port = ruby_system.network.in_port
-
- self.optionalQueue = MessageBuffer()
-
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getBlockSizeBits(system,
- num_l2Caches))
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
- self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2006/configs/system/MI_example_caches.py b/src/spec-2006/configs/system/MI_example_caches.py
deleted file mode 100644
index 0d028df..0000000
--- a/src/spec-2006/configs/system/MI_example_caches.py
+++ /dev/null
@@ -1,279 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2015 Jason Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Power
-
-""" This file creates a set of Ruby caches, the Ruby network, and a simple
-point-to-point topology.
-See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
-You can change simple_ruby to import from this file instead of from msi_caches
-to use the MI_example protocol instead of MSI.
-
-IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
- also needs to be updated. For now, email Jason <jason@lowepower.com>
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MIExampleSystem(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MI_example':
- fatal("This system assumes MI_example!")
-
- super(MIExampleSystem, self).__init__()
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MI example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # Create one controller for each L1 cache (and the cache mem obj.)
- # Create a single directory controller (Really the memory cntrl)
- self.controllers = \
- [L1Cache(system, self, cpu) for cpu in cpus] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU. In many systems this is more
- # complicated since you have to create sequencers for DMA controllers
- # and other controllers, too.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].cacheMemory,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[0:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu):
- """CPUs are needed to grab the clock domain and system is needed for
- the cache block size.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.cacheMemory = RubyCache(size = '16kB',
- assoc = 8,
- start_index_bit = self.getBlockSizeBits(system))
- self.clk_domain = cpu.clk_domain
- self.send_evictions = self.sendEvicts(cpu)
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromCache = MessageBuffer(ordered = True)
- self.requestFromCache.out_port = ruby_system.network.in_port
- self.responseFromCache = MessageBuffer(ordered = True)
- self.responseFromCache.out_port = ruby_system.network.in_port
- self.forwardToCache = MessageBuffer(ordered = True)
- self.forwardToCache.in_port = ruby_system.network.out_port
- self.responseToCache = MessageBuffer(ordered = True)
- self.responseToCache.in_port = ruby_system.network.out_port
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer(ordered = True)
- self.requestToDir.in_port = ruby_system.network.out_port
- self.dmaRequestToDir = MessageBuffer(ordered = True)
- self.dmaRequestToDir.in_port = ruby_system.network.out_port
-
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.dmaResponseFromDir = MessageBuffer(ordered = True)
- self.dmaResponseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2006/configs/system/MOESI_CMP_directory.py b/src/spec-2006/configs/system/MOESI_CMP_directory.py
deleted file mode 100644
index 15b215d..0000000
--- a/src/spec-2006/configs/system/MOESI_CMP_directory.py
+++ /dev/null
@@ -1,350 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2020 The Regents of the University of California.
-# All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MOESI CMP directory
-protocol.
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MOESICMPDirCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
- fatal("This system assumes MOESI_CMP_directory!")
-
- super(MOESICMPDirCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MOESI_CMP_directory example uses 3 virtual networks
- self.number_of_virtual_networks = 3
- self.network.number_of_virtual_networks = 3
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU core.
- # The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in range(self._numL2Caches)] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getL2StartIdx(system,
- num_l2Caches),
- dataAccessLatency = 20,
- tagAccessLatency = 20)
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getL2StartIdx(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.GlobalRequestFromL2Cache = MessageBuffer()
- self.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
-
- self.GlobalRequestToL2Cache = MessageBuffer()
- self.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.reqToDir = MessageBuffer()
- self.reqToDir.out_port = ruby_system.network.in_port
- self.respToDir = MessageBuffer()
- self.respToDir.out_port = ruby_system.network.in_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2006/configs/system/__init__.py b/src/spec-2006/configs/system/__init__.py
deleted file mode 100644
index 94e676f..0000000
--- a/src/spec-2006/configs/system/__init__.py
+++ /dev/null
@@ -1,31 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from .system import MySystem
-from .ruby_system import MyRubySystem
diff --git a/src/spec-2006/configs/system/caches.py b/src/spec-2006/configs/system/caches.py
deleted file mode 100644
index 3e786b7..0000000
--- a/src/spec-2006/configs/system/caches.py
+++ /dev/null
@@ -1,173 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-""" Caches with options for a simple gem5 configuration script
-
-This file contains L1 I/D and L2 caches to be used in the simple
-gem5 configuration script.
-"""
-
-import m5
-from m5.objects import Cache, L2XBar, StridePrefetcher
-
-# Some specific options for caches
-# For all options see src/mem/cache/BaseCache.py
-
-class PrefetchCache(Cache):
-
- def __init__(self, options = None):
- super(PrefetchCache, self).__init__()
- if not options or options.no_prefetchers:
- return
- self.prefetcher = StridePrefetcher()
-
-class L1Cache(PrefetchCache):
- """Simple L1 Cache with default values"""
-
- assoc = 8
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 16
- tgts_per_mshr = 20
- writeback_clean = True
-
- def __init__(self):
- super(L1Cache, self).__init__()
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU-side port
- This must be defined in a subclass"""
- raise NotImplementedError
-
-class L1ICache(L1Cache):
- """Simple L1 instruction cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1ICache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU icache port"""
- self.cpu_side = cpu.icache_port
-
-class L1DCache(L1Cache):
- """Simple L1 data cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1DCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU dcache port"""
- self.cpu_side = cpu.dcache_port
-
-class MMUCache(Cache):
- # Default parameters
- size = '8kB'
- assoc = 4
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(MMUCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect the CPU itb and dtb to the cache
- Note: This creates a new crossbar
- """
- self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
-class L2Cache(PrefetchCache):
- """Simple L2 Cache with default values"""
-
- # Default parameters
- size = '256kB'
- assoc = 16
- tag_latency = 10
- data_latency = 10
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(L2Cache, self).__init__()
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
-
-class L3Cache(Cache):
- """Simple L3 Cache bank with default values
- This assumes that the L3 is made up of multiple banks. This cannot
- be used as a standalone L3 cache.
- """
-
- # Default parameters
- assoc = 32
- tag_latency = 40
- data_latency = 40
- response_latency = 10
- mshrs = 256
- tgts_per_mshr = 12
- clusivity = 'mostly_excl'
-
- size = '4MB'
-
- def __init__(self):
- super(L3Cache, self).__init__()
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
-
diff --git a/src/spec-2006/configs/system/fs_tools.py b/src/spec-2006/configs/system/fs_tools.py
deleted file mode 100644
index 5e5e2df..0000000
--- a/src/spec-2006/configs/system/fs_tools.py
+++ /dev/null
@@ -1,39 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
-
-class CowDisk(IdeDisk):
-
- def __init__(self, filename):
- super(CowDisk, self).__init__()
- self.driveID = 'device0'
- self.image = CowDiskImage(child=RawDiskImage(read_only=True),
- read_only=False)
- self.image.child.image_file = filename
diff --git a/src/spec-2006/configs/system/ruby_system.py b/src/spec-2006/configs/system/ruby_system.py
deleted file mode 100755
index d1ddb07..0000000
--- a/src/spec-2006/configs/system/ruby_system.py
+++ /dev/null
@@ -1,244 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-
-
-class MyRubySystem(System):
-
- def __init__(self, kernel, disk, mem_sys, num_cpus, TimingCPUModel, no_kvm=False):
- super(MyRubySystem, self).__init__()
- self._no_kvm = no_kvm
-
- self._host_parallel = True
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '2.3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- self.initFS(num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus,TimingCPUModel)
-
- self.createMemoryControllersDDR4()
-
- # Create the cache hierarchy for the system.
- if mem_sys == 'MI_example':
- from .MI_example_caches import MIExampleSystem
- self.caches = MIExampleSystem()
- elif mem_sys == 'MESI_Two_Level':
- from .MESI_Two_Level import MESITwoLevelCache
- self.caches = MESITwoLevelCache()
- elif mem_sys == 'MOESI_CMP_directory':
- from .MOESI_CMP_directory import MOESICMPDirCache
- self.caches = MOESICMPDirCache()
- self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports],
- self.iobus)
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus, TimingCPUModel):
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.mem_mode = 'timing'
-
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.detailed_cpu = [TimingCPUModel(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
-
- self.createCPUThreads(self.detailed_cpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createMemoryControllersDDR4(self):
- self._createMemoryControllers(1, DDR4_2400_16x4)
-
- def _createMemoryControllers(self, num, cls):
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = self.mem_ranges[0]))
- for i in range(num)
- ]
-
- def _createKernelMemoryController(self, cls):
- return cls(range = self.mem_ranges[0],
- port = self.membus.mem_side_ports)
-
- def initFS(self, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # North Bridge
- self.iobus = IOXBar()
-
- # connect the io bus
- # Note: pass in a reference to where Ruby will connect to in the future
- # so the port isn't connected twice.
- self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/spec-2006/configs/system/system.py b/src/spec-2006/configs/system/system.py
deleted file mode 100644
index 35f0721..0000000
--- a/src/spec-2006/configs/system/system.py
+++ /dev/null
@@ -1,373 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2018 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-from .caches import *
-
-
-class MySystem(System):
-
- def __init__(self, kernel, disk, num_cpus, TimingCPUModel, no_kvm=False):
- super(MySystem, self).__init__()
- self._no_kvm = no_kvm
-
- self._host_parallel = True
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '2.3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- mem_size = '32GB'
- self.mem_ranges = [AddrRange('100MB'), # For kernel
- AddrRange(0xC0000000, size=0x100000), # For I/0
- AddrRange(Addr('4GB'), size = mem_size) # All data
- ]
-
- # Create the main memory bus
- # This connects to main memory
- self.membus = SystemXBar(width = 64) # 64-byte width
- self.membus.badaddr_responder = BadAddr()
- self.membus.default = Self.badaddr_responder.pio
-
- # Set up the system port for functional access from the simulator
- self.system_port = self.membus.cpu_side_ports
-
- self.initFS(self.membus, num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus, TimingCPUModel)
-
- # Create the cache heirarchy for the system.
- self.createCacheHierarchy()
-
- # Set up the interrupt controllers for the system (x86 specific)
- self.setupInterrupts()
-
- self.createMemoryControllersDDR4()
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus, TimingCPUModel):
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.mem_mode = 'timing'
-
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.detailed_cpu = [TimingCPUModel(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
-
- self.createCPUThreads(self.detailed_cpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createCacheHierarchy(self):
- # Create an L3 cache (with crossbar)
- self.l3bus = L2XBar(width = 64,
- snoop_filter = SnoopFilter(max_capacity='32MB'))
-
- for cpu in self.cpu:
- # Create a memory bus, a coherent crossbar, in this case
- cpu.l2bus = L2XBar()
-
- # Create an L1 instruction and data cache
- cpu.icache = L1ICache()
- cpu.dcache = L1DCache()
- cpu.mmucache = MMUCache()
-
- # Connect the instruction and data caches to the CPU
- cpu.icache.connectCPU(cpu)
- cpu.dcache.connectCPU(cpu)
- cpu.mmucache.connectCPU(cpu)
-
- # Hook the CPU ports up to the l2bus
- cpu.icache.connectBus(cpu.l2bus)
- cpu.dcache.connectBus(cpu.l2bus)
- cpu.mmucache.connectBus(cpu.l2bus)
-
- # Create an L2 cache and connect it to the l2bus
- cpu.l2cache = L2Cache()
- cpu.l2cache.connectCPUSideBus(cpu.l2bus)
-
- # Connect the L2 cache to the L3 bus
- cpu.l2cache.connectMemSideBus(self.l3bus)
-
- self.l3cache = L3Cache()
- self.l3cache.connectCPUSideBus(self.l3bus)
-
- # Connect the L3 cache to the membus
- self.l3cache.connectMemSideBus(self.membus)
-
- def setupInterrupts(self):
- for cpu in self.cpu:
- # create the interrupt controller CPU and connect to the membus
- cpu.createInterruptController()
-
- # For x86 only, connect interrupts to the memory
- # Note: these are directly connected to the memory bus and
- # not cached
- cpu.interrupts[0].pio = self.membus.mem_side_ports
- cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
- cpu.interrupts[0].int_responder = self.membus.mem_side_ports
-
- # Memory latency: Using the smaller number from [3]: 96ns
- def createMemoryControllersDDR4(self):
- self._createMemoryControllers(8, DDR4_2400_16x4)
-
- def _createMemoryControllers(self, num, cls):
- kernel_controller = self._createKernelMemoryController(cls)
-
- ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = ranges[i]), port = self.membus.mem_side_ports)
- for i in range(num)
- ] + [kernel_controller]
-
- def _createKernelMemoryController(self, cls):
- return MemCtrl(dram = cls(range = self.mem_ranges[0]), port = self.membus.mem_side_ports)
-
- def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
- from math import log
- bits = int(log(num, 2))
- if 2**bits != num:
- m5.fatal("Non-power of two number of memory controllers")
-
- intlv_bits = bits
- ranges = [
- AddrRange(start=rng.start,
- end=rng.end,
- intlvHighBit = intlv_low_bit + intlv_bits - 1,
- xorHighBit = xor_low_bit + intlv_bits - 1,
- intlvBits = intlv_bits,
- intlvMatch = i)
- for i in range(num)
- ]
-
- return ranges
-
- def initFS(self, membus, cpus):
- self.pc = Pc()
- self.workload = X86FsLinux()
- # Constants similar to x86_traits.hh
- IO_address_space_base = 0x8000000000000000
- pci_config_address_space_base = 0xc000000000000000
- interrupts_address_space_base = 0xa000000000000000
- APIC_range_size = 1 << 12
-
- # North Bridge
- self.iobus = IOXBar()
- self.bridge = Bridge(delay='50ns')
- self.bridge.mem_side_port = self.iobus.cpu_side_ports
- self.bridge.cpu_side_port = membus.mem_side_ports
- # Allow the bridge to pass through:
- # 1) kernel configured PCI device memory map address: address range
- # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
- # 2) the bridge to pass through the IO APIC (two pages, already
- # contained in 1),
- # 3) everything in the IO address range up to the local APIC, and
- # 4) then the entire PCI address space and beyond.
- self.bridge.ranges = \
- [
- AddrRange(0xC0000000, 0xFFFF0000),
- AddrRange(IO_address_space_base,
- interrupts_address_space_base - 1),
- AddrRange(pci_config_address_space_base,
- Addr.max)
- ]
-
- # Create a bridge from the IO bus to the memory bus to allow access
- # to the local APIC (two pages)
- self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
- self.apicbridge.mem_side_port = membus.cpu_side_ports
- self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
- interrupts_address_space_base +
- cpus * APIC_range_size
- - 1)]
-
- # connect the io bus
- self.pc.attachIO(self.iobus)
-
- # Add a tiny cache to the IO bus.
- # This cache is required for the classic memory model for coherence
- self.iocache = Cache(assoc=8,
- tag_latency = 50,
- data_latency = 50,
- response_latency = 50,
- mshrs = 20,
- size = '1kB',
- tgts_per_mshr = 12,
- addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.mem_side_ports
- self.iocache.mem_side = self.membus.cpu_side_ports
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
- # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which
- # force IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests
- # to this specific range can pass though bridge to iobus.
- entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
- size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
- range_type=2))
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- # Add the rest of memory. This is where all the actual data is
- entries.append(X86E820Entry(addr = self.mem_ranges[-1].start,
- size='%dB' % (self.mem_ranges[-1].size()),
- range_type=1))
-
- self.workload.e820_table.entries = entries
diff --git a/src/spec-2017/README.md b/src/spec-2017/README.md
index 604f5fc..68f1a75 100644
--- a/src/spec-2017/README.md
+++ b/src/spec-2017/README.md
@@ -11,8 +11,8 @@
---
This document aims to provide instructions to create a gem5-compatible disk
-image containing the SPEC 2017 benchmark suite and also to provide necessary
-configuration files.
+image containing the SPEC 2017 benchmark suite. It also demonstrates how to
+simulate the SPEC CPU2017 benchmarks using an example configuration script.
## Building the Disk Image
Creating a disk-image for SPEC 2017 requires the benchmark suite ISO file.
@@ -39,10 +39,6 @@
| |___ spec-2017.json # the Packer script
| |___ cpu2017-1.1.0.iso # SPEC 2017 ISO (add here)
|
- |___ configs
- | |___ system/
- | |___ run_spec.py # gem5 run script
- |
|___ vmlinux-4.19.83 # Linux kernel, link to download provided below
|
|___ README.md
@@ -67,106 +63,98 @@
./build.sh # the script downloading packer binary and building the disk image
```
-## gem5 Configuration Scripts
-gem5 scripts which configure the system and run the simulation are available
-in `configs/`.
-The main script `run_spec.py` expects following arguments:
+## Simulating SPEC CPU2017 using an example script
-`usage: run_spec.py [-h] [-l] [-z] kernel disk cpu benchmark size`
-
-`-h`: show this help message and exit.
-
-`-l`, `--no-copy-logs`: optional, to not copy SPEC run logs to the host system,
-logs are copied by default, and are available in the result folder.
-
-`-z`, `--allow-listeners`: optional, to turn on GDB listening ports, the ports
-are off by default.
-
-`kernel`: required, a positional argument specifying the path to the Linux
-kernel. This has been tested with version 4.19.83, available at
-<http://dist.gem5.org/dist/v21-1/kernels/x86/static/vmlinux-4.19.83>. Info on
-building Linux kernels can be found in `src/linux-kernels`.
-
-`disk`: required, a positional argument specifying the path to the disk image
-containing SPEC 2017 benchmark suite.
-
-`cpu`: required, a positional argument specifying the name of either a
-detailed CPU model or KVM CPU model.
-
-The available CPU models are,
-
-| cpu | Corresponding CPU model in gem5 |
-| ------ | ------------------------------- |
-| kvm | |
-| o3 | DerivO3CPU |
-| atomic | AtomicSimpleCPU |
-| timing | TimingSimpleCPU |
-
-`benchmark`: required, a positional argument specifying the name of the SPEC
-2017 to run. Listed below are valid options:
-
-* 500.perlbench_r
-* 502.gcc_r
-* 503.bwaves_r
-* 505.mcf_r
-* 507.cactuBSSN_r
-* 508.namd_r
-* 510.parest_r
-* 511.povray_r
-* 519.lbm_r
-* 520.omnetpp_r
-* 521.wrf_r
-* 523.xalancbmk_r
-* 525.x264_r
-* 526.blender_r
-* 527.cam4_r
-* 531.deepsjeng_r
-* 538.imagick_r
-* 541.leela_r
-* 544.nab_r
-* 548.exchange2_r
-* 549.fotonik3d_r
-* 554.roms_r
-* 557.xz_r
-* 600.perlbench_s
-* 602.gcc_s
-* 603.bwaves_s
-* 605.mcf_s
-* 607.cactuBSSN_s
-* 619.lbm_s
-* 620.omnetpp_s
-* 621.wrf_s
-* 623.xalancbmk_s
-* 625.x264_s
-* 627.cam4_s
-* 628.pop2_s
-* 631.deepsjeng_s
-* 638.imagick_s
-* 641.leela_s
-* 644.nab_s
-* 648.exchange2_s
-* 649.fotonik3d_s
-* 654.roms_s
-* 657.xz_s
-* 996.specrand_fs
-* 997.specrand_fr
-* 998.specrand_is
-* 999.specrand_ir
-
-`size`: required, a positional argument specifying the input data size. Valid
-values are `test`, `train`, and `ref`.
-
-As a minimum the following parameters must be specified:
+An example script with a pre-configured system is available in the following directory within the gem5 repository:
```
-<gem5 X86 binary> --outdir <output directory> configs/run_spec.py <kernel> <disk> <cpu> <mem_sys> <benchmark> <size>
+gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
```
-**Note**: `--outdir` is a required argument when running the gem5 binary with SPEC 2006.
+The example script specifies a system with the following parameters:
+* A `SimpleSwitchableProcessor` (`KVM` for startup and `TIMING` for ROI execution). There are 2 CPU cores, each clocked at 3 GHz.
+* 2 Level `MESI_Two_Level` cache with 32 kB L1I and L1D size, and, 256 kB L2 size. The L1 cache(s) has associativity of 8, and, the L2 cache has associativity 16. There are 2 L2 cache banks.
+* The system has 3 GB `SingleChannelDDR4_2400` memory.
+* The script uses `x86-linux-kernel-4.19.83` and the disk image created from following the instructions in this `README.md`.
+* The user inputs the path to the built disk image, along with the root partition.
+* The script then uses `CustomResource` class to use the `spec-2017` disk-image.
+
+The example script must be run with the `X86_MESI_Two_Level` binary. To build:
+
+```sh
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5
+scons build/X86/gem5.opt -j<proc>
+```
+Once compiled, you may use the example configuration file to run the SPEC CPU2017 benchmark programs using the following command:
+
+```sh
+# In the gem5 directory
+build/X86/gem5.opt \
+configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py \
+--image <path_to_built_spec-2017_disk_image> \
+--partition <root_partition_to_mount> \
+--benchmark <benchmark_program> \
+--size <workload_size>
+```
+
+Description of the four arguments, provided in the above command are:
+* **--image** refers to the full path of the the SPEC CPU2017 disk-image, built using the instructions specified above.
+* **--partition** refers to the root partition of the disk-image to mount. If the disk has no partitions, then pass `--partition ""`. Otherwise, pass an integer specifying the partition number. Set `--partition 1` if the above instructions to build the disk-image are followed.
+* **--benchmark**, which refers to one of 47 benchmark programs, provided in the SPEC CPU2017 Benchmark Suite. For more information on the workloads can be found at <https://www.spec.org/cpu2017/>. The list of benchmark programs include:
+ * 500.perlbench_r
+ * 502.gcc_r
+ * 503.bwaves_r
+ * 505.mcf_r
+ * 507.cactuBSSN_r
+ * 508.namd_r
+ * 510.parest_r
+ * 511.povray_r
+ * 519.lbm_r
+ * 520.omnetpp_r
+ * 521.wrf_r
+ * 523.xalancbmk_r
+ * 525.x264_r
+ * 526.blender_r
+ * 527.cam4_r
+ * 531.deepsjeng_r
+ * 538.imagick_r
+ * 541.leela_r
+ * 544.nab_r
+ * 548.exchange2_r
+ * 549.fotonik3d_r
+ * 554.roms_r
+ * 557.xz_r
+ * 600.perlbench_s
+ * 602.gcc_s
+ * 603.bwaves_s
+ * 605.mcf_s
+ * 607.cactuBSSN_s
+ * 619.lbm_s
+ * 620.omnetpp_s
+ * 621.wrf_s
+ * 623.xalancbmk_s
+ * 625.x264_s
+ * 627.cam4_s
+ * 628.pop2_s
+ * 631.deepsjeng_s
+ * 638.imagick_s
+ * 641.leela_s
+ * 644.nab_s
+ * 648.exchange2_s
+ * 649.fotonik3d_s
+ * 654.roms_s
+ * 657.xz_s
+ * 996.specrand_fs
+ * 997.specrand_fr
+ * 998.specrand_is
+ * 999.specrand_ir
+* **--size**, which refers to the workload size to simulate. Valid choices for `--size` are `test`, `train` and `ref`.
+
+The output directory, where the simulation statistics will be redirected to, will have a new folder named `speclogs_<Day><Month><Date><Hour><Minute><Second>`. The time is of execution is appended to avoid conflicts while coping the files. The output files, generated on the disk-image in the folder `speclogs` will be copied to this aforementioned directory.
## Working Status
Status of these benchmarks runs with respect to gem5-20, linux kernel version
4.19.83 and gcc version 7.5.0 can be found
[here](https://www.gem5.org/documentation/benchmark_status/gem5-20#spec-2017-tests)
-
diff --git a/src/spec-2017/configs/run_spec.py b/src/spec-2017/configs/run_spec.py
deleted file mode 100644
index 63f3934..0000000
--- a/src/spec-2017/configs/run_spec.py
+++ /dev/null
@@ -1,301 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2019 The Regents of the University of California.
-# All rights reserved.
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power, Ayaz Akram, Hoa Nguyen
-
-""" Script to run a SPEC benchmark in full system mode with gem5.
-
- Inputs:
- * This script expects the following as arguments:
- ** kernel:
- This is a positional argument specifying the path to
- vmlinux.
- ** disk:
- This is a positional argument specifying the path to the
- disk image containing the installed SPEC benchmarks.
- ** cpu:
- This is a positional argument specifying the name of the
- detailed CPU model. The names of the available CPU models
- are available in the getDetailedCPUModel(cpu_name) function.
- The function should be modified to add new CPU models.
- Currently, the available CPU models are:
- - kvm: this is not a detailed CPU model, ideal for testing.
- - o3: DerivO3CPU.
- - atomic: AtomicSimpleCPU.
- - timing: TimingSimpleCPU.
- ** benchmark:
- This is a positional argument specifying the name of the
- SPEC benchmark to run. Most SPEC benchmarks are available.
- Please follow this link to check the availability of the
- benchmarks. The working benchmark matrix is near the end
- of the page:
- (SPEC 2006) https://gem5art.readthedocs.io/en/latest/tutorials/spec2006-tutorial.html#appendix-i-working-spec-2006-benchmarks-x-cpu-model-table
- (SPEC 2017) https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html#appendix-i-working-spec-2017-benchmarks-x-cpu-model-table
- ** size:
- This is a positional argument specifying the size of the
- benchmark. The available sizes are: ref, test, train.
- ** --no-copy-logs:
- This is an optional argument specifying the reports of
- the benchmark run is not copied to the output folder.
- The reports are copied by default.
- ** --allow-listeners:
- This is an optional argument specifying gem5 to open GDB
- listening ports. Usually, the ports are opened for debugging
- purposes.
- By default, the ports are off.
-"""
-import os
-
-import m5
-import m5.ticks
-from m5.objects import *
-
-import argparse
-
-from system import *
-
-
-def writeBenchScript(dir, benchmark_name, size, output_path):
- """
- This method creates a script in dir which will be eventually
- passed to the simulated system (to run a specific benchmark
- at bootup).
- """
- input_file_name = '{}/run_{}_{}'.format(dir, benchmark_name, size)
- with open(input_file_name, "w") as f:
- f.write('{} {} {}'.format(benchmark_name, size, output_path))
- return input_file_name
-
-def parse_arguments():
- parser = argparse.ArgumentParser(description=
- "gem5 config file to run SPEC benchmarks")
- parser.add_argument("kernel", type = str, help = "Path to vmlinux")
- parser.add_argument("disk", type = str,
- help = "Path to the disk image containing SPEC benchmarks")
- parser.add_argument("cpu", type = str, help = "Name of the detailed CPU")
- parser.add_argument("mem_sys", type = str, help = "Name of the memory system")
- parser.add_argument("benchmark", type = str,
- help = "Name of the SPEC benchmark")
- parser.add_argument("size", type = str,
- help = "Available sizes: test, train, ref")
- parser.add_argument("-l", "--no-copy-logs", default = False,
- action = "store_true",
- help = "Not to copy SPEC run logs to the host system;"
- "Logs are copied by default")
- parser.add_argument("-z", "--allow-listeners", default = False,
- action = "store_true",
- help = "Turn on ports;"
- "The ports are off by default")
- return parser.parse_args()
-
-def getDetailedCPUModel(cpu_name):
- '''
- Return the CPU model corresponding to the cpu_name.
- '''
- available_models = {"kvm": X86KvmCPU,
- "o3": DerivO3CPU,
- "atomic": AtomicSimpleCPU,
- "timing": TimingSimpleCPU
- }
- try:
- available_models["FlexCPU"] = FlexCPU
- except NameError:
- # FlexCPU is not defined
- pass
- # https://docs.python.org/3/library/stdtypes.html#dict.get
- # dict.get() returns None if the key does not exist
- return available_models.get(cpu_name)
-
-def getBenchmarkName(benchmark_name):
- if benchmark_name.endswith("(base)"):
- benchmark_name = benchmark_name[:-6]
- return benchmark_name
-
-def create_system(linux_kernel_path, disk_image_path, detailed_cpu_model, memory_system):
- # create the system we are going to simulate
- ruby_protocols = [ "MI_example", "MESI_Two_Level", "MOESI_CMP_directory"]
- if memory_system == 'classic':
- system = MySystem(kernel = linux_kernel_path,
- disk = disk_image_path,
- num_cpus = 1, # run the benchmark in a single thread
- no_kvm = False,
- TimingCPUModel = detailed_cpu_model)
- elif memory_system in ruby_protocols:
- system = MyRubySystem(kernel = linux_kernel_path,
- disk = disk_image_path,
- num_cpus = 1, # run the benchmark in a single thread
- mem_sys = memory_system,
- no_kvm = False,
- TimingCPUModel = detailed_cpu_model)
- else:
- m5.fatal("Bad option for mem_sys, should be "
- "{}, or 'classic'".format(', '.join(ruby_protocols)))
-
- # For workitems to work correctly
- # This will cause the simulator to exit simulation when the first work
- # item is reached and when the first work item is finished.
- system.work_begin_exit_count = 1
- system.work_end_exit_count = 1
-
- # set up the root SimObject and start the simulation
- root = Root(full_system = True, system = system)
-
- if system.getHostParallel():
- # Required for running kvm on multiple host cores.
- # Uses gem5's parallel event queue feature
- # Note: The simulator is quite picky about this number!
- root.sim_quantum = int(1e9) # 1 ms
-
- return root, system
-
-
-def boot_linux():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Booting Linux")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while booting linux: {}".format(exit_cause))
- exit(1)
- print("Done booting Linux")
- return success, exit_cause
-
-def run_spec_benchmark():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Start running benchmark")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while running benchmark: {}".format(exit_cause))
- exit(1)
- print("Benchmark done")
- return success, exit_cause
-
-def copy_spec_logs():
- '''
- Output 1: False if errors occur, True otherwise
- Output 2: exit cause
- '''
- print("Copying SPEC logs")
- exit_event = m5.simulate()
- exit_cause = exit_event.getCause()
- success = exit_cause == "m5_exit instruction encountered"
- if not success:
- print("Error while copying SPEC log files: {}".format(exit_cause))
- exit(1)
- print("Copying done")
- return success, exit_cause
-
-if __name__ == "__m5_main__":
- args = parse_arguments()
-
- cpu_name = args.cpu
- mem_sys = args.mem_sys
- benchmark_name = getBenchmarkName(args.benchmark)
- benchmark_size = args.size
- linux_kernel_path = args.kernel
- disk_image_path = args.disk
- no_copy_logs = args.no_copy_logs
- allow_listeners = args.allow_listeners
-
- if not no_copy_logs and not os.path.isabs(m5.options.outdir):
- print("Please specify the --outdir (output directory) of gem5"
- " in the form of an absolute path")
- print("An example: build/X86/gem5.opt --outdir /home/user/m5out/"
- " configs-spec-tests/run_spec ...")
- exit(1)
-
- output_dir = os.path.join(m5.options.outdir, "speclogs")
-
- # Get the DetailedCPU class from its name
- detailed_cpu = getDetailedCPUModel(cpu_name)
- if detailed_cpu == None:
- print("'{}' is not define in the config script.".format(cpu_name))
- print("Change getDeatiledCPUModel() in run_spec.py "
- "to add more CPU Models.")
- exit(1)
-
- if not benchmark_size in ["ref", "train", "test"]:
- print("Benchmark size must be one of the following: ref, train, test")
- exit(1)
-
- root, system = create_system(linux_kernel_path, disk_image_path,
- detailed_cpu, mem_sys)
-
- # Create and pass a script to the simulated system to run the required
- # benchmark
- system.readfile = writeBenchScript(m5.options.outdir, benchmark_name,
- benchmark_size, output_dir)
-
- # needed for long running jobs
- if not allow_listeners:
- m5.disableAllListeners()
-
- # instantiate all of the objects we've created above
- m5.instantiate()
-
- # booting linux
- success, exit_cause = boot_linux()
-
- # reset stats
- print("Reset stats")
- m5.stats.reset()
-
- # switch from KVM to detailed CPU
- if not cpu_name == "kvm":
- print("Switching to detailed CPU")
- system.switchCpus(system.cpu, system.detailed_cpu)
- print("Switching done")
-
- # running benchmark
- print("Benchmark: {}; Size: {}".format(benchmark_name, benchmark_size))
- success, exit_cause = run_spec_benchmark()
-
- # output the stats after the benchmark is complete
- print("Output stats")
- m5.stats.dump()
-
- if not no_copy_logs:
- # create the output folder
- if not os.path.exists(output_dir):
- os.makedirs(output_dir)
-
- # switch from detailed CPU to KVM
- if not cpu_name == "kvm":
- print("Switching to KVM")
- system.switchCpus(system.detailed_cpu, system.cpu)
- print("Switching done")
-
- # copying logs
- success, exit_cause = copy_spec_logs()
diff --git a/src/spec-2017/configs/system/MESI_Two_Level.py b/src/spec-2017/configs/system/MESI_Two_Level.py
deleted file mode 100644
index 17df7c0..0000000
--- a/src/spec-2017/configs/system/MESI_Two_Level.py
+++ /dev/null
@@ -1,340 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2020 The Regents of the University of California.
-# All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MESI TWO Level protocol
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MESITwoLevelCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
- fatal("This system assumes MESI_Two_Level!")
-
- super(MESITwoLevelCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MESI_Two_Level example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU core.
- # The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in range(self._numL2Caches)] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False)
- self.l2_select_num_bits = int(math.log(num_l2Caches , 2))
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.enable_prefetch = False
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.out_port = ruby_system.network.in_port
-
- self.optionalQueue = MessageBuffer()
-
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getBlockSizeBits(system,
- num_l2Caches))
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
- self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2017/configs/system/MI_example_caches.py b/src/spec-2017/configs/system/MI_example_caches.py
deleted file mode 100644
index 0d028df..0000000
--- a/src/spec-2017/configs/system/MI_example_caches.py
+++ /dev/null
@@ -1,279 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2015 Jason Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Power
-
-""" This file creates a set of Ruby caches, the Ruby network, and a simple
-point-to-point topology.
-See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
-You can change simple_ruby to import from this file instead of from msi_caches
-to use the MI_example protocol instead of MSI.
-
-IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
- also needs to be updated. For now, email Jason <jason@lowepower.com>
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MIExampleSystem(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MI_example':
- fatal("This system assumes MI_example!")
-
- super(MIExampleSystem, self).__init__()
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MI example uses 5 virtual networks
- self.number_of_virtual_networks = 5
- self.network.number_of_virtual_networks = 5
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # Create one controller for each L1 cache (and the cache mem obj.)
- # Create a single directory controller (Really the memory cntrl)
- self.controllers = \
- [L1Cache(system, self, cpu) for cpu in cpus] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU. In many systems this is more
- # complicated since you have to create sequencers for DMA controllers
- # and other controllers, too.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].cacheMemory,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[0:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu):
- """CPUs are needed to grab the clock domain and system is needed for
- the cache block size.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.cacheMemory = RubyCache(size = '16kB',
- assoc = 8,
- start_index_bit = self.getBlockSizeBits(system))
- self.clk_domain = cpu.clk_domain
- self.send_evictions = self.sendEvicts(cpu)
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromCache = MessageBuffer(ordered = True)
- self.requestFromCache.out_port = ruby_system.network.in_port
- self.responseFromCache = MessageBuffer(ordered = True)
- self.responseFromCache.out_port = ruby_system.network.in_port
- self.forwardToCache = MessageBuffer(ordered = True)
- self.forwardToCache.in_port = ruby_system.network.out_port
- self.responseToCache = MessageBuffer(ordered = True)
- self.responseToCache.in_port = ruby_system.network.out_port
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer(ordered = True)
- self.requestToDir.in_port = ruby_system.network.out_port
- self.dmaRequestToDir = MessageBuffer(ordered = True)
- self.dmaRequestToDir.in_port = ruby_system.network.out_port
-
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.dmaResponseFromDir = MessageBuffer(ordered = True)
- self.dmaResponseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.requestToDir = MessageBuffer()
- self.requestToDir.out_port = ruby_system.network.in_port
- self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.in_port = ruby_system.network.out_port
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2017/configs/system/MOESI_CMP_directory.py b/src/spec-2017/configs/system/MOESI_CMP_directory.py
deleted file mode 100644
index 15b215d..0000000
--- a/src/spec-2017/configs/system/MOESI_CMP_directory.py
+++ /dev/null
@@ -1,350 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2020 The Regents of the University of California.
-# All Rights Reserved
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-
-""" This file creates a set of Ruby caches for the MOESI CMP directory
-protocol.
-This protocol models two level cache hierarchy. The L1 cache is split into
-instruction and data cache.
-
-This system support the memory size of up to 3GB.
-
-"""
-
-from __future__ import print_function
-from __future__ import absolute_import
-
-import math
-
-from m5.defines import buildEnv
-from m5.util import fatal, panic
-
-from m5.objects import *
-
-class MOESICMPDirCache(RubySystem):
-
- def __init__(self):
- if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
- fatal("This system assumes MOESI_CMP_directory!")
-
- super(MOESICMPDirCache, self).__init__()
-
- self._numL2Caches = 8
-
- def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
- """Set up the Ruby cache subsystem. Note: This can't be done in the
- constructor because many of these items require a pointer to the
- ruby system (self). This causes infinite recursion in initialize()
- if we do this in the __init__.
- """
- # Ruby's global network.
- self.network = MyNetwork(self)
-
- # MOESI_CMP_directory example uses 3 virtual networks
- self.number_of_virtual_networks = 3
- self.network.number_of_virtual_networks = 3
-
- # There is a single global list of all of the controllers to make it
- # easier to connect everything to the global network. This can be
- # customized depending on the topology/network requirements.
- # L1 caches are private to a core, hence there are one L1 cache per CPU core.
- # The number of L2 caches are dependent to the architecture.
- self.controllers = \
- [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
- [L2Cache(system, self, self._numL2Caches) for num in range(self._numL2Caches)] + \
- [DirController(self, system.mem_ranges, mem_ctrls)] + \
- [DMAController(self) for i in range(len(dma_ports))]
-
- # Create one sequencer per CPU and dma controller.
- # Sequencers for other controllers can be here here.
- self.sequencers = [RubySequencer(version = i,
- # Grab dcache from ctrl
- dcache = self.controllers[i].L1Dcache,
- clk_domain = self.controllers[i].clk_domain,
- pio_request_port = iobus.cpu_side_ports,
- mem_request_port = iobus.cpu_side_ports,
- pio_response_port = iobus.mem_side_ports
- ) for i in range(len(cpus))] + \
- [DMASequencer(version = i,
- in_ports = port)
- for i,port in enumerate(dma_ports)
- ]
-
- for i,c in enumerate(self.controllers[:len(cpus)]):
- c.sequencer = self.sequencers[i]
-
- #Connecting the DMA sequencer to DMA controller
- for i,d in enumerate(self.controllers[-len(dma_ports):]):
- i += len(cpus)
- d.dma_sequencer = self.sequencers[i]
-
- self.num_of_sequencers = len(self.sequencers)
-
- # Create the network and connect the controllers.
- # NOTE: This is quite different if using Garnet!
- self.network.connectControllers(self.controllers)
- self.network.setup_buffers()
-
- # Set up a proxy port for the system_port. Used for load binaries and
- # other functional-only things.
- self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_ports
- self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
-
- # Connect the cpu's cache, interrupt, and TLB ports to Ruby
- for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_ports
- cpu.dcache_port = self.sequencers[i].in_ports
- cpu.createInterruptController()
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
- if isa == 'x86' or isa == 'arm':
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].in_ports, self.sequencers[i].in_ports)
-
-
-class L1Cache(L1Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, cpu, num_l2Caches):
- """Creating L1 cache controller. Consist of both instruction
- and data cache. The size of data cache is 512KB and
- 8-way set associative. The instruction cache is 32KB,
- 2-way set associative.
- """
- super(L1Cache, self).__init__()
-
- self.version = self.versionCount()
- block_size_bits = int(math.log(system.cache_line_size, 2))
- l1i_size = '32kB'
- l1i_assoc = '2'
- l1d_size = '512kB'
- l1d_assoc = '8'
- # This is the cache memory object that stores the cache data and tags
- self.L1Icache = RubyCache(size = l1i_size,
- assoc = l1i_assoc,
- start_index_bit = block_size_bits ,
- is_icache = True,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.L1Dcache = RubyCache(size = l1d_size,
- assoc = l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False,
- dataAccessLatency = 1,
- tagAccessLatency = 1)
- self.clk_domain = cpu.clk_domain
- self.prefetcher = RubyPrefetcher()
- self.send_evictions = self.sendEvicts(cpu)
- self.transitions_per_cycle = 4
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getBlockSizeBits(self, system):
- bits = int(math.log(system.cache_line_size, 2))
- if 2**bits != system.cache_line_size.value:
- panic("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, cpu):
- """True if the CPU model or ISA requires sending evictions from caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
- return True
- return False
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.mandatoryQueue = MessageBuffer()
- self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.out_port = ruby_system.network.in_port
- self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.out_port = ruby_system.network.in_port
- self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.in_port = ruby_system.network.out_port
- self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class L2Cache(L2Cache_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, system, ruby_system, num_l2Caches):
-
- super(L2Cache, self).__init__()
-
- self.version = self.versionCount()
- # This is the cache memory object that stores the cache data and tags
- self.L2cache = RubyCache(size = '1 MB',
- assoc = 16,
- start_index_bit = self.getL2StartIdx(system,
- num_l2Caches),
- dataAccessLatency = 20,
- tagAccessLatency = 20)
-
- self.transitions_per_cycle = '4'
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def getL2StartIdx(self, system, num_l2caches):
- l2_bits = int(math.log(num_l2caches, 2))
- bits = int(math.log(system.cache_line_size, 2)) + l2_bits
- return bits
-
-
- def connectQueues(self, ruby_system):
- """Connect all of the queues for this controller.
- """
- self.GlobalRequestFromL2Cache = MessageBuffer()
- self.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
- self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
- self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.out_port = ruby_system.network.in_port
-
- self.GlobalRequestToL2Cache = MessageBuffer()
- self.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
- self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
- self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.in_port = ruby_system.network.out_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class DirController(Directory_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system, ranges, mem_ctrls):
- """ranges are the memory ranges assigned to this controller.
- """
- if len(mem_ctrls) > 1:
- panic("This cache system can only be connected to one mem ctrl")
- super(DirController, self).__init__()
- self.version = self.versionCount()
- self.addr_ranges = ranges
- self.ruby_system = ruby_system
- self.directory = RubyDirectoryMemory()
- # Connect this directory to the memory side.
- self.memory_out_port = mem_ctrls[0].port
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.requestToDir = MessageBuffer()
- self.requestToDir.in_port = ruby_system.network.out_port
- self.responseToDir = MessageBuffer()
- self.responseToDir.in_port = ruby_system.network.out_port
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.out_port = ruby_system.network.in_port
- self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.out_port = ruby_system.network.in_port
- self.requestToMemory = MessageBuffer()
- self.responseFromMemory = MessageBuffer()
- self.triggerQueue = MessageBuffer(ordered = True)
-
-class DMAController(DMA_Controller):
-
- _version = 0
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, ruby_system):
- super(DMAController, self).__init__()
- self.version = self.versionCount()
- self.ruby_system = ruby_system
- self.connectQueues(ruby_system)
-
- def connectQueues(self, ruby_system):
- self.mandatoryQueue = MessageBuffer()
- self.responseFromDir = MessageBuffer()
- self.responseFromDir.in_port = ruby_system.network.out_port
- self.reqToDir = MessageBuffer()
- self.reqToDir.out_port = ruby_system.network.in_port
- self.respToDir = MessageBuffer()
- self.respToDir.out_port = ruby_system.network.in_port
- self.triggerQueue = MessageBuffer(ordered = True)
-
-
-class MyNetwork(SimpleNetwork):
- """A simple point-to-point network. This doesn't not use garnet.
- """
-
- def __init__(self, ruby_system):
- super(MyNetwork, self).__init__()
- self.netifs = []
- self.ruby_system = ruby_system
-
- def connectControllers(self, controllers):
- """Connect all of the controllers to routers and connec the routers
- together in a point-to-point network.
- """
- # Create one router/switch per controller in the system
- self.routers = [Switch(router_id = i) for i in range(len(controllers))]
-
- # Make a link from each controller to the router. The link goes
- # externally to the network.
- self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
- int_node=self.routers[i])
- for i, c in enumerate(controllers)]
-
- # Make an "internal" link (internal to the network) between every pair
- # of routers.
- link_count = 0
- self.int_links = []
- for ri in self.routers:
- for rj in self.routers:
- if ri == rj: continue # Don't connect a router to itself!
- link_count += 1
- self.int_links.append(SimpleIntLink(link_id = link_count,
- src_node = ri,
- dst_node = rj))
diff --git a/src/spec-2017/configs/system/__init__.py b/src/spec-2017/configs/system/__init__.py
deleted file mode 100644
index 94e676f..0000000
--- a/src/spec-2017/configs/system/__init__.py
+++ /dev/null
@@ -1,31 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from .system import MySystem
-from .ruby_system import MyRubySystem
diff --git a/src/spec-2017/configs/system/caches.py b/src/spec-2017/configs/system/caches.py
deleted file mode 100644
index 84f63e7..0000000
--- a/src/spec-2017/configs/system/caches.py
+++ /dev/null
@@ -1,171 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-""" Caches with options for a simple gem5 configuration script
-
-This file contains L1 I/D and L2 caches to be used in the simple
-gem5 configuration script.
-"""
-
-from m5.objects import Cache, L2XBar, StridePrefetcher
-# Some specific options for caches
-# For all options see src/mem/cache/BaseCache.py
-
-class PrefetchCache(Cache):
-
- def __init__(self, options = None):
- super(PrefetchCache, self).__init__()
- if not options or options.no_prefetchers:
- return
- self.prefetcher = StridePrefetcher()
-
-class L1Cache(PrefetchCache):
- """Simple L1 Cache with default values"""
-
- assoc = 8
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 16
- tgts_per_mshr = 20
- writeback_clean = True
-
- def __init__(self):
- super(L1Cache, self).__init__()
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU-side port
- This must be defined in a subclass"""
- raise NotImplementedError
-
-class L1ICache(L1Cache):
- """Simple L1 instruction cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1ICache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU icache port"""
- self.cpu_side = cpu.icache_port
-
-class L1DCache(L1Cache):
- """Simple L1 data cache with default values"""
-
- # Set the default size
- size = '32kB'
-
- def __init__(self):
- super(L1DCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect this cache's port to a CPU dcache port"""
- self.cpu_side = cpu.dcache_port
-
-class MMUCache(Cache):
- # Default parameters
- size = '8kB'
- assoc = 4
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(MMUCache, self).__init__()
-
- def connectCPU(self, cpu):
- """Connect the CPU itb and dtb to the cache
- Note: This creates a new crossbar
- """
- self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
-
- def connectBus(self, bus):
- """Connect this cache to a memory-side bus"""
- self.mem_side = bus.cpu_side_ports
-
-class L2Cache(PrefetchCache):
- """Simple L2 Cache with default values"""
-
- # Default parameters
- size = '256kB'
- assoc = 16
- tag_latency = 10
- data_latency = 10
- response_latency = 1
- mshrs = 20
- tgts_per_mshr = 12
- writeback_clean = True
-
- def __init__(self):
- super(L2Cache, self).__init__()
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
-
-class L3Cache(Cache):
- """Simple L3 Cache bank with default values
- This assumes that the L3 is made up of multiple banks. This cannot
- be used as a standalone L3 cache.
- """
-
- # Default parameters
- assoc = 32
- tag_latency = 40
- data_latency = 40
- response_latency = 10
- mshrs = 256
- tgts_per_mshr = 12
- clusivity = 'mostly_excl'
-
- size = '4MB'
-
- def __init__(self):
- super(L3Cache, self).__init__()
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.mem_side_ports
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.cpu_side_ports
-
diff --git a/src/spec-2017/configs/system/fs_tools.py b/src/spec-2017/configs/system/fs_tools.py
deleted file mode 100644
index 5e5e2df..0000000
--- a/src/spec-2017/configs/system/fs_tools.py
+++ /dev/null
@@ -1,39 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
-
-class CowDisk(IdeDisk):
-
- def __init__(self, filename):
- super(CowDisk, self).__init__()
- self.driveID = 'device0'
- self.image = CowDiskImage(child=RawDiskImage(read_only=True),
- read_only=False)
- self.image.child.image_file = filename
diff --git a/src/spec-2017/configs/system/ruby_system.py b/src/spec-2017/configs/system/ruby_system.py
deleted file mode 100755
index d1ddb07..0000000
--- a/src/spec-2017/configs/system/ruby_system.py
+++ /dev/null
@@ -1,244 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2016 Jason Lowe-Power
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-
-
-class MyRubySystem(System):
-
- def __init__(self, kernel, disk, mem_sys, num_cpus, TimingCPUModel, no_kvm=False):
- super(MyRubySystem, self).__init__()
- self._no_kvm = no_kvm
-
- self._host_parallel = True
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '2.3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- self.mem_ranges = [AddrRange(Addr('3GB')), # All data
- AddrRange(0xC0000000, size=0x100000), # For I/0
- ]
-
- self.initFS(num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus,TimingCPUModel)
-
- self.createMemoryControllersDDR4()
-
- # Create the cache hierarchy for the system.
- if mem_sys == 'MI_example':
- from .MI_example_caches import MIExampleSystem
- self.caches = MIExampleSystem()
- elif mem_sys == 'MESI_Two_Level':
- from .MESI_Two_Level import MESITwoLevelCache
- self.caches = MESITwoLevelCache()
- elif mem_sys == 'MOESI_CMP_directory':
- from .MOESI_CMP_directory import MOESICMPDirCache
- self.caches = MOESICMPDirCache()
- self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports],
- self.iobus)
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus, TimingCPUModel):
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.mem_mode = 'timing'
-
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.detailed_cpu = [TimingCPUModel(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
-
- self.createCPUThreads(self.detailed_cpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createMemoryControllersDDR4(self):
- self._createMemoryControllers(1, DDR4_2400_16x4)
-
- def _createMemoryControllers(self, num, cls):
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = self.mem_ranges[0]))
- for i in range(num)
- ]
-
- def _createKernelMemoryController(self, cls):
- return cls(range = self.mem_ranges[0],
- port = self.membus.mem_side_ports)
-
- def initFS(self, cpus):
- self.pc = Pc()
-
- self.workload = X86FsLinux()
-
- # North Bridge
- self.iobus = IOXBar()
-
- # connect the io bus
- # Note: pass in a reference to where Ruby will connect to in the future
- # so the port isn't connected twice.
- self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- self.workload.e820_table.entries = entries
diff --git a/src/spec-2017/configs/system/system.py b/src/spec-2017/configs/system/system.py
deleted file mode 100644
index b07596c..0000000
--- a/src/spec-2017/configs/system/system.py
+++ /dev/null
@@ -1,375 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2018 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power
-
-import m5
-from m5.objects import *
-from .fs_tools import *
-from .caches import *
-
-
-class MySystem(System):
-
- def __init__(self, kernel, disk, num_cpus, TimingCPUModel, no_kvm=False):
- super(MySystem, self).__init__()
- self._no_kvm = no_kvm
-
- self._host_parallel = True
-
- # Set up the clock domain and the voltage domain
- self.clk_domain = SrcClockDomain()
- self.clk_domain.clock = '2.3GHz'
- self.clk_domain.voltage_domain = VoltageDomain()
-
- mem_size = '32GB'
- self.mem_ranges = [AddrRange('100MB'), # For kernel
- AddrRange(0xC0000000, size=0x100000), # For I/0
- AddrRange(Addr('4GB'), size = mem_size) # All data
- ]
-
- # Create the main memory bus
- # This connects to main memory
- self.membus = SystemXBar(width = 64) # 64-byte width
- self.membus.badaddr_responder = BadAddr()
- self.membus.default = Self.badaddr_responder.pio
-
- # Set up the system port for functional access from the simulator
- self.system_port = self.membus.cpu_side_ports
-
- self.initFS(self.membus, num_cpus)
-
- # Replace these paths with the path to your disk images.
- # The first disk is the root disk. The second could be used for swap
- # or anything else.
- self.setDiskImages(disk, disk)
-
- # Change this path to point to the kernel you want to use
- self.workload.object_file = kernel
- # Options specified on the kernel command line
- boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
- 'root=/dev/hda1']
-
- self.workload.command_line = ' '.join(boot_options)
-
- # Create the CPUs for our system.
- self.createCPU(num_cpus, TimingCPUModel)
-
- # Create the cache heirarchy for the system.
- self.createCacheHierarchy()
-
- # Set up the interrupt controllers for the system (x86 specific)
- self.setupInterrupts()
-
- self.createMemoryControllersDDR4()
-
- if self._host_parallel:
- # To get the KVM CPUs to run on different host CPUs
- # Specify a different event queue for each CPU
- for i,cpu in enumerate(self.cpu):
- for obj in cpu.descendants():
- obj.eventq_index = 0
- cpu.eventq_index = i + 1
-
- def getHostParallel(self):
- return self._host_parallel
-
- def totalInsts(self):
- return sum([cpu.totalInsts() for cpu in self.cpu])
-
- def createCPUThreads(self, cpu):
- for c in cpu:
- c.createThreads()
-
- def createCPU(self, num_cpus, TimingCPUModel):
- if self._no_kvm:
- self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.mem_mode = 'timing'
-
- else:
- # Note KVM needs a VM and atomic_noncaching
- self.cpu = [X86KvmCPU(cpu_id = i)
- for i in range(num_cpus)]
- self.createCPUThreads(self.cpu)
- self.kvm_vm = KvmVM()
- self.mem_mode = 'atomic_noncaching'
-
- self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
- self.createCPUThreads(self.atomicCpu)
-
- self.detailed_cpu = [TimingCPUModel(cpu_id = i,
- switched_out = True)
- for i in range(num_cpus)]
-
- self.createCPUThreads(self.detailed_cpu)
-
- def switchCpus(self, old, new):
- assert(new[0].switchedOut())
- m5.switchCpus(self, list(zip(old, new)))
-
- def setDiskImages(self, img_path_1, img_path_2):
- disk0 = CowDisk(img_path_1)
- disk2 = CowDisk(img_path_2)
- self.pc.south_bridge.ide.disks = [disk0, disk2]
-
- def createCacheHierarchy(self):
- # Create an L3 cache (with crossbar)
- self.l3bus = L2XBar(width = 64,
- snoop_filter = SnoopFilter(max_capacity='32MB'))
-
- for cpu in self.cpu:
- # Create a memory bus, a coherent crossbar, in this case
- cpu.l2bus = L2XBar()
-
- # Create an L1 instruction and data cache
- cpu.icache = L1ICache()
- cpu.dcache = L1DCache()
- cpu.mmucache = MMUCache()
-
- # Connect the instruction and data caches to the CPU
- cpu.icache.connectCPU(cpu)
- cpu.dcache.connectCPU(cpu)
- cpu.mmucache.connectCPU(cpu)
-
- # Hook the CPU ports up to the l2bus
- cpu.icache.connectBus(cpu.l2bus)
- cpu.dcache.connectBus(cpu.l2bus)
- cpu.mmucache.connectBus(cpu.l2bus)
-
- # Create an L2 cache and connect it to the l2bus
- cpu.l2cache = L2Cache()
- cpu.l2cache.connectCPUSideBus(cpu.l2bus)
-
- # Connect the L2 cache to the L3 bus
- cpu.l2cache.connectMemSideBus(self.l3bus)
-
- self.l3cache = L3Cache()
- self.l3cache.connectCPUSideBus(self.l3bus)
-
- # Connect the L3 cache to the membus
- self.l3cache.connectMemSideBus(self.membus)
-
- def setupInterrupts(self):
- for cpu in self.cpu:
- # create the interrupt controller CPU and connect to the membus
- cpu.createInterruptController()
-
- # For x86 only, connect interrupts to the memory
- # Note: these are directly connected to the memory bus and
- # not cached
- cpu.interrupts[0].pio = self.membus.mem_side_ports
- cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
- cpu.interrupts[0].int_responder = self.membus.mem_side_ports
-
- # Memory latency: Using the smaller number from [3]: 96ns
- def createMemoryControllersDDR4(self):
- self._createMemoryControllers(8, DDR4_2400_16x4)
-
- def _createMemoryControllers(self, num, cls):
- kernel_controller = self._createKernelMemoryController(cls)
-
- ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
- self.mem_cntrls = [
- MemCtrl(dram = cls(range = ranges[i]),
- port = self.membus.mem_side_ports)
- for i in range(num)
- ] + [kernel_controller]
-
- def _createKernelMemoryController(self, cls):
- return MemCtrl(dram = cls(range = self.mem_ranges[0]),
- port = self.membus.mem_side_ports)
-
- def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
- from math import log
- bits = int(log(num, 2))
- if 2**bits != num:
- m5.fatal("Non-power of two number of memory controllers")
-
- intlv_bits = bits
- ranges = [
- AddrRange(start=rng.start,
- end=rng.end,
- intlvHighBit = intlv_low_bit + intlv_bits - 1,
- xorHighBit = xor_low_bit + intlv_bits - 1,
- intlvBits = intlv_bits,
- intlvMatch = i)
- for i in range(num)
- ]
-
- return ranges
-
- def initFS(self, membus, cpus):
- self.pc = Pc()
- self.workload = X86FsLinux()
- # Constants similar to x86_traits.hh
- IO_address_space_base = 0x8000000000000000
- pci_config_address_space_base = 0xc000000000000000
- interrupts_address_space_base = 0xa000000000000000
- APIC_range_size = 1 << 12
-
- # North Bridge
- self.iobus = IOXBar()
- self.bridge = Bridge(delay='50ns')
- self.bridge.mem_side_port = self.iobus.cpu_side_ports
- self.bridge.cpu_side_port = membus.mem_side_ports
- # Allow the bridge to pass through:
- # 1) kernel configured PCI device memory map address: address range
- # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
- # 2) the bridge to pass through the IO APIC (two pages, already
- # contained in 1),
- # 3) everything in the IO address range up to the local APIC, and
- # 4) then the entire PCI address space and beyond.
- self.bridge.ranges = \
- [
- AddrRange(0xC0000000, 0xFFFF0000),
- AddrRange(IO_address_space_base,
- interrupts_address_space_base - 1),
- AddrRange(pci_config_address_space_base,
- Addr.max)
- ]
-
- # Create a bridge from the IO bus to the memory bus to allow access
- # to the local APIC (two pages)
- self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
- self.apicbridge.mem_side_port = membus.cpu_side_ports
- self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
- interrupts_address_space_base +
- cpus * APIC_range_size
- - 1)]
-
- # connect the io bus
- self.pc.attachIO(self.iobus)
-
- # Add a tiny cache to the IO bus.
- # This cache is required for the classic memory model for coherence
- self.iocache = Cache(assoc=8,
- tag_latency = 50,
- data_latency = 50,
- response_latency = 50,
- mshrs = 20,
- size = '1kB',
- tgts_per_mshr = 12,
- addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.mem_side_ports
- self.iocache.mem_side = self.membus.cpu_side_ports
-
- ###############################################
-
- # Add in a Bios information structure.
- self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
-
- # Set up the Intel MP table
- base_entries = []
- ext_entries = []
- for i in range(cpus):
- bp = X86IntelMPProcessor(
- local_apic_id = i,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = (i ==0))
- base_entries.append(bp)
- io_apic = X86IntelMPIOAPIC(
- id = cpus,
- version = 0x11,
- enable = True,
- address = 0xfec00000)
- self.pc.south_bridge.io_apic.apic_id = io_apic.id
- base_entries.append(io_apic)
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
- base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
- base_entries.append(isa_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=1,
- subtractive_decode=True, parent_bus=0)
- ext_entries.append(connect_busses)
- pci_dev4_inta = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0 + (4 << 2),
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 16)
- base_entries.append(pci_dev4_inta)
- def assignISAInt(irq, apicPin):
- assign_8259_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- base_entries.append(assign_8259_to_apic)
- assign_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 1,
- source_bus_irq = irq,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = apicPin)
- base_entries.append(assign_to_apic)
- assignISAInt(0, 2)
- assignISAInt(1, 1)
- for i in range(3, 15):
- assignISAInt(i, i)
- self.workload.intel_mp_table.base_entries = base_entries
- self.workload.intel_mp_table.ext_entries = ext_entries
-
- entries = \
- [
- # Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '639kB', range_type = 1),
- X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
- # Mark the rest of physical memory as available
- X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
- range_type = 1),
- ]
- # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which
- # force IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests
- # to this specific range can pass though bridge to iobus.
- entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
- size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
- range_type=2))
-
- # Reserve the last 16kB of the 32-bit address space for m5ops
- entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
- range_type=2))
-
- # Add the rest of memory. This is where all the actual data is
- entries.append(X86E820Entry(addr = self.mem_ranges[-1].start,
- size='%dB' % (self.mem_ranges[-1].size()),
- range_type=1))
-
- self.workload.e820_table.entries = entries
diff --git a/src/spec-2017/disk-image/spec-2017/runscript.sh b/src/spec-2017/disk-image/spec-2017/runscript.sh
index 922af4f..a3b210f 100644
--- a/src/spec-2017/disk-image/spec-2017/runscript.sh
+++ b/src/spec-2017/disk-image/spec-2017/runscript.sh
@@ -19,7 +19,7 @@
# run the commands
read -r workload size m5filespath < workloads
- runcpu --size $size --iterations 1 --config myconfig.x86.cfg --noreportable --nobuild $workload
+ runcpu --size $size --iterations 1 --config myconfig.x86.cfg --define gcc_dir="/usr" --noreportable --nobuild $workload
m5 exit
# copy the SPEC result files to host
diff --git a/src/boot-exit/.gitignore b/src/x86-ubuntu/.gitignore
similarity index 100%
rename from src/boot-exit/.gitignore
rename to src/x86-ubuntu/.gitignore
diff --git a/src/boot-exit/README.md b/src/x86-ubuntu/README.md
similarity index 66%
rename from src/boot-exit/README.md
rename to src/x86-ubuntu/README.md
index 118b7ac..d1f6f08 100644
--- a/src/boot-exit/README.md
+++ b/src/x86-ubuntu/README.md
@@ -1,31 +1,32 @@
---
-title: Linux boot-exit image
+title: Linux x86-ubuntu image
tags:
- x86
- fullsystem
layout: default
-permalink: resources/boot-exit
+permalink: resources/x86-ubuntu
shortdoc: >
- Resources to build a disk image and run "boot-exit" test.
+ Resources to build a generic x86-ubuntu disk image and run a "boot-exit" test.
author: ["Ayaz Akram"]
---
-This document provides instructions to create the "boot-exit" image, the Linux kernel binaries, and also points to the gem5 configuration files needed to run the boot.
-The boot-exit disk image is based on Ubuntu 18.04 and has its `.bashrc` file modified in such a way that the guest OS terminates the simulation (using the `m5 exit` instruction) as soon as the system boots.
+This document provides instructions to create the "x86-ubuntu" image, the Linux kernel binaries, and also points to the gem5 configuration files needed to run the boot.
+The x86-ubuntu disk image is based on Ubuntu 18.04 and has its `.bashrc` file modified in such a way that it executes a script passed from the gem5 configuration files (using the `m5 readfile` instruction).
+The boot-exit test passes a script that causes the guest OS to terminate the simulation (using the `m5 exit` instruction) as soon as the system boots.
We assume the following directory structure while following the instructions in this README file:
```
-boot-exit/
+x86-ubuntu/
|___ gem5/ # gem5 source code (to be cloned here)
|
|___ disk-image/
| |___ build.sh # the script downloading packer binary and building the disk image
| |___ shared/ # Auxiliary files needed for disk creation
- | |___ boot-exit/
- | |___ boot-exit-image/ # Will be created once the disk is generated
- | | |___ boot-exit # The generated disk image
- | |___ boot-exit.json # The Packer script
+ | |___ x86-ubuntu/
+ | |___ x86-ubuntu-image/ # Will be created once the disk is generated
+ | | |___ x86-ubuntu # The generated disk image
+ | |___ x86-ubuntu.json # The Packer script
| |___ exit.sh # Exits the simulated guest upon booting
| |___ post-installation.sh # Moves exit.sh to guest's .bashrc
|
@@ -41,7 +42,7 @@
## Disk Image
-Assuming that you are in the `src/boot-exit/` directory (the directory containing this README), first build `m5` (which is needed to create the disk image):
+Assuming that you are in the `src/x86-ubuntu/` directory (the directory containing this README), first build `m5` (which is needed to create the disk image):
```sh
git clone https://gem5.googlesource.com/public/gem5
@@ -49,14 +50,14 @@
scons build/x86/out/m5
```
-Next (within the `src/boot-exit/` directory),
+Next (within the `src/x86-ubuntu/` directory),
```sh
cd disk-image
./build.sh # the script downloading packer binary and building the disk image
```
-If you see errors or warnings from `packer validate` you can modify the file `disk-image/boot-exit/boot-exit.json` to update the file.
+If you see errors or warnings from `packer validate` you can modify the file `disk-image/x86-ubuntu/x86-ubuntu.json` to update the file.
Specifically, you may see the following error.
```
@@ -69,7 +70,7 @@
```
In this case, the `gem5` directory is in a different location than when this script was written.
-You can update the following line in the `boot-exit.json` file.
+You can update the following line in the `x86-ubuntu.json` file.
```
"destination": "/home/gem5/",
@@ -78,8 +79,8 @@
"type": "file"
```
-Once this process succeeds, the disk image can be found on `boot-exit/boot-exit-image/boot-exit`.
-A disk image already created following the above instructions can be found, gzipped, [here](http://dist.gem5.org/dist/v21-1/images/x86/ubuntu-18-04/boot-exit.img.gz).
+Once this process succeeds, the disk image can be found on `x86-ubuntu/x86-ubuntu-image/x86-ubuntu`.
+A disk image already created following the above instructions can be found, gzipped, [here](http://dist.gem5.org/dist/v21-1/images/x86/ubuntu-18-04/x86-ubuntu.img.gz).
## gem5 Run Scripts
diff --git a/src/boot-exit/configs/run_exit.py b/src/x86-ubuntu/configs/run_exit.py
similarity index 99%
rename from src/boot-exit/configs/run_exit.py
rename to src/x86-ubuntu/configs/run_exit.py
index 0eadcde..2bacc67 100755
--- a/src/boot-exit/configs/run_exit.py
+++ b/src/x86-ubuntu/configs/run_exit.py
@@ -27,8 +27,9 @@
"""
"""
-import time
import argparse
+import os
+import time
import m5
import m5.ticks
diff --git a/src/boot-exit/configs/system/MESI_Two_Level.py b/src/x86-ubuntu/configs/system/MESI_Two_Level.py
similarity index 100%
rename from src/boot-exit/configs/system/MESI_Two_Level.py
rename to src/x86-ubuntu/configs/system/MESI_Two_Level.py
diff --git a/src/boot-exit/configs/system/MI_example_caches.py b/src/x86-ubuntu/configs/system/MI_example_caches.py
similarity index 100%
rename from src/boot-exit/configs/system/MI_example_caches.py
rename to src/x86-ubuntu/configs/system/MI_example_caches.py
diff --git a/src/boot-exit/configs/system/MOESI_CMP_directory.py b/src/x86-ubuntu/configs/system/MOESI_CMP_directory.py
similarity index 100%
rename from src/boot-exit/configs/system/MOESI_CMP_directory.py
rename to src/x86-ubuntu/configs/system/MOESI_CMP_directory.py
diff --git a/src/boot-exit/configs/system/__init__.py b/src/x86-ubuntu/configs/system/__init__.py
similarity index 100%
rename from src/boot-exit/configs/system/__init__.py
rename to src/x86-ubuntu/configs/system/__init__.py
diff --git a/src/boot-exit/configs/system/caches.py b/src/x86-ubuntu/configs/system/caches.py
similarity index 100%
rename from src/boot-exit/configs/system/caches.py
rename to src/x86-ubuntu/configs/system/caches.py
diff --git a/src/boot-exit/configs/system/fs_tools.py b/src/x86-ubuntu/configs/system/fs_tools.py
similarity index 100%
rename from src/boot-exit/configs/system/fs_tools.py
rename to src/x86-ubuntu/configs/system/fs_tools.py
diff --git a/src/boot-exit/configs/system/ruby_system.py b/src/x86-ubuntu/configs/system/ruby_system.py
similarity index 100%
rename from src/boot-exit/configs/system/ruby_system.py
rename to src/x86-ubuntu/configs/system/ruby_system.py
diff --git a/src/boot-exit/configs/system/system.py b/src/x86-ubuntu/configs/system/system.py
similarity index 100%
rename from src/boot-exit/configs/system/system.py
rename to src/x86-ubuntu/configs/system/system.py
diff --git a/src/boot-exit/disk-image/build.sh b/src/x86-ubuntu/disk-image/build.sh
similarity index 100%
rename from src/boot-exit/disk-image/build.sh
rename to src/x86-ubuntu/disk-image/build.sh
diff --git a/src/boot-exit/disk-image/shared/preseed.cfg b/src/x86-ubuntu/disk-image/shared/preseed.cfg
similarity index 100%
rename from src/boot-exit/disk-image/shared/preseed.cfg
rename to src/x86-ubuntu/disk-image/shared/preseed.cfg
diff --git a/src/boot-exit/disk-image/shared/serial-getty@.service b/src/x86-ubuntu/disk-image/shared/serial-getty@.service
similarity index 100%
rename from src/boot-exit/disk-image/shared/serial-getty@.service
rename to src/x86-ubuntu/disk-image/shared/serial-getty@.service
diff --git a/src/boot-exit/disk-image/boot-exit/exit.sh b/src/x86-ubuntu/disk-image/x86-ubuntu/exit.sh
similarity index 100%
rename from src/boot-exit/disk-image/boot-exit/exit.sh
rename to src/x86-ubuntu/disk-image/x86-ubuntu/exit.sh
diff --git a/src/x86-ubuntu/disk-image/x86-ubuntu/gem5_init.sh b/src/x86-ubuntu/disk-image/x86-ubuntu/gem5_init.sh
new file mode 100755
index 0000000..bbdbbfb
--- /dev/null
+++ b/src/x86-ubuntu/disk-image/x86-ubuntu/gem5_init.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+
+# Copyright (c) 2021 The University of Texas at Austin.
+# SPDX-License-Identifier: BSD 3-Clause
+
+echo "Starting gem5 init... reading run script file."
+if ! m5 readfile > /tmp/script; then
+ echo "Failed to run m5 readfile, exiting!"
+ rm -f /tmp/script
+ if ! m5 exit; then
+ # Useful for booting the disk image in (e.g.,) qemu for debugging
+ echo "m5 exit failed, dropping to shell."
+ /bin/sh
+ fi
+else
+ echo "Running m5 script from /tmp/script"
+ chmod 755 /tmp/script
+ /tmp/script
+ echo "Done running script, exiting."
+ rm -f /tmp/script
+ m5 exit
+fi
diff --git a/src/boot-exit/disk-image/boot-exit/post-installation.sh b/src/x86-ubuntu/disk-image/x86-ubuntu/post-installation.sh
similarity index 75%
rename from src/boot-exit/disk-image/boot-exit/post-installation.sh
rename to src/x86-ubuntu/disk-image/x86-ubuntu/post-installation.sh
index 5f8bf36..4e013d0 100755
--- a/src/boot-exit/disk-image/boot-exit/post-installation.sh
+++ b/src/x86-ubuntu/disk-image/x86-ubuntu/post-installation.sh
@@ -11,8 +11,9 @@
ln -s /sbin/m5 /sbin/gem5
mv /home/gem5/exit.sh /root/
+mv /home/gem5/gem5_init.sh /root/
-# Add exit script to bashrc
-echo "/root/exit.sh" >> /root/.bashrc
+# Add init script to bashrc
+echo "/root/gem5_init.sh" >> /root/.bashrc
echo 'Post Installation Done'
diff --git a/src/boot-exit/disk-image/boot-exit/boot-exit.json b/src/x86-ubuntu/disk-image/x86-ubuntu/x86-ubuntu.json
similarity index 91%
rename from src/boot-exit/disk-image/boot-exit/boot-exit.json
rename to src/x86-ubuntu/disk-image/x86-ubuntu/x86-ubuntu.json
index 1ad08df..60fee86 100755
--- a/src/boot-exit/disk-image/boot-exit/boot-exit.json
+++ b/src/x86-ubuntu/disk-image/x86-ubuntu/x86-ubuntu.json
@@ -35,7 +35,7 @@
"iso_checksum": "{{ user `iso_checksum_type` }}:{{ user `iso_checksum` }}",
"iso_urls": [ "{{ user `iso_url` }}" ],
"memory": "{{ user `vm_memory`}}",
- "output_directory": "boot-exit/{{ user `image_name` }}-image",
+ "output_directory": "x86-ubuntu/{{ user `image_name` }}-image",
"qemuargs":
[
[ "-cpu", "host" ],
@@ -53,7 +53,12 @@
[
{
"type": "file",
- "source": "boot-exit/exit.sh",
+ "source": "x86-ubuntu/exit.sh",
+ "destination": "/home/gem5/"
+ },
+ {
+ "type": "file",
+ "source": "x86-ubuntu/gem5_init.sh",
"destination": "/home/gem5/"
},
{
@@ -71,7 +76,7 @@
"execute_command": "echo '{{ user `ssh_password` }}' | {{.Vars}} sudo -E -S bash '{{.Path}}'",
"scripts":
[
- "boot-exit/post-installation.sh"
+ "x86-ubuntu/post-installation.sh"
]
}
],
@@ -93,7 +98,7 @@
"ssh_username": "gem5",
"vm_cpus": "16",
"vm_memory": "8192",
- "image_name": "boot-exit"
+ "image_name": "x86-ubuntu"
}
}
