diff --git a/src/npb/configs/system/MESI_Two_Level.py b/src/npb/configs/system/MESI_Two_Level.py
index eac0834..bc72d00 100755
--- a/src/npb/configs/system/MESI_Two_Level.py
+++ b/src/npb/configs/system/MESI_Two_Level.py
@@ -88,7 +88,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 
diff --git a/src/npb/configs/system/MI_example_caches.py b/src/npb/configs/system/MI_example_caches.py
index 907c3f0..cdc8771 100755
--- a/src/npb/configs/system/MI_example_caches.py
+++ b/src/npb/configs/system/MI_example_caches.py
@@ -89,7 +89,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 
diff --git a/src/npb/configs/system/MOESI_CMP_directory.py b/src/npb/configs/system/MOESI_CMP_directory.py
index bf31ab7..1aec746 100755
--- a/src/npb/configs/system/MOESI_CMP_directory.py
+++ b/src/npb/configs/system/MOESI_CMP_directory.py
@@ -92,7 +92,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 
diff --git a/src/spec-2006/configs/system/MESI_Two_Level.py b/src/spec-2006/configs/system/MESI_Two_Level.py
index 0513041..c200b5e 100644
--- a/src/spec-2006/configs/system/MESI_Two_Level.py
+++ b/src/spec-2006/configs/system/MESI_Two_Level.py
@@ -91,7 +91,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 
diff --git a/src/spec-2006/configs/system/MI_example_caches.py b/src/spec-2006/configs/system/MI_example_caches.py
index b8fd7b4..8435924 100644
--- a/src/spec-2006/configs/system/MI_example_caches.py
+++ b/src/spec-2006/configs/system/MI_example_caches.py
@@ -92,7 +92,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 
diff --git a/src/spec-2006/configs/system/MOESI_CMP_directory.py b/src/spec-2006/configs/system/MOESI_CMP_directory.py
index c657df7..ec13fda 100644
--- a/src/spec-2006/configs/system/MOESI_CMP_directory.py
+++ b/src/spec-2006/configs/system/MOESI_CMP_directory.py
@@ -92,7 +92,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]