resources: Remove SimpleOpts from boot-exit
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Change-Id: I18079b3a5d96d0eb4dbbd99261b16d29eda418e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/32336
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/boot-exit/configs/run_exit.py b/src/boot-exit/configs/run_exit.py
index 7e9e6d9..ccea261 100755
--- a/src/boot-exit/configs/run_exit.py
+++ b/src/boot-exit/configs/run_exit.py
@@ -30,53 +30,54 @@
"""
"""
-import errno
-import os
-import sys
import time
+import argparse
import m5
import m5.ticks
from m5.objects import *
-sys.path.append('gem5/configs/common/') # For the next line...
-import SimpleOpts
-
from system import *
-SimpleOpts.set_usage(
- "usage: %prog [options] kernel disk cpu_type mem_sys num_cpus boot_type")
+supported_protocols = ["classic", "MI_example", "MESI_Two_Level",
+ "MOESI_CMP_directory"]
+supported_cpu_types = ['kvm', 'atomic', 'simple', 'o3']
-SimpleOpts.add_option("--allow_listeners", default=False, action="store_true",
- help="Listeners disabled by default")
+def parse_options():
+ parser = argparse.ArgumentParser(description='For use with gem5. Runs a '
+ 'simple system through Linux boot. Expects the disk image to '
+ 'call the simulator exit event after boot. Only works with '
+ 'x86 ISA.')
+ parser.add_argument("--allow_listeners", default=False,
+ action="store_true",
+ help="Listeners disabled by default")
+ parser.add_argument("kernel", help="Path to the kernel binary to boot")
+ parser.add_argument("disk", help="Path to the disk image to boot")
+ parser.add_argument("cpu_type", choices=supported_cpu_types,
+ help="The type of CPU to use in the system")
+ parser.add_argument("mem_sys", choices=supported_protocols,
+ help="Type of memory system or coherence protocol")
+ parser.add_argument("num_cpus", type=int, help="Number of CPU cores")
+ parser.add_argument("boot_type", choices=["init", "systemd"],
+ help="How to boot the kernel. Either to a simple init "
+ "script or all of the way through systemd")
+
+ return parser.parse_args()
if __name__ == "__m5_main__":
- (opts, args) = SimpleOpts.parse_args()
- if len(args) != 6:
- SimpleOpts.print_help()
- m5.fatal("Bad arguments")
-
- kernel, disk, cpu_type, mem_sys, num_cpus, boot_type = args
- num_cpus = int(num_cpus)
+ args = parse_options()
# create the system we are going to simulate
- ruby_protocols = [ "MI_example", "MESI_Two_Level", "MOESI_CMP_directory"]
- if mem_sys == "classic":
- system = MySystem(kernel, disk, cpu_type, num_cpus, opts)
- elif mem_sys in ruby_protocols:
- system = MyRubySystem(kernel, disk, cpu_type, mem_sys, num_cpus, opts)
+ if args.mem_sys == "classic":
+ system = MySystem(args.kernel, args.disk, args.cpu_type, args.num_cpus)
else:
- m5.fatal("Bad option for mem_sys, should be "
- "{}, or 'classic'".format(', '.join(ruby_protocols)))
+ system = MyRubySystem(args.kernel, args.disk, args.cpu_type,
+ args.mem_sys, args.num_cpus)
- if boot_type == "init":
+ if args.boot_type == "init":
# Simply run "exit.sh"
system.workload.command_line += ' init=/root/exit.sh'
- else:
- if boot_type != "systemd":
- SimpleOpts.print_help()
- m5.fatal("Bad option for boot_type. init or systemd.")
# set up the root SimObject and start the simulation
root = Root(full_system = True, system = system)
@@ -88,7 +89,7 @@
root.sim_quantum = int(1e9) # 1 ms
# Required for long-running jobs
- if not opts.allow_listeners:
+ if not args.allow_listeners:
m5.disableAllListeners()
# instantiate all of the objects we've created above
diff --git a/src/boot-exit/configs/system/caches.py b/src/boot-exit/configs/system/caches.py
index 4630cea..abc0b31 100755
--- a/src/boot-exit/configs/system/caches.py
+++ b/src/boot-exit/configs/system/caches.py
@@ -39,21 +39,13 @@
from m5.params import AddrRange, AllMemory, MemorySize
from m5.util.convert import toMemorySize
-import SimpleOpts
-
# Some specific options for caches
# For all options see src/mem/cache/BaseCache.py
class PrefetchCache(Cache):
- SimpleOpts.add_option("--no_prefetchers", default=False,
- action="store_true",
- help="Enable prefectchers on the caches")
-
- def __init__(self, options):
+ def __init__(self):
super(PrefetchCache, self).__init__()
- if not options or options.no_prefetchers:
- return
self.prefetcher = StridePrefetcher()
class L1Cache(PrefetchCache):
@@ -67,9 +59,8 @@
tgts_per_mshr = 20
writeback_clean = True
- def __init__(self, options=None):
- super(L1Cache, self).__init__(options)
- pass
+ def __init__(self):
+ super(L1Cache, self).__init__()
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
@@ -86,14 +77,8 @@
# Set the default size
size = '32kB'
- SimpleOpts.add_option('--l1i_size',
- help="L1 instruction cache size. Default: %s" % size)
-
- def __init__(self, opts=None):
- super(L1ICache, self).__init__(opts)
- if not opts or not opts.l1i_size:
- return
- self.size = opts.l1i_size
+ def __init__(self):
+ super(L1ICache, self).__init__()
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU icache port"""
@@ -105,14 +90,8 @@
# Set the default size
size = '32kB'
- SimpleOpts.add_option('--l1d_size',
- help="L1 data cache size. Default: %s" % size)
-
- def __init__(self, opts=None):
- super(L1DCache, self).__init__(opts)
- if not opts or not opts.l1d_size:
- return
- self.size = opts.l1d_size
+ def __init__(self):
+ super(L1DCache, self).__init__()
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU dcache port"""
@@ -158,42 +137,8 @@
tgts_per_mshr = 12
writeback_clean = True
- SimpleOpts.add_option('--l2_size',
- help="L2 cache size. Default: %s" % size)
-
- def __init__(self, opts=None):
- super(L2Cache, self).__init__(opts)
- if not opts or not opts.l2_size:
- return
- self.size = opts.l2_size
-
- def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
-
- def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
-
-class L3Cache(Cache):
- """Simple L3 Cache bank with default values
- This assumes that the L3 is made up of multiple banks. This cannot
- be used as a standalone L3 cache.
- """
-
- SimpleOpts.add_option('--l3_size', default = '4MB',
- help="L3 cache size. Default: 4MB")
-
- # Default parameters
- assoc = 32
- tag_latency = 40
- data_latency = 40
- response_latency = 10
- mshrs = 256
- tgts_per_mshr = 12
- clusivity = 'mostly_excl'
-
- def __init__(self, opts):
- super(L3Cache, self).__init__()
- self.size = (opts.l3_size)
+ def __init__(self):
+ super(L2Cache, self).__init__()
def connectCPUSideBus(self, bus):
self.cpu_side = bus.master
diff --git a/src/boot-exit/configs/system/ruby_system.py b/src/boot-exit/configs/system/ruby_system.py
index cd25d8d..778743a 100755
--- a/src/boot-exit/configs/system/ruby_system.py
+++ b/src/boot-exit/configs/system/ruby_system.py
@@ -35,9 +35,8 @@
class MyRubySystem(System):
- def __init__(self, kernel, disk, cpu_type, mem_sys, num_cpus, opts):
+ def __init__(self, kernel, disk, cpu_type, mem_sys, num_cpus):
super(MyRubySystem, self).__init__()
- self._opts = opts
self._host_parallel = cpu_type == "kvm"
diff --git a/src/boot-exit/configs/system/system.py b/src/boot-exit/configs/system/system.py
index 909859c..58e37b8 100755
--- a/src/boot-exit/configs/system/system.py
+++ b/src/boot-exit/configs/system/system.py
@@ -35,9 +35,8 @@
class MySystem(System):
- def __init__(self, kernel, disk, cpu_type, num_cpus, opts):
+ def __init__(self, kernel, disk, cpu_type, num_cpus):
super(MySystem, self).__init__()
- self._opts = opts
self._host_parallel = cpu_type == "kvm"
@@ -135,8 +134,8 @@
cpu.l2bus = L2XBar()
# Create an L1 instruction and data cache
- cpu.icache = L1ICache(self._opts)
- cpu.dcache = L1DCache(self._opts)
+ cpu.icache = L1ICache()
+ cpu.dcache = L1DCache()
cpu.mmucache = MMUCache()
# Connect the instruction and data caches to the CPU
@@ -150,7 +149,7 @@
cpu.mmucache.connectBus(cpu.l2bus)
# Create an L2 cache and connect it to the l2bus
- cpu.l2cache = L2Cache(self._opts)
+ cpu.l2cache = L2Cache()
cpu.l2cache.connectCPUSideBus(cpu.l2bus)
# Connect the L2 cache to the L3 bus