resources: Fix spec-2017 configs
gem5 v21 requires using mmu.connectWalkerPorts() to connect the
caches and the tlb's.
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I0d2d503036a3af9c70e14f0485a805554032e1d2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/46219
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
diff --git a/src/spec-2017/configs/system/caches.py b/src/spec-2017/configs/system/caches.py
index f15b741..9932ecf 100644
--- a/src/spec-2017/configs/system/caches.py
+++ b/src/spec-2017/configs/system/caches.py
@@ -119,8 +119,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.mem_side_ports
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.cpu_side_ports = tlb.walker.port
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
