diff --git a/src/spec-2017/configs/system/caches.py b/src/spec-2017/configs/system/caches.py
index f15b741..9932ecf 100644
--- a/src/spec-2017/configs/system/caches.py
+++ b/src/spec-2017/configs/system/caches.py
@@ -119,8 +119,8 @@
         """
         self.mmubus = L2XBar()
         self.cpu_side = self.mmubus.mem_side_ports
-        for tlb in [cpu.itb, cpu.dtb]:
-            self.mmubus.cpu_side_ports = tlb.walker.port
+        cpu.mmu.connectWalkerPorts(
+            self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
 
     def connectBus(self, bus):
         """Connect this cache to a memory-side bus"""