diff --git a/README.md b/README.md
index 7cd447b..9797c8a 100644
--- a/README.md
+++ b/README.md
@@ -194,6 +194,17 @@
 Contains scripts to create a disk image and to run SPEC-2006 tests on gem5.
 Instructions on how to use these scripts can be found here `src/spec2006-tests/README.md`.
 
+# Resource: GAP Benchmark Suite (GAPBS) tests
+
+[GAPBS](http://gap.cs.berkeley.edu/benchmark.html) is a graph processing benchmark suite and it contains 6 kernels: Breadth-First Search, PageRank, Connected Components, Betweenness Centrality, Single-Source Shortest Paths, and Triangle Counting.
+
+`src/gapbs` contains resources to build a GAPBS disk image which may
+be used to run the benchmark on gem5 X86 simulations.
+`src/gapbs/README.md` contains build and usage instructions.
+
+The pre-built GAPBS disk image can be found here:
+<http://dist.gem5.org/images/x86/ubuntu-18-04/gapbs>.
+
 # Licensing
 
 Each project under the `src` is under a different license. Before using
@@ -210,3 +221,5 @@
 * **spec2006-tests**: SPEC-2006 requires purchase of benchmark suite from
 [SPEC](https://www.spec.org/cpu2006/) thus, it cannot be freely distributed.
 Consult individual copyright notices of source files in `src/spec2006-tests`.
+* **gapbs**: Consult individual copyright notices of source files in
+`src/gapbs`.
diff --git a/src/gapbs/README.md b/src/gapbs/README.md
new file mode 100644
index 0000000..12a3069
--- /dev/null
+++ b/src/gapbs/README.md
@@ -0,0 +1,52 @@
+# GAP Benchmark Suite (GAPBS) tests
+This document provides instructions to create a GAP Benchmarks Suite (GAPBS) disk image, which, along with provided configuration scripts, may be used to run GAPBS within gem5 simulations.
+
+A pre-build disk image, for X86, can be found here: <http://dist.gem5.org/images/x86/ubuntu-18-04/gapbs>.
+
+## Building the Disk Image
+Assuming that you are in the `src/gapbs/` directory, first create `m5` (which is needed to create the disk image):
+
+```sh
+git clone https://gem5.googlesource.com/public/gem5
+cd gem5/util/m5
+scons build/x86/out/m5
+```
+
+To create the disk image you need to add the packer binary in the disk-image directory:
+
+```sh
+cd disk-image/
+wget https://releases.hashicorp.com/packer/1.4.3/packer_1.4.3_linux_amd64.zip   # (if packer is not already installed)
+unzip packer_1.4.3_linux_amd64.zip # (if packer is not already installed)
+./packer validate gapbs/gapbs.json
+./packer build gapbs/gapbs.json
+```
+
+After this process succeeds, the disk image can be found on the `src/gapbs/disk-image/gapbs-image/gapbs`.
+
+## gem5 Configuration Scripts
+
+gem5 scripts which configure the system and run the simulation are available in `configs/`.
+The main script `run_gapbs.py` expects following arguments:
+
+**--kernel** : path to the Linux kernel. GAPBS has been tested with [vmlinux-5.2.3](http://dist.gem5.org/kernels/x86/static/vmlinux-5.2.3).
+
+**--disk** : Path to the disk image.
+
+**--cpu\_type** : Cpu model (`kvm`, `atomic`, `simple`, `o3`).
+
+**--num\_cpus** : Number of cpu cores.
+
+**--mem\_sys** : Memory model (`classic`, `MI_example`, `MESI_Two_Level`).
+
+**--benchmark** : The graph workload (`cc`, `bc`, `bfs`, `tc`, `pr`, `sssp`).
+
+**--synthetic** : Type of graph (if synthetic graph 1, if real world graph 0)
+
+**--graph** : Size of graph (if synthetic then number of nodes, else name of the graph )
+
+Example usage:
+
+```sh
+build/X86/gem5.opt configs/run_gapbs.py --kernel [path to the linux kernel] --disk [path to the disk image] --cpu-type kvm --num_cpus 1 --mem_sys classic --benchmark cc --synthetic 1 --graph 20
+```
diff --git a/src/gapbs/configs/run_gapbs.py b/src/gapbs/configs/run_gapbs.py
new file mode 100644
index 0000000..4e27261
--- /dev/null
+++ b/src/gapbs/configs/run_gapbs.py
@@ -0,0 +1,154 @@
+#Copyright (c) 2020 The Regents of the University of California.
+#All Rights Reserved
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+
+""" Script to run GAP Benchmark suites workloads.
+    The workloads have two modes: synthetic and real graphs.
+"""
+
+import sys
+import time
+
+import m5
+import m5.ticks
+from m5.objects import *
+
+import argparse
+
+from system import *
+
+def parse_arguments():
+    parser = argparse.ArgumentParser(description=
+                                "gem5 config file to run GAPBS")
+    parser.add_argument("kernel", type = str, help = "Path to vmlinux")
+    parser.add_argument("disk", type = str,
+                        help = "Path to the disk image containing GAPBS")
+    parser.add_argument("cpu_type", type = str, help = "Name of the detailed CPU")
+    parser.add_argument("num_cpus", type = str, help = "Number of CPUs")
+    parser.add_argument("mem_sys", type = str,
+                        help = "Memory model, Classic or MI_example")
+    parser.add_argument("benchmark", type = str,
+                        help = "Name of the GAPBS")
+    parser.add_argument("synthetic", type = int,
+                        help = "1 for synthetic graph, 0 for real graph")
+    parser.add_argument("graph", type = str,
+                        help = "synthetic=1: integer number. synthetic=0: graph")
+
+    return parser.parse_args()
+
+
+def writeBenchScript(dir, benchmark_name, size, synthetic):
+    """
+    This method creates a script in dir which will be eventually
+    passed to the simulated system (to run a specific benchmark
+    at bootup).
+    """
+    input_file_name = '{}/run_{}_{}'.format(dir, benchmark_name, size)
+    if (synthetic):
+        with open(input_file_name,"w") as f:
+           f.write('./{} -g {}\n'.format(benchmark_name, size))
+    elif(synthetic==0):
+        with open(input_file_name,"w") as f:
+           f.write('./{} -sf {}'.format(benchmark_name, size))
+
+    return input_file_name
+
+if __name__ == "__m5_main__":
+    args = parse_arguments()
+
+
+    kernel = args.kernel
+    disk = args.disk
+    cpu_type = args.cpu_type
+    num_cpus = int(args.num_cpus)
+    mem_sys = args.mem_sys
+    benchmark_name =args.benchmark
+    benchmark_size = args.graph
+    synthetic = args.synthetic
+
+
+
+    if (mem_sys == "classic"):
+        system = MySystem(kernel, disk, cpu_type, num_cpus)
+    elif (mem_sys == "MI_example" or "MESI_Two_Level"):
+        system = MyRubySystem(kernel, disk, cpu_type, mem_sys, num_cpus)
+
+
+
+    output_dir = os.path.join(m5.options.outdir, "speclogs")
+
+    # For workitems to work correctly
+    # This will cause the simulator to exit simulation when the first work
+    # item is reached and when the first work item is finished.
+    system.work_begin_exit_count = 1
+    system.work_end_exit_count = 1
+
+    # Read in the script file passed in via an option.
+    # This file gets read and executed by the simulated system after boot.
+    # Note: The disk image needs to be configured to do this.
+
+    system.readfile = writeBenchScript(m5.options.outdir, benchmark_name,
+                                       benchmark_size, synthetic)
+
+    # set up the root SimObject and start the simulation
+    root = Root(full_system = True, system = system)
+
+    if system.getHostParallel():
+        # Required for running kvm on multiple host cores.
+        # Uses gem5's parallel event queue feature
+        # Note: The simulator is quite picky about this number!
+        root.sim_quantum = int(1e9) # 1 ms
+
+    # instantiate all of the objects we've created above
+    m5.instantiate()
+
+    print("Running the simulation")
+    exit_event = m5.simulate()
+    if exit_event.getCause() == "work started count reach":
+        m5.stats.reset()
+        start_tick = m5.curTick()
+        start_insts = system.totalInsts()
+        # switching to atomic cpu if argument cpu == atomic
+        if cpu_type != 'kvm':
+            system.switchCpus(system.cpu, system.timingCpu)
+            print("Switch to detailed cpu model")
+    else:
+        print("ROI is not annotated!")
+        print('Exiting @ tick {} because {}'
+            .format(m5.curTick(), exit_event.getCause()))
+        exit()
+
+    exit_event = m5.simulate()
+
+    if exit_event.getCause() == "work items exit count reached":
+        m5.stats.dump()
+        m5.stats.reset()
+    exit_event = m5.simulate()
+    m5.stats.dump()
+    m5.stats.reset()
+    print('Exiting @ tick {} because {}'
+        .format(m5.curTick(), exit_event.getCause()))
diff --git a/src/gapbs/configs/system/MESI_Two_Level.py b/src/gapbs/configs/system/MESI_Two_Level.py
new file mode 100644
index 0000000..bb07456
--- /dev/null
+++ b/src/gapbs/configs/system/MESI_Two_Level.py
@@ -0,0 +1,338 @@
+#Copyright (c) 2020 The Regents of the University of California.
+#All Rights Reserved
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+
+""" This file creates a set of Ruby caches for the MESI TWO Level protocol
+This protocol models two level cache hierarchy. The L1 cache is split into
+instruction and data cache.
+This system support the memory size of up to 3GB.
+"""
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+import math
+
+from m5.defines import buildEnv
+from m5.util import fatal, panic
+
+from m5.objects import *
+
+class MESITwoLevelCache(RubySystem):
+
+    def __init__(self):
+        if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
+            fatal("This system assumes MESI_Two_Level!")
+
+        super(MESITwoLevelCache, self).__init__()
+
+        self._numL2Caches = 8
+
+    def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
+        """Set up the Ruby cache subsystem. Note: This can't be done in the
+           constructor because many of these items require a pointer to the
+           ruby system (self). This causes infinite recursion in initialize()
+           if we do this in the __init__.
+        """
+        # Ruby's global network.
+        self.network = MyNetwork(self)
+
+        # MESI_Two_Level example uses 5 virtual networks
+        self.number_of_virtual_networks = 5
+        self.network.number_of_virtual_networks = 5
+
+        # There is a single global list of all of the controllers to make it
+        # easier to connect everything to the global network. This can be
+        # customized depending on the topology/network requirements.
+        # L1 caches are private to a core, hence there are one L1 cache per CPU core.
+        # The number of L2 caches are dependent to the architecture.
+        self.controllers = \
+            [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
+            [L2Cache(system, self, self._numL2Caches) for num in range(self._numL2Caches)] + \
+            [DirController(self, system.mem_ranges, mem_ctrls)] + \
+            [DMAController(self) for i in range(len(dma_ports))]
+
+        # Create one sequencer per CPU and dma controller.
+        # Sequencers for other controllers can be here here.
+        self.sequencers = [RubySequencer(version = i,
+                                # I/D cache is combined and grab from ctrl
+                                icache = self.controllers[i].L1Icache,
+                                dcache = self.controllers[i].L1Dcache,
+                                clk_domain = self.controllers[i].clk_domain,
+                                pio_master_port = iobus.slave,
+                                mem_master_port = iobus.slave,
+                                pio_slave_port = iobus.master
+                                ) for i in range(len(cpus))] + \
+                          [DMASequencer(version = i,
+                                        slave = port)
+                            for i,port in enumerate(dma_ports)
+                          ]
+
+        for i,c in enumerate(self.controllers[:len(cpus)]):
+            c.sequencer = self.sequencers[i]
+
+        #Connecting the DMA sequencer to DMA controller
+        for i,d in enumerate(self.controllers[-len(dma_ports):]):
+            i += len(cpus)
+            d.dma_sequencer = self.sequencers[i]
+
+        self.num_of_sequencers = len(self.sequencers)
+
+        # Create the network and connect the controllers.
+        # NOTE: This is quite different if using Garnet!
+        self.network.connectControllers(self.controllers)
+        self.network.setup_buffers()
+
+        # Set up a proxy port for the system_port. Used for load binaries and
+        # other functional-only things.
+        self.sys_port_proxy = RubyPortProxy()
+        system.system_port = self.sys_port_proxy.slave
+        self.sys_port_proxy.pio_master_port = iobus.slave
+
+        # Connect the cpu's cache, interrupt, and TLB ports to Ruby
+        for i,cpu in enumerate(cpus):
+            cpu.icache_port = self.sequencers[i].slave
+            cpu.dcache_port = self.sequencers[i].slave
+            isa = buildEnv['TARGET_ISA']
+            if isa == 'x86':
+                cpu.interrupts[0].pio = self.sequencers[i].master
+                cpu.interrupts[0].int_master = self.sequencers[i].slave
+                cpu.interrupts[0].int_slave = self.sequencers[i].master
+            if isa == 'x86' or isa == 'arm':
+                cpu.itb.walker.port = self.sequencers[i].slave
+                cpu.dtb.walker.port = self.sequencers[i].slave
+
+
+class L1Cache(L1Cache_Controller):
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+    def __init__(self, system, ruby_system, cpu, num_l2Caches):
+        """Creating L1 cache controller. Consist of both instruction
+           and data cache. The size of data cache is 512KB and
+           8-way set associative. The instruction cache is 32KB,
+           2-way set associative.
+        """
+        super(L1Cache, self).__init__()
+
+        self.version = self.versionCount()
+        block_size_bits = int(math.log(system.cache_line_size, 2))
+        l1i_size = '32kB'
+        l1i_assoc = '2'
+        l1d_size = '512kB'
+        l1d_assoc = '8'
+        # This is the cache memory object that stores the cache data and tags
+        self.L1Icache = RubyCache(size = l1i_size,
+                                assoc = l1i_assoc,
+                                start_index_bit = block_size_bits ,
+                                is_icache = True)
+        self.L1Dcache = RubyCache(size = l1d_size,
+                            assoc = l1d_assoc,
+                            start_index_bit = block_size_bits,
+                            is_icache = False)
+        self.l2_select_num_bits = int(math.log(num_l2Caches , 2))
+        self.clk_domain = cpu.clk_domain
+        self.prefetcher = RubyPrefetcher()
+        self.send_evictions = self.sendEvicts(cpu)
+        self.transitions_per_cycle = 4
+        self.enable_prefetch = False
+        self.ruby_system = ruby_system
+        self.connectQueues(ruby_system)
+
+    def getBlockSizeBits(self, system):
+        bits = int(math.log(system.cache_line_size, 2))
+        if 2**bits != system.cache_line_size.value:
+            panic("Cache line size not a power of 2!")
+        return bits
+
+    def sendEvicts(self, cpu):
+        """True if the CPU model or ISA requires sending evictions from caches
+           to the CPU. Two scenarios warrant forwarding evictions to the CPU:
+           1. The O3 model must keep the LSQ coherent with the caches
+           2. The x86 mwait instruction is built on top of coherence
+           3. The local exclusive monitor in ARM systems
+        """
+        if type(cpu) is DerivO3CPU or \
+           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
+            return True
+        return False
+
+    def connectQueues(self, ruby_system):
+        """Connect all of the queues for this controller.
+        """
+        self.mandatoryQueue = MessageBuffer()
+        self.requestFromL1Cache = MessageBuffer()
+        self.requestFromL1Cache.master = ruby_system.network.slave
+        self.responseFromL1Cache = MessageBuffer()
+        self.responseFromL1Cache.master = ruby_system.network.slave
+        self.unblockFromL1Cache = MessageBuffer()
+        self.unblockFromL1Cache.master = ruby_system.network.slave
+
+        self.optionalQueue = MessageBuffer()
+
+        self.requestToL1Cache = MessageBuffer()
+        self.requestToL1Cache.slave = ruby_system.network.master
+        self.responseToL1Cache = MessageBuffer()
+        self.responseToL1Cache.slave = ruby_system.network.master
+
+class L2Cache(L2Cache_Controller):
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+    def __init__(self, system, ruby_system, num_l2Caches):
+
+        super(L2Cache, self).__init__()
+
+        self.version = self.versionCount()
+        # This is the cache memory object that stores the cache data and tags
+        self.L2cache = RubyCache(size = '1 MB',
+                                assoc = 16,
+                                start_index_bit = self.getBlockSizeBits(system, num_l2Caches))
+
+        self.transitions_per_cycle = '4'
+        self.ruby_system = ruby_system
+        self.connectQueues(ruby_system)
+
+    def getBlockSizeBits(self, system, num_l2caches):
+        l2_bits = int(math.log(num_l2caches, 2))
+        bits = int(math.log(system.cache_line_size, 2)) + l2_bits
+        return bits
+
+
+    def connectQueues(self, ruby_system):
+        """Connect all of the queues for this controller.
+        """
+        self.DirRequestFromL2Cache = MessageBuffer()
+        self.DirRequestFromL2Cache.master = ruby_system.network.slave
+        self.L1RequestFromL2Cache = MessageBuffer()
+        self.L1RequestFromL2Cache.master = ruby_system.network.slave
+        self.responseFromL2Cache = MessageBuffer()
+        self.responseFromL2Cache.master = ruby_system.network.slave
+        self.unblockToL2Cache = MessageBuffer()
+        self.unblockToL2Cache.slave = ruby_system.network.master
+        self.L1RequestToL2Cache = MessageBuffer()
+        self.L1RequestToL2Cache.slave = ruby_system.network.master
+        self.responseToL2Cache = MessageBuffer()
+        self.responseToL2Cache.slave = ruby_system.network.master
+
+
+
+class DirController(Directory_Controller):
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+    def __init__(self, ruby_system, ranges, mem_ctrls):
+        """ranges are the memory ranges assigned to this controller.
+        """
+        if len(mem_ctrls) > 1:
+            panic("This cache system can only be connected to one mem ctrl")
+        super(DirController, self).__init__()
+        self.version = self.versionCount()
+        self.addr_ranges = ranges
+        self.ruby_system = ruby_system
+        self.directory = RubyDirectoryMemory()
+        # Connect this directory to the memory side.
+        self.memory = mem_ctrls[0].port
+        self.connectQueues(ruby_system)
+
+    def connectQueues(self, ruby_system):
+        self.requestToDir = MessageBuffer()
+        self.requestToDir.slave = ruby_system.network.master
+        self.responseToDir = MessageBuffer()
+        self.responseToDir.slave = ruby_system.network.master
+        self.responseFromDir = MessageBuffer()
+        self.responseFromDir.master = ruby_system.network.slave
+        self.requestToMemory = MessageBuffer()
+        self.responseFromMemory = MessageBuffer()
+
+class DMAController(DMA_Controller):
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+    def __init__(self, ruby_system):
+        super(DMAController, self).__init__()
+        self.version = self.versionCount()
+        self.ruby_system = ruby_system
+        self.connectQueues(ruby_system)
+
+    def connectQueues(self, ruby_system):
+        self.mandatoryQueue = MessageBuffer()
+        self.responseFromDir = MessageBuffer(ordered = True)
+        self.responseFromDir.slave = ruby_system.network.master
+        self.requestToDir = MessageBuffer()
+        self.requestToDir.master = ruby_system.network.slave
+
+
+class MyNetwork(SimpleNetwork):
+    """A simple point-to-point network. This doesn't not use garnet.
+    """
+
+    def __init__(self, ruby_system):
+        super(MyNetwork, self).__init__()
+        self.netifs = []
+        self.ruby_system = ruby_system
+
+    def connectControllers(self, controllers):
+        """Connect all of the controllers to routers and connec the routers
+           together in a point-to-point network.
+        """
+        # Create one router/switch per controller in the system
+        self.routers = [Switch(router_id = i) for i in range(len(controllers))]
+
+        # Make a link from each controller to the router. The link goes
+        # externally to the network.
+        self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
+                                        int_node=self.routers[i])
+                          for i, c in enumerate(controllers)]
+
+        # Make an "internal" link (internal to the network) between every pair
+        # of routers.
+        link_count = 0
+        self.int_links = []
+        for ri in self.routers:
+            for rj in self.routers:
+                if ri == rj: continue # Don't connect a router to itself!
+                link_count += 1
+                self.int_links.append(SimpleIntLink(link_id = link_count,
+                                                    src_node = ri,
+                                                    dst_node = rj))
diff --git a/src/gapbs/configs/system/MI_example_caches.py b/src/gapbs/configs/system/MI_example_caches.py
new file mode 100644
index 0000000..2a7e975
--- /dev/null
+++ b/src/gapbs/configs/system/MI_example_caches.py
@@ -0,0 +1,279 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" This file creates a set of Ruby caches, the Ruby network, and a simple
+point-to-point topology.
+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+You can change simple_ruby to import from this file instead of from msi_caches
+to use the MI_example protocol instead of MSI.
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+           also needs to be updated. For now, email Jason <jason@lowepower.com>
+
+"""
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+import math
+
+from m5.defines import buildEnv
+from m5.util import fatal, panic
+
+from m5.objects import *
+
+class MIExampleSystem(RubySystem):
+
+    def __init__(self):
+        if buildEnv['PROTOCOL'] != 'MI_example':
+            fatal("This system assumes MI_example!")
+
+        super(MIExampleSystem, self).__init__()
+
+    def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
+        """Set up the Ruby cache subsystem. Note: This can't be done in the
+           constructor because many of these items require a pointer to the
+           ruby system (self). This causes infinite recursion in initialize()
+           if we do this in the __init__.
+        """
+        # Ruby's global network.
+        self.network = MyNetwork(self)
+
+        # MI example uses 5 virtual networks
+        self.number_of_virtual_networks = 5
+        self.network.number_of_virtual_networks = 5
+
+        # There is a single global list of all of the controllers to make it
+        # easier to connect everything to the global network. This can be
+        # customized depending on the topology/network requirements.
+        # Create one controller for each L1 cache (and the cache mem obj.)
+        # Create a single directory controller (Really the memory cntrl)
+        self.controllers = \
+            [L1Cache(system, self, cpu) for cpu in cpus] + \
+            [DirController(self, system.mem_ranges, mem_ctrls)] + \
+            [DMAController(self) for i in range(len(dma_ports))]
+
+        # Create one sequencer per CPU. In many systems this is more
+        # complicated since you have to create sequencers for DMA controllers
+        # and other controllers, too.
+        self.sequencers = [RubySequencer(version = i,
+                                # I/D cache is combined and grab from ctrl
+                                icache = self.controllers[i].cacheMemory,
+                                dcache = self.controllers[i].cacheMemory,
+                                clk_domain = self.controllers[i].clk_domain,
+                                pio_master_port = iobus.slave,
+                                mem_master_port = iobus.slave,
+                                pio_slave_port = iobus.master
+                                ) for i in range(len(cpus))] + \
+                          [DMASequencer(version = i,
+                                        slave = port)
+                            for i,port in enumerate(dma_ports)
+                          ]
+
+        for i,c in enumerate(self.controllers[0:len(cpus)]):
+            c.sequencer = self.sequencers[i]
+
+        for i,d in enumerate(self.controllers[-len(dma_ports):]):
+            i += len(cpus)
+            d.dma_sequencer = self.sequencers[i]
+
+        self.num_of_sequencers = len(self.sequencers)
+
+        # Create the network and connect the controllers.
+        # NOTE: This is quite different if using Garnet!
+        self.network.connectControllers(self.controllers)
+        self.network.setup_buffers()
+
+        # Set up a proxy port for the system_port. Used for load binaries and
+        # other functional-only things.
+        self.sys_port_proxy = RubyPortProxy()
+        system.system_port = self.sys_port_proxy.slave
+        self.sys_port_proxy.pio_master_port = iobus.slave
+
+        # Connect the cpu's cache, interrupt, and TLB ports to Ruby
+        for i,cpu in enumerate(cpus):
+            cpu.icache_port = self.sequencers[i].slave
+            cpu.dcache_port = self.sequencers[i].slave
+            isa = buildEnv['TARGET_ISA']
+            if isa == 'x86':
+                cpu.interrupts[0].pio = self.sequencers[i].master
+                cpu.interrupts[0].int_master = self.sequencers[i].slave
+                cpu.interrupts[0].int_slave = self.sequencers[i].master
+            if isa == 'x86' or isa == 'arm':
+                cpu.itb.walker.port = self.sequencers[i].slave
+                cpu.dtb.walker.port = self.sequencers[i].slave
+
+
+class L1Cache(L1Cache_Controller):
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+    def __init__(self, system, ruby_system, cpu):
+        """CPUs are needed to grab the clock domain and system is needed for
+           the cache block size.
+        """
+        super(L1Cache, self).__init__()
+
+        self.version = self.versionCount()
+        # This is the cache memory object that stores the cache data and tags
+        self.cacheMemory = RubyCache(size = '16kB',
+                               assoc = 8,
+                               start_index_bit = self.getBlockSizeBits(system))
+        self.clk_domain = cpu.clk_domain
+        self.send_evictions = self.sendEvicts(cpu)
+        self.ruby_system = ruby_system
+        self.connectQueues(ruby_system)
+
+    def getBlockSizeBits(self, system):
+        bits = int(math.log(system.cache_line_size, 2))
+        if 2**bits != system.cache_line_size.value:
+            panic("Cache line size not a power of 2!")
+        return bits
+
+    def sendEvicts(self, cpu):
+        """True if the CPU model or ISA requires sending evictions from caches
+           to the CPU. Two scenarios warrant forwarding evictions to the CPU:
+           1. The O3 model must keep the LSQ coherent with the caches
+           2. The x86 mwait instruction is built on top of coherence
+           3. The local exclusive monitor in ARM systems
+        """
+        if type(cpu) is DerivO3CPU or \
+           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
+            return True
+        return False
+
+    def connectQueues(self, ruby_system):
+        """Connect all of the queues for this controller.
+        """
+        self.mandatoryQueue = MessageBuffer()
+        self.requestFromCache = MessageBuffer(ordered = True)
+        self.requestFromCache.master = ruby_system.network.slave
+        self.responseFromCache = MessageBuffer(ordered = True)
+        self.responseFromCache.master = ruby_system.network.slave
+        self.forwardToCache = MessageBuffer(ordered = True)
+        self.forwardToCache.slave = ruby_system.network.master
+        self.responseToCache = MessageBuffer(ordered = True)
+        self.responseToCache.slave = ruby_system.network.master
+
+class DirController(Directory_Controller):
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+    def __init__(self, ruby_system, ranges, mem_ctrls):
+        """ranges are the memory ranges assigned to this controller.
+        """
+        if len(mem_ctrls) > 1:
+            panic("This cache system can only be connected to one mem ctrl")
+        super(DirController, self).__init__()
+        self.version = self.versionCount()
+        self.addr_ranges = ranges
+        self.ruby_system = ruby_system
+        self.directory = RubyDirectoryMemory()
+        # Connect this directory to the memory side.
+        self.memory = mem_ctrls[0].port
+        self.connectQueues(ruby_system)
+
+    def connectQueues(self, ruby_system):
+        self.requestToDir = MessageBuffer(ordered = True)
+        self.requestToDir.slave = ruby_system.network.master
+        self.dmaRequestToDir = MessageBuffer(ordered = True)
+        self.dmaRequestToDir.slave = ruby_system.network.master
+
+        self.responseFromDir = MessageBuffer()
+        self.responseFromDir.master = ruby_system.network.slave
+        self.dmaResponseFromDir = MessageBuffer(ordered = True)
+        self.dmaResponseFromDir.master = ruby_system.network.slave
+        self.forwardFromDir = MessageBuffer()
+        self.forwardFromDir.master = ruby_system.network.slave
+        self.requestToMemory = MessageBuffer()
+        self.responseFromMemory = MessageBuffer()
+
+class DMAController(DMA_Controller):
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+    def __init__(self, ruby_system):
+        super(DMAController, self).__init__()
+        self.version = self.versionCount()
+        self.ruby_system = ruby_system
+        self.connectQueues(ruby_system)
+
+    def connectQueues(self, ruby_system):
+        self.mandatoryQueue = MessageBuffer()
+        self.requestToDir = MessageBuffer()
+        self.requestToDir.master = ruby_system.network.slave
+        self.responseFromDir = MessageBuffer(ordered = True)
+        self.responseFromDir.slave = ruby_system.network.master
+
+
+class MyNetwork(SimpleNetwork):
+    """A simple point-to-point network. This doesn't not use garnet.
+    """
+
+    def __init__(self, ruby_system):
+        super(MyNetwork, self).__init__()
+        self.netifs = []
+        self.ruby_system = ruby_system
+
+    def connectControllers(self, controllers):
+        """Connect all of the controllers to routers and connec the routers
+           together in a point-to-point network.
+        """
+        # Create one router/switch per controller in the system
+        self.routers = [Switch(router_id = i) for i in range(len(controllers))]
+
+        # Make a link from each controller to the router. The link goes
+        # externally to the network.
+        self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
+                                        int_node=self.routers[i])
+                          for i, c in enumerate(controllers)]
+
+        # Make an "internal" link (internal to the network) between every pair
+        # of routers.
+        link_count = 0
+        self.int_links = []
+        for ri in self.routers:
+            for rj in self.routers:
+                if ri == rj: continue # Don't connect a router to itself!
+                link_count += 1
+                self.int_links.append(SimpleIntLink(link_id = link_count,
+                                                    src_node = ri,
+                                                    dst_node = rj))
diff --git a/src/gapbs/configs/system/__init__.py b/src/gapbs/configs/system/__init__.py
new file mode 100755
index 0000000..3b71680
--- /dev/null
+++ b/src/gapbs/configs/system/__init__.py
@@ -0,0 +1,31 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+from system import MySystem
+from ruby_system import MyRubySystem
diff --git a/src/gapbs/configs/system/caches.py b/src/gapbs/configs/system/caches.py
new file mode 100755
index 0000000..1b4862a
--- /dev/null
+++ b/src/gapbs/configs/system/caches.py
@@ -0,0 +1,191 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+""" Caches with options for a simple gem5 configuration script
+
+This file contains L1 I/D and L2 caches to be used in the simple
+gem5 configuration script. It uses the SimpleOpts wrapper to set up command
+line options from each individual class.
+"""
+
+import m5
+from m5.objects import Cache, L2XBar, StridePrefetcher, SubSystem
+from m5.params import AddrRange, AllMemory, MemorySize
+from m5.util.convert import toMemorySize
+
+
+# Some specific options for caches
+# For all options see src/mem/cache/BaseCache.py
+
+class PrefetchCache(Cache):
+
+
+    def __init__(self, options):
+        super(PrefetchCache, self).__init__()
+        if not options or options.no_prefetchers:
+            return
+        self.prefetcher = StridePrefetcher()
+
+class L1Cache(PrefetchCache):
+    """Simple L1 Cache with default values"""
+
+    assoc = 8
+    tag_latency = 1
+    data_latency = 1
+    response_latency = 1
+    mshrs = 16
+    tgts_per_mshr = 20
+    writeback_clean = True
+
+    def __init__(self, options=None):
+        super(L1Cache, self).__init__(options)
+        pass
+
+    def connectBus(self, bus):
+        """Connect this cache to a memory-side bus"""
+        self.mem_side = bus.slave
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU-side port
+           This must be defined in a subclass"""
+        raise NotImplementedError
+
+class L1ICache(L1Cache):
+    """Simple L1 instruction cache with default values"""
+
+    # Set the default size
+    size = '32kB'
+
+
+    def __init__(self, opts=None):
+        super(L1ICache, self).__init__(opts)
+        if not opts or not opts.l1i_size:
+            return
+        self.size = opts.l1i_size
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU icache port"""
+        self.cpu_side = cpu.icache_port
+
+class L1DCache(L1Cache):
+    """Simple L1 data cache with default values"""
+
+    # Set the default size
+    size = '32kB'
+
+
+    def __init__(self, opts=None):
+        super(L1DCache, self).__init__(opts)
+        if not opts or not opts.l1d_size:
+            return
+        self.size = opts.l1d_size
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU dcache port"""
+        self.cpu_side = cpu.dcache_port
+
+class MMUCache(Cache):
+    # Default parameters
+    size = '8kB'
+    assoc = 4
+    tag_latency = 1
+    data_latency = 1
+    response_latency = 1
+    mshrs = 20
+    tgts_per_mshr = 12
+    writeback_clean = True
+
+    def __init__(self):
+        super(MMUCache, self).__init__()
+
+    def connectCPU(self, cpu):
+        """Connect the CPU itb and dtb to the cache
+           Note: This creates a new crossbar
+        """
+        self.mmubus = L2XBar()
+        self.cpu_side = self.mmubus.master
+        for tlb in [cpu.itb, cpu.dtb]:
+            self.mmubus.slave = tlb.walker.port
+
+    def connectBus(self, bus):
+        """Connect this cache to a memory-side bus"""
+        self.mem_side = bus.slave
+
+class L2Cache(PrefetchCache):
+    """Simple L2 Cache with default values"""
+
+    # Default parameters
+    size = '256kB'
+    assoc = 16
+    tag_latency = 10
+    data_latency = 10
+    response_latency = 1
+    mshrs = 20
+    tgts_per_mshr = 12
+    writeback_clean = True
+
+
+    def __init__(self, opts=None):
+        super(L2Cache, self).__init__(opts)
+        if not opts or not opts.l2_size:
+            return
+        self.size = opts.l2_size
+
+    def connectCPUSideBus(self, bus):
+        self.cpu_side = bus.master
+
+    def connectMemSideBus(self, bus):
+        self.mem_side = bus.slave
+
+class L3Cache(Cache):
+    """Simple L3 Cache bank with default values
+       This assumes that the L3 is made up of multiple banks. This cannot
+       be used as a standalone L3 cache.
+    """
+
+
+    # Default parameters
+    assoc = 32
+    tag_latency = 40
+    data_latency = 40
+    response_latency = 10
+    mshrs = 256
+    tgts_per_mshr = 12
+    clusivity = 'mostly_excl'
+    # size = '4MB'
+
+    def __init__(self, opts=None):
+        super(L3Cache, self).__init__()
+        self.size = ('4MB')
+
+    def connectCPUSideBus(self, bus):
+        self.cpu_side = bus.master
+
+    def connectMemSideBus(self, bus):
+        self.mem_side = bus.slave
diff --git a/src/gapbs/configs/system/fs_tools.py b/src/gapbs/configs/system/fs_tools.py
new file mode 100755
index 0000000..22a43d2
--- /dev/null
+++ b/src/gapbs/configs/system/fs_tools.py
@@ -0,0 +1,39 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
+
+class CowDisk(IdeDisk):
+
+    def __init__(self, filename):
+        super(CowDisk, self).__init__()
+        self.driveID = 'master'
+        self.image = CowDiskImage(child=RawDiskImage(read_only=True),
+                                  read_only=False)
+        self.image.child.image_file = filename
diff --git a/src/gapbs/configs/system/ruby_system.py b/src/gapbs/configs/system/ruby_system.py
new file mode 100755
index 0000000..b661ace
--- /dev/null
+++ b/src/gapbs/configs/system/ruby_system.py
@@ -0,0 +1,238 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+import m5
+from m5.objects import *
+from m5.util import convert
+from fs_tools import *
+
+class MyRubySystem(System):
+
+    def __init__(self, kernel, disk, cpu_type, mem_sys, num_cpus):
+        super(MyRubySystem, self).__init__()
+
+        self._host_parallel = cpu_type == "kvm"
+
+        # Set up the clock domain and the voltage domain
+        self.clk_domain = SrcClockDomain()
+        self.clk_domain.clock = '3GHz'
+        self.clk_domain.voltage_domain = VoltageDomain()
+
+        self.mem_ranges = [AddrRange(Addr('3GB')), # All data
+                           AddrRange(0xC0000000, size=0x100000), # For I/0
+                           ]
+
+        self.initFS(num_cpus)
+
+        # Replace these paths with the path to your disk images.
+        # The first disk is the root disk. The second could be used for swap
+        # or anything else.
+        self.setDiskImages(disk, disk)
+
+        # Change this path to point to the kernel you want to use
+        self.workload.object_file = kernel
+        # Options specified on the kernel command line
+        boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
+                         'root=/dev/hda1']
+
+        self.workload.command_line = ' '.join(boot_options)
+
+        # Create the CPUs for our system.
+        self.createCPU(cpu_type, num_cpus)
+
+        self.createMemoryControllersDDR3()
+
+        # Create the cache hierarchy for the system.
+
+        if mem_sys == 'MI_example':
+            from MI_example_caches import MIExampleSystem
+            self.caches = MIExampleSystem()
+        elif mem_sys == 'MESI_Two_Level':
+            from MESI_Two_Level import MESITwoLevelCache
+            self.caches = MESITwoLevelCache()
+
+        self.caches.setup(self, self.cpu, self.mem_cntrls,
+                          [self.pc.south_bridge.ide.dma, self.iobus.master],
+                          self.iobus)
+
+        if self._host_parallel:
+            # To get the KVM CPUs to run on different host CPUs
+            # Specify a different event queue for each CPU
+            for i,cpu in enumerate(self.cpu):
+                for obj in cpu.descendants():
+                    obj.eventq_index = 0
+                cpu.eventq_index = i + 1
+
+    def getHostParallel(self):
+        return self._host_parallel
+
+    def totalInsts(self):
+        return sum([cpu.totalInsts() for cpu in self.cpu])
+
+    def createCPU(self, cpu_type, num_cpus):
+        self.cpu = [X86KvmCPU(cpu_id = i)
+                        for i in range(num_cpus)]
+        self.kvm_vm = KvmVM()
+        self.mem_mode = 'atomic_noncaching'
+        if cpu_type == "atomic":
+            self.timingCpu = [AtomicSimpleCPU(cpu_id = i,
+                                        switched_out = True)
+                              for i in range(num_cpus)]
+            map(lambda c: c.createThreads(), self.timingCpu)
+        elif cpu_type == "o3":
+            self.timingCpu = [DerivO3CPU(cpu_id = i,
+                                        switched_out = True)
+                        for i in range(num_cpus)]
+            map(lambda c: c.createThreads(), self.timingCpu)
+        elif cpu_type == "simple":
+            self.timingCpu = [TimingSimpleCPU(cpu_id = i,
+                                        switched_out = True)
+                        for i in range(num_cpus)]
+            map(lambda c: c.createThreads(), self.timingCpu)
+        elif cpu_type == "kvm":
+            pass
+        else:
+            m5.fatal("No CPU type {}".format(cpu_type))
+
+        map(lambda c: c.createThreads(), self.cpu)
+        map(lambda c: c.createInterruptController(), self.cpu)
+
+    def switchCpus(self, old, new):
+        assert(new[0].switchedOut())
+        m5.switchCpus(self, zip(old, new))
+
+    def setDiskImages(self, img_path_1, img_path_2):
+        disk0 = CowDisk(img_path_1)
+        disk2 = CowDisk(img_path_2)
+        self.pc.south_bridge.ide.disks = [disk0, disk2]
+
+    def createMemoryControllersDDR3(self):
+        self._createMemoryControllers(1, DDR3_1600_8x8)
+
+    def _createMemoryControllers(self, num, cls):
+        self.mem_cntrls = [
+            cls(range = self.mem_ranges[0])
+            for i in range(num)
+        ]
+
+    def initFS(self, cpus):
+        self.pc = Pc()
+
+        self.workload = X86FsLinux()
+
+        # North Bridge
+        self.iobus = IOXBar()
+
+        # connect the io bus
+        # Note: pass in a reference to where Ruby will connect to in the future
+        # so the port isn't connected twice.
+        self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
+
+        self.intrctrl = IntrControl()
+
+        ###############################################
+
+        # Add in a Bios information structure.
+        self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
+
+        # Set up the Intel MP table
+        base_entries = []
+        ext_entries = []
+        for i in range(cpus):
+            bp = X86IntelMPProcessor(
+                    local_apic_id = i,
+                    local_apic_version = 0x14,
+                    enable = True,
+                    bootstrap = (i ==0))
+            base_entries.append(bp)
+        io_apic = X86IntelMPIOAPIC(
+                id = cpus,
+                version = 0x11,
+                enable = True,
+                address = 0xfec00000)
+        self.pc.south_bridge.io_apic.apic_id = io_apic.id
+        base_entries.append(io_apic)
+        pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI   ')
+        base_entries.append(pci_bus)
+        isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA   ')
+        base_entries.append(isa_bus)
+        connect_busses = X86IntelMPBusHierarchy(bus_id=1,
+                subtractive_decode=True, parent_bus=0)
+        ext_entries.append(connect_busses)
+        pci_dev4_inta = X86IntelMPIOIntAssignment(
+                interrupt_type = 'INT',
+                polarity = 'ConformPolarity',
+                trigger = 'ConformTrigger',
+                source_bus_id = 0,
+                source_bus_irq = 0 + (4 << 2),
+                dest_io_apic_id = io_apic.id,
+                dest_io_apic_intin = 16)
+        base_entries.append(pci_dev4_inta)
+        def assignISAInt(irq, apicPin):
+            assign_8259_to_apic = X86IntelMPIOIntAssignment(
+                    interrupt_type = 'ExtInt',
+                    polarity = 'ConformPolarity',
+                    trigger = 'ConformTrigger',
+                    source_bus_id = 1,
+                    source_bus_irq = irq,
+                    dest_io_apic_id = io_apic.id,
+                    dest_io_apic_intin = 0)
+            base_entries.append(assign_8259_to_apic)
+            assign_to_apic = X86IntelMPIOIntAssignment(
+                    interrupt_type = 'INT',
+                    polarity = 'ConformPolarity',
+                    trigger = 'ConformTrigger',
+                    source_bus_id = 1,
+                    source_bus_irq = irq,
+                    dest_io_apic_id = io_apic.id,
+                    dest_io_apic_intin = apicPin)
+            base_entries.append(assign_to_apic)
+        assignISAInt(0, 2)
+        assignISAInt(1, 1)
+        for i in range(3, 15):
+            assignISAInt(i, i)
+        self.workload.intel_mp_table.base_entries = base_entries
+        self.workload.intel_mp_table.ext_entries = ext_entries
+
+        entries = \
+           [
+            # Mark the first megabyte of memory as reserved
+            X86E820Entry(addr = 0, size = '639kB', range_type = 1),
+            X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
+            # Mark the rest of physical memory as available
+            X86E820Entry(addr = 0x100000,
+                    size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
+                    range_type = 1),
+            ]
+
+        # Reserve the last 16kB of the 32-bit address space for m5ops
+        entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
+                                    range_type=2))
+
+        self.workload.e820_table.entries = entries
diff --git a/src/gapbs/configs/system/system.py b/src/gapbs/configs/system/system.py
new file mode 100755
index 0000000..3843b5a
--- /dev/null
+++ b/src/gapbs/configs/system/system.py
@@ -0,0 +1,379 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+import m5
+from m5.objects import *
+from m5.util import convert
+from fs_tools import *
+from caches import *
+
+class MySystem(System):
+
+
+    def __init__(self, kernel, disk, cpu_type, num_cpus):
+        super(MySystem, self).__init__()
+        no_kvm=False
+        self._host_parallel = cpu_type == "kvm"
+
+        # Set up the clock domain and the voltage domain
+        self.clk_domain = SrcClockDomain()
+        self.clk_domain.clock = '3GHz'
+        self.clk_domain.voltage_domain = VoltageDomain()
+
+        mem_size = '16GB'
+        self.mem_ranges = [AddrRange('100MB'), # For kernel
+                           AddrRange(0xC0000000, size=0x100000), # For I/0
+                           AddrRange(Addr('4GB'), size = mem_size) # All data
+                           ]
+
+        # Create the main memory bus
+        # This connects to main memory
+        self.membus = SystemXBar(width = 64) # 64-byte width
+        self.membus.badaddr_responder = BadAddr()
+        self.membus.default = Self.badaddr_responder.pio
+
+        # Set up the system port for functional access from the simulator
+        self.system_port = self.membus.slave
+
+        self.initFS(self.membus,num_cpus)
+
+        # Replace these paths with the path to your disk images.
+        # The first disk is the root disk. The second could be used for swap
+        # or anything else.
+        imagepath = disk
+        self.setDiskImages(imagepath, imagepath)
+
+        # Change this path to point to the kernel you want to use
+        self.workload.object_file = kernel
+        # Options specified on the kernel command line
+        boot_options = ['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
+                         'root=/dev/hda1']
+
+        self.workload.command_line = ' '.join(boot_options)
+
+        # Create the CPUs for our system.
+        self.createCPU(cpu_type, num_cpus)
+
+        # Create the cache heirarchy for the system.
+        self.createCacheHierarchy()
+
+        # Set up the interrupt controllers for the system (x86 specific)
+        self.setupInterrupts()
+
+        self.createMemoryControllersDDR3()
+
+        if self._host_parallel:
+            # To get the KVM CPUs to run on different host CPUs
+            # Specify a different event queue for each CPU
+            for i,cpu in enumerate(self.cpu):
+                for obj in cpu.descendants():
+                    obj.eventq_index = 0
+                cpu.eventq_index = i + 1
+
+    def getHostParallel(self):
+        return self._host_parallel
+
+    def totalInsts(self):
+        return sum([cpu.totalInsts() for cpu in self.cpu])
+
+    def createCPU(self, cpu_type, num_cpus):
+        self.cpu = [X86KvmCPU(cpu_id = i)
+                        for i in range(num_cpus)]
+        self.kvm_vm = KvmVM()
+        self.mem_mode = 'atomic_noncaching'
+        if cpu_type == "atomic":
+            self.timingCpu = [AtomicSimpleCPU(cpu_id = i,
+                                        switched_out = True)
+                              for i in range(num_cpus)]
+            map(lambda c: c.createThreads(), self.timingCpu)
+        elif cpu_type == "o3":
+            self.timingCpu = [DerivO3CPU(cpu_id = i,
+                                        switched_out = True)
+                        for i in range(num_cpus)]
+            map(lambda c: c.createThreads(), self.timingCpu)
+        elif cpu_type == "simple":
+            self.timingCpu = [TimingSimpleCPU(cpu_id = i,
+                                        switched_out = True)
+                        for i in range(num_cpus)]
+            map(lambda c: c.createThreads(), self.timingCpu)
+        elif cpu_type == "kvm":
+            pass
+        else:
+            m5.fatal("No CPU type {}".format(cpu_type))
+
+        map(lambda c: c.createThreads(), self.cpu)
+        map(lambda c: c.createInterruptController(), self.cpu)
+
+    def switchCpus(self, old, new):
+        assert(new[0].switchedOut())
+        m5.switchCpus(self, zip(old, new))
+
+    def setDiskImages(self, img_path_1, img_path_2):
+        disk0 = CowDisk(img_path_1)
+        disk2 = CowDisk(img_path_2)
+        self.pc.south_bridge.ide.disks = [disk0, disk2]
+
+    def createCacheHierarchy(self):
+        # Create an L3 cache (with crossbar)
+        self.l3bus = L2XBar(width = 64,
+                            snoop_filter = SnoopFilter(max_capacity='32MB'))
+
+        for cpu in self.cpu:
+            # Create a memory bus, a coherent crossbar, in this case
+            cpu.l2bus = L2XBar()
+
+            # Create an L1 instruction and data cache
+            cpu.icache = L1ICache()
+            cpu.dcache = L1DCache()
+            cpu.mmucache = MMUCache()
+
+            # Connect the instruction and data caches to the CPU
+            cpu.icache.connectCPU(cpu)
+            cpu.dcache.connectCPU(cpu)
+            cpu.mmucache.connectCPU(cpu)
+
+            # Hook the CPU ports up to the l2bus
+            cpu.icache.connectBus(cpu.l2bus)
+            cpu.dcache.connectBus(cpu.l2bus)
+            cpu.mmucache.connectBus(cpu.l2bus)
+
+            # Create an L2 cache and connect it to the l2bus
+            cpu.l2cache = L2Cache()
+            cpu.l2cache.connectCPUSideBus(cpu.l2bus)
+
+            # Connect the L2 cache to the L3 bus
+            cpu.l2cache.connectMemSideBus(self.l3bus)
+
+        self.l3cache = L3Cache()
+        self.l3cache.connectCPUSideBus(self.l3bus)
+
+        # Connect the L3 cache to the membus
+        self.l3cache.connectMemSideBus(self.membus)
+
+    def setupInterrupts(self):
+        for cpu in self.cpu:
+            # create the interrupt controller CPU and connect to the membus
+            cpu.createInterruptController()
+
+            # For x86 only, connect interrupts to the memory
+            # Note: these are directly connected to the memory bus and
+            #       not cached
+            cpu.interrupts[0].pio = self.membus.master
+            cpu.interrupts[0].int_master = self.membus.slave
+            cpu.interrupts[0].int_slave = self.membus.master
+
+
+    def createMemoryControllersDDR3(self):
+        self._createMemoryControllers(2, DDR3_1600_8x8)
+
+    def _createMemoryControllers(self, num, cls):
+        kernel_controller = self._createKernelMemoryController(cls)
+
+        ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
+
+        self.mem_cntrls = [
+            cls(range = ranges[i],
+                port = self.membus.master)
+            for i in range(num)
+        ] + [kernel_controller]
+
+    def _createKernelMemoryController(self, cls):
+        return cls(range = self.mem_ranges[0],
+                   port = self.membus.master)
+
+    def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
+        from math import log
+        bits = int(log(num, 2))
+        if 2**bits != num:
+            m5.fatal("Non-power of two number of memory controllers")
+
+        intlv_bits = bits
+        ranges = [
+            AddrRange(start=rng.start,
+                      end=rng.end,
+                      intlvHighBit = intlv_low_bit + intlv_bits - 1,
+                      xorHighBit = xor_low_bit + intlv_bits - 1,
+                      intlvBits = intlv_bits,
+                      intlvMatch = i)
+                for i in range(num)
+            ]
+
+        return ranges
+
+    def initFS(self, membus, cpus):
+        self.pc = Pc()
+
+        self.workload = X86FsLinux()
+
+        # Constants similar to x86_traits.hh
+        IO_address_space_base = 0x8000000000000000
+        pci_config_address_space_base = 0xc000000000000000
+        interrupts_address_space_base = 0xa000000000000000
+        APIC_range_size = 1 << 12;
+
+        # North Bridge
+        self.iobus = IOXBar()
+        self.bridge = Bridge(delay='50ns')
+        self.bridge.master = self.iobus.slave
+        self.bridge.slave = membus.master
+        # Allow the bridge to pass through:
+        #  1) kernel configured PCI device memory map address: address range
+        #  [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
+        #  2) the bridge to pass through the IO APIC (two pages, already
+        #     contained in 1),
+        #  3) everything in the IO address range up to the local APIC, and
+        #  4) then the entire PCI address space and beyond.
+        self.bridge.ranges = \
+            [
+            AddrRange(0xC0000000, 0xFFFF0000),
+            AddrRange(IO_address_space_base,
+                      interrupts_address_space_base - 1),
+            AddrRange(pci_config_address_space_base,
+                      Addr.max)
+            ]
+
+        # Create a bridge from the IO bus to the memory bus to allow access
+        # to the local APIC (two pages)
+        self.apicbridge = Bridge(delay='50ns')
+        self.apicbridge.slave = self.iobus.master
+        self.apicbridge.master = membus.slave
+        self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
+                                            interrupts_address_space_base +
+                                            cpus * APIC_range_size
+                                            - 1)]
+
+        # connect the io bus
+        self.pc.attachIO(self.iobus)
+
+        # Add a tiny cache to the IO bus.
+        # This cache is required for the classic memory model for coherence
+        self.iocache = Cache(assoc=8,
+                            tag_latency = 50,
+                            data_latency = 50,
+                            response_latency = 50,
+                            mshrs = 20,
+                            size = '1kB',
+                            tgts_per_mshr = 12,
+                            addr_ranges = self.mem_ranges)
+        self.iocache.cpu_side = self.iobus.master
+        self.iocache.mem_side = self.membus.slave
+
+        self.intrctrl = IntrControl()
+
+        ###############################################
+
+        # Add in a Bios information structure.
+        self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
+
+        # Set up the Intel MP table
+        base_entries = []
+        ext_entries = []
+        for i in range(cpus):
+            bp = X86IntelMPProcessor(
+                    local_apic_id = i,
+                    local_apic_version = 0x14,
+                    enable = True,
+                    bootstrap = (i ==0))
+            base_entries.append(bp)
+        io_apic = X86IntelMPIOAPIC(
+                id = cpus,
+                version = 0x11,
+                enable = True,
+                address = 0xfec00000)
+        self.pc.south_bridge.io_apic.apic_id = io_apic.id
+        base_entries.append(io_apic)
+        pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI   ')
+        base_entries.append(pci_bus)
+        isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA   ')
+        base_entries.append(isa_bus)
+        connect_busses = X86IntelMPBusHierarchy(bus_id=1,
+                subtractive_decode=True, parent_bus=0)
+        ext_entries.append(connect_busses)
+        pci_dev4_inta = X86IntelMPIOIntAssignment(
+                interrupt_type = 'INT',
+                polarity = 'ConformPolarity',
+                trigger = 'ConformTrigger',
+                source_bus_id = 0,
+                source_bus_irq = 0 + (4 << 2),
+                dest_io_apic_id = io_apic.id,
+                dest_io_apic_intin = 16)
+        base_entries.append(pci_dev4_inta)
+        def assignISAInt(irq, apicPin):
+            assign_8259_to_apic = X86IntelMPIOIntAssignment(
+                    interrupt_type = 'ExtInt',
+                    polarity = 'ConformPolarity',
+                    trigger = 'ConformTrigger',
+                    source_bus_id = 1,
+                    source_bus_irq = irq,
+                    dest_io_apic_id = io_apic.id,
+                    dest_io_apic_intin = 0)
+            base_entries.append(assign_8259_to_apic)
+            assign_to_apic = X86IntelMPIOIntAssignment(
+                    interrupt_type = 'INT',
+                    polarity = 'ConformPolarity',
+                    trigger = 'ConformTrigger',
+                    source_bus_id = 1,
+                    source_bus_irq = irq,
+                    dest_io_apic_id = io_apic.id,
+                    dest_io_apic_intin = apicPin)
+            base_entries.append(assign_to_apic)
+        assignISAInt(0, 2)
+        assignISAInt(1, 1)
+        for i in range(3, 15):
+            assignISAInt(i, i)
+        self.workload.intel_mp_table.base_entries = base_entries
+        self.workload.intel_mp_table.ext_entries = ext_entries
+
+        entries = \
+           [
+            # Mark the first megabyte of memory as reserved
+            X86E820Entry(addr = 0, size = '639kB', range_type = 1),
+            X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
+            # Mark the rest of physical memory as available
+            X86E820Entry(addr = 0x100000,
+                    size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
+                    range_type = 1),
+            ]
+        # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which
+        # force IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests
+        # to this specific range can pass though bridge to iobus.
+        entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
+            size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
+            range_type=2))
+
+        # Reserve the last 16kB of the 32-bit address space for m5ops
+        entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
+                                    range_type=2))
+
+        # Add the rest of memory. This is where all the actual data is
+        entries.append(X86E820Entry(addr = self.mem_ranges[-1].start,
+            size='%dB' % (self.mem_ranges[-1].size()),
+            range_type=1))
+
+        self.workload.e820_table.entries = entries
diff --git a/src/gapbs/disk-image/gapbs/gapbs-install.sh b/src/gapbs/disk-image/gapbs/gapbs-install.sh
new file mode 100644
index 0000000..8d0b4e4
--- /dev/null
+++ b/src/gapbs/disk-image/gapbs/gapbs-install.sh
@@ -0,0 +1,19 @@
+# Copyright (c) 2020 The Regents of the University of California.
+# SPDX-License-Identifier: BSD 3-Clause
+
+cd /home/gem5/
+su gem5
+
+sudo apt install -y debconf-utils
+sudo debconf-get-selections | grep restart-without-asking > libs.txt
+sed -i 's/false/true/g' libs.txt
+while read line; do echo $line | sudo debconf-set-selections; done < libs.txt
+sudo rm libs.txt
+
+sudo apt install -y git
+echo "12345" | sudo apt-get install -y build-essential libboost-all-dev
+
+git clone https://github.com/darchr/gapbs.git
+cd gapbs
+make HOOKS=1
+cd ..
\ No newline at end of file
diff --git a/src/gapbs/disk-image/gapbs/gapbs.json b/src/gapbs/disk-image/gapbs/gapbs.json
new file mode 100644
index 0000000..96c3546
--- /dev/null
+++ b/src/gapbs/disk-image/gapbs/gapbs.json
@@ -0,0 +1,104 @@
+{
+    "_author": "Hoa Nguyen <hoanguyen@ucdavis.edu>, Marjan Fariborz <mfariborz@ucdavis.edu>",
+    "_license": "Copyright (c) 2020 The Regents of the University of California. SPDX-License-Identifier: BSD 3-Clause",
+    "builders":
+    [
+        {
+            "type": "qemu",
+            "format": "raw",
+            "accelerator": "kvm",
+            "boot_command":
+            [
+                "{{ user `boot_command_prefix` }}",
+                "debian-installer={{ user `locale` }} auto locale={{ user `locale` }} kbd-chooser/method=us ",
+                "file=/floppy/{{ user `preseed` }} ",
+                "fb=false debconf/frontend=noninteractive ",
+                "hostname={{ user `hostname` }} ",
+                "/install/vmlinuz noapic ",
+                "initrd=/install/initrd.gz ",
+                "keyboard-configuration/modelcode=SKIP keyboard-configuration/layout=USA ",
+                "keyboard-configuration/variant=USA console-setup/ask_detect=false ",
+                "passwd/user-fullname={{ user `ssh_fullname` }} ",
+                "passwd/user-password={{ user `ssh_password` }} ",
+                "passwd/user-password-again={{ user `ssh_password` }} ",
+                "passwd/username={{ user `ssh_username` }} ",
+                "-- <enter>"
+            ],
+            "cpus": "{{ user `vm_cpus`}}",
+            "disk_size": "{{ user `image_size` }}",
+            "floppy_files":
+            [
+                "shared/{{ user `preseed` }}"
+            ],
+            "headless": "{{ user `headless` }}",
+            "http_directory": "http",
+            "iso_checksum": "{{ user `iso_checksum` }}",
+            "iso_checksum_type": "{{ user `iso_checksum_type` }}",
+            "iso_urls": [ "{{ user `iso_url` }}" ],
+            "memory": "{{ user `vm_memory`}}",
+            "output_directory": "{{ user `image_name` }}-image",
+            "qemuargs":
+            [
+                [ "-cpu", "host" ],
+                [ "-display", "none" ]
+            ],
+            "qemu_binary": "/usr/local/bin/qemu-system-x86_64",
+            "shutdown_command": "echo '{{ user `ssh_password` }}'|sudo -S shutdown -P now",
+            "ssh_password": "{{ user `ssh_password` }}",
+            "ssh_username": "{{ user `ssh_username` }}",
+            "ssh_wait_timeout": "120m",
+            "vm_name": "{{ user `image_name` }}"
+       }
+    ],
+    "provisioners":
+    [
+        {
+            "type": "file",
+            "source": "../gem5/util/m5/build/x86/out/m5",
+            "destination": "/home/gem5/"
+        },
+        {
+            "type": "file",
+            "source": "shared/serial-getty@.service",
+            "destination": "/home/gem5/"
+        },
+        {
+            "type": "file",
+            "source": "gapbs/runscript.sh",
+            "destination": "/home/gem5/"
+        },
+        {
+            "type": "shell",
+            "execute_command": "echo '{{ user `ssh_password` }}' | {{.Vars}} sudo -E -S bash '{{.Path}}'",
+            "scripts":
+            [
+                "gapbs/post-installation.sh",
+                "gapbs/gapbs-install.sh"
+            ]
+        }
+    ],
+    "variables":
+    {
+        "boot_command_prefix": "<enter><wait><f6><esc><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs><bs>",
+        "desktop": "false",
+        "image_size": "8192",
+        "headless": "true",
+        "iso_checksum": "34416ff83179728d54583bf3f18d42d2",
+        "iso_checksum_type": "md5",
+        "iso_name": "ubuntu-18.04.2-server-amd64.iso",
+        "iso_url": "http://old-releases.ubuntu.com/releases/18.04.2/ubuntu-18.04.2-server-amd64.iso",
+        "locale": "en_US",
+        "preseed" : "preseed.cfg",
+        "hostname": "gem5",
+        "ssh_fullname": "gem5",
+        "hostname": "gem5",
+        "ssh_fullname": "gem5",
+        "ssh_password": "12345",
+        "ssh_username": "gem5",
+        "vm_cpus": "16",
+        "vm_memory": "8192",
+        "image_name": "gapbs"
+  }
+
+}
+
diff --git a/src/gapbs/disk-image/gapbs/post-installation.sh b/src/gapbs/disk-image/gapbs/post-installation.sh
new file mode 100644
index 0000000..1a3109c
--- /dev/null
+++ b/src/gapbs/disk-image/gapbs/post-installation.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Copyright (c) 2020 The Regents of the University of California.
+# SPDX-License-Identifier: BSD 3-Clause
+
+
+echo 'Post Installation Started'
+
+mv /home/gem5/serial-getty@.service /lib/systemd/system/
+
+mv /home/gem5/m5 /sbin
+ln -s /sbin/m5 /sbin/gem5
+
+# copy and run outside (host) script after booting
+cat /home/gem5/runscript.sh >> /root/.bashrc
+
+echo 'Post Installation Done'
diff --git a/src/gapbs/disk-image/gapbs/runscript.sh b/src/gapbs/disk-image/gapbs/runscript.sh
new file mode 100644
index 0000000..92540de
--- /dev/null
+++ b/src/gapbs/disk-image/gapbs/runscript.sh
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+# Copyright (c) 2020 The Regents of the University of California.
+# SPDX-License-Identifier: BSD 3-Clause
+
+
+# This file is the script that runs on the gem5 guest. This reads a file from the host via m5 readfile
+# which contains the workload if it's synthetic or real graph and the size to run.
+
+cd /home/gem5/gapbs
+
+# Read workload file
+m5 readfile > workloadfile
+echo "Done reading workloads"
+
+
+# Read the name of the workload, the size of the workload
+read -r workload arg size < workloadfile
+./$workload $arg $size;
+m5 exit
\ No newline at end of file
diff --git a/src/gapbs/disk-image/shared/preseed.cfg b/src/gapbs/disk-image/shared/preseed.cfg
new file mode 100644
index 0000000..b5cd8a7
--- /dev/null
+++ b/src/gapbs/disk-image/shared/preseed.cfg
@@ -0,0 +1,96 @@
+# Copyright (c) 2020 The Regents of the University of California.
+# SPDX-License-Identifier: BSD 3-Clause
+
+# Choosing keyboard layout
+d-i debian-installer/locale string en_US
+d-i console-setup/ask_detect boolean false
+d-i keyboard-configuration/xkb-keymap select us
+
+# Choosing network interface
+d-i netcfg/choose_interface select auto
+
+# Assigning hostname and domain
+d-i netcfg/get_hostname string gem5-host
+d-i netcfg/get_domain string gem5-domain
+
+d-i netcfg/wireless_wep string
+
+# https://unix.stackexchange.com/q/216348
+# The above link says there's no way to not to set a mirror
+# Should choose a local minor
+d-i mirror/country string manual
+d-i mirror/http/hostname string archive.ubuntu.com
+d-i mirror/http/directory string /ubuntu
+d-i mirror/http/proxy string
+
+# Setting up `root` password
+d-i passwd/root-login boolean false
+
+# Creating a normal user account. This account has sudo permission.
+d-i passwd/user-fullname string gem5
+d-i passwd/username string gem5
+d-i passwd/user-password password 12345
+d-i passwd/user-password-again password 12345
+d-i user-setup/allow-password-weak boolean true
+
+# No home folder encryption
+d-i user-setup/encrypt-home boolean false
+
+# Choosing the clock timezone
+d-i clock-setup/utc boolean true
+d-i time/zone string US/Eastern
+d-i clock-setup/ntp boolean true
+
+# Choosing partition scheme
+# This setting should result in MBR
+# gem5 doesn't work with logical volumes
+d-i partman-auto/method string regular
+d-i partman-lvm/device_remove_lvm boolean true
+d-i partman-md/device_remove_md boolean true
+d-i partman-lvm/confirm boolean true
+d-i partman-lvm/confirm_nooverwrite boolean true
+
+# Ignoring an option to set the home folder in another partition
+d-i partman-auto/choose_recipe select atomic
+
+# Finishing disk partition settings
+d-i partman-md/confirm boolean true
+d-i partman-partitioning/confirm_write_new_label boolean true
+d-i partman/choose_partition select finish
+d-i partman/confirm boolean true
+d-i partman/confirm_nooverwrite boolean true
+
+# Installing standard packages and ubuntu-server packages
+# More details about ubuntu standard packages:
+# https://packages.ubuntu.com/bionic/ubuntu-standard
+# More details about ubuntu-server packages:
+# https://packages.ubuntu.com/bionic/ubuntu-server
+tasksel tasksel/first multiselect standard, ubuntu-server
+
+# openssh-server is required for communicating with Packer
+# build-essential has standard compiling tools, could be removed
+d-i pkgsel/include string openssh-server build-essential
+# No package upgrade
+d-i pkgsel/upgrade select none
+
+# Updating packages automatically is unnecessary
+d-i pkgsel/update-policy select none
+
+# Choosing not to report installed software to some servers
+popularity-contest popularity-contest/participate boolean false
+
+# Installing grub
+d-i grub-installer/only_debian boolean true
+
+# Specifying which partition to boot
+d-i grub-installer/bootdev  string /dev/sda
+
+# Install to the above partition
+d-i grub-installer/bootdev  string default
+
+# Answering the prompt saying the installation is finished
+d-i finish-install/reboot_in_progress note
+
+# Answering the prompt saying no bootloader is installed
+# This will appear if grub is not installed
+nobootloader nobootloader/confirmation_common note
diff --git a/src/gapbs/disk-image/shared/serial-getty@.service b/src/gapbs/disk-image/shared/serial-getty@.service
new file mode 100644
index 0000000..b0424f0
--- /dev/null
+++ b/src/gapbs/disk-image/shared/serial-getty@.service
@@ -0,0 +1,46 @@
+#  SPDX-License-Identifier: LGPL-2.1+
+#
+#  This file is part of systemd.
+#
+#  systemd is free software; you can redistribute it and/or modify it
+#  under the terms of the GNU Lesser General Public License as published by
+#  the Free Software Foundation; either version 2.1 of the License, or
+#  (at your option) any later version.
+
+[Unit]
+Description=Serial Getty on %I
+Documentation=man:agetty(8) man:systemd-getty-generator(8)
+Documentation=http://0pointer.de/blog/projects/serial-console.html
+BindsTo=dev-%i.device
+After=dev-%i.device systemd-user-sessions.service plymouth-quit-wait.service getty-pre.target
+After=rc-local.service
+
+# If additional gettys are spawned during boot then we should make
+# sure that this is synchronized before getty.target, even though
+# getty.target didn't actually pull it in.
+Before=getty.target
+IgnoreOnIsolate=yes
+
+# IgnoreOnIsolate causes issues with sulogin, if someone isolates
+# rescue.target or starts rescue.service from multi-user.target or
+# graphical.target.
+Conflicts=rescue.service
+Before=rescue.service
+
+[Service]
+# The '-o' option value tells agetty to replace 'login' arguments with an
+# option to preserve environment (-p), followed by '--' for safety, and then
+# the entered username.
+ExecStart=-/sbin/agetty --autologin root --keep-baud 115200,38400,9600 %I $TERM
+Type=idle
+Restart=always
+UtmpIdentifier=%I
+TTYPath=/dev/%I
+TTYReset=yes
+TTYVHangup=yes
+KillMode=process
+IgnoreSIGPIPE=no
+SendSIGHUP=yes
+
+[Install]
+WantedBy=getty.target