| commit | da55feb48c48efc03d82a46fe5e249a13537f61f | [log] [tgz] |
|---|---|---|
| author | Hoa Nguyen <hoanguyen@ucdavis.edu> | Fri Aug 27 14:58:30 2021 -0700 |
| committer | Hoa Nguyen <hoanguyen@ucdavis.edu> | Fri Aug 27 23:03:19 2021 +0000 |
| tree | 408989432a8c44728646f1dba404499c6ddb0609 | |
| parent | 0dc3ce6ab73d0e2c87693fa8ea9cc954605165ea [diff] |
resources: Specify the number of cores to riscv platform Due to a recent fix of HiFive platform, https://gem5-review.googlesource.com/c/public/gem5/+/49431, the number of cores must be explicitly specified. Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Change-Id: I053e75ffb2c2d86da3478556599b70ecc45fdf49 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/49630 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/riscv-fs/configs/system/system.py b/src/riscv-fs/configs/system/system.py index 3f545f1..85d162d 100755 --- a/src/riscv-fs/configs/system/system.py +++ b/src/riscv-fs/configs/system/system.py
@@ -119,6 +119,9 @@ # Create the memory controller self.createMemoryControllerDDR3() + # Set number of CPU cores + self.platform.setNumCores(num_cpus) + self.setupInterrupts() # using RiscvLinux as the base full system workload