diff --git a/src/npb/configs/system/MESI_Two_Level.py b/src/npb/configs/system/MESI_Two_Level.py
index 82d0bb8..1294445 100755
--- a/src/npb/configs/system/MESI_Two_Level.py
+++ b/src/npb/configs/system/MESI_Two_Level.py
@@ -34,9 +34,6 @@
 
 """
 
-
-
-
 import math
 
 from m5.defines import buildEnv
@@ -86,9 +83,9 @@
                                 icache = self.controllers[i].L1Icache,
                                 dcache = self.controllers[i].L1Dcache,
                                 clk_domain = self.controllers[i].clk_domain,
-                                pio_master_port = iobus.slave,
-                                mem_master_port = iobus.slave,
-                                pio_slave_port = iobus.master
+                                pio_request_port = iobus.cpu_side_ports,
+                                mem_request_port = iobus.cpu_side_ports,
+                                pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
                                         slave = port)
@@ -113,23 +110,22 @@
         # Set up a proxy port for the system_port. Used for load binaries and
         # other functional-only things.
         self.sys_port_proxy = RubyPortProxy()
-        system.system_port = self.sys_port_proxy.slave
-        self.sys_port_proxy.pio_master_port = iobus.slave
+        system.system_port = self.sys_port_proxy.in_ports
+        self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
 
         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
         for i,cpu in enumerate(cpus):
-            cpu.icache_port = self.sequencers[i].slave
-            cpu.dcache_port = self.sequencers[i].slave
+            cpu.icache_port = self.sequencers[i].in_ports
+            cpu.dcache_port = self.sequencers[i].in_ports
             cpu.createInterruptController()
             isa = buildEnv['TARGET_ISA']
             if isa == 'x86':
-                cpu.interrupts[0].pio = self.sequencers[i].master
-                cpu.interrupts[0].int_master = self.sequencers[i].slave
-                cpu.interrupts[0].int_slave = self.sequencers[i].master
+                cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+                cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
+                cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
             if isa == 'x86' or isa == 'arm':
-                cpu.itb.walker.port = self.sequencers[i].slave
-                cpu.dtb.walker.port = self.sequencers[i].slave
-
+                cpu.itb.walker.port = self.sequencers[i].in_ports
+                cpu.dtb.walker.port = self.sequencers[i].in_ports
 
 class L1Cache(L1Cache_Controller):
 
@@ -194,18 +190,18 @@
         """
         self.mandatoryQueue = MessageBuffer()
         self.requestFromL1Cache = MessageBuffer()
-        self.requestFromL1Cache.master = ruby_system.network.slave
+        self.requestFromL1Cache.out_port = ruby_system.network.in_port
         self.responseFromL1Cache = MessageBuffer()
-        self.responseFromL1Cache.master = ruby_system.network.slave
+        self.responseFromL1Cache.out_port = ruby_system.network.in_port
         self.unblockFromL1Cache = MessageBuffer()
-        self.unblockFromL1Cache.master = ruby_system.network.slave
+        self.unblockFromL1Cache.out_port = ruby_system.network.in_port
 
         self.optionalQueue = MessageBuffer()
 
         self.requestToL1Cache = MessageBuffer()
-        self.requestToL1Cache.slave = ruby_system.network.master
+        self.requestToL1Cache.in_port = ruby_system.network.out_port
         self.responseToL1Cache = MessageBuffer()
-        self.responseToL1Cache.slave = ruby_system.network.master
+        self.responseToL1Cache.in_port = ruby_system.network.out_port
 
 class L2Cache(L2Cache_Controller):
 
@@ -240,17 +236,17 @@
         """Connect all of the queues for this controller.
         """
         self.DirRequestFromL2Cache = MessageBuffer()
-        self.DirRequestFromL2Cache.master = ruby_system.network.slave
+        self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
         self.L1RequestFromL2Cache = MessageBuffer()
-        self.L1RequestFromL2Cache.master = ruby_system.network.slave
+        self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
         self.responseFromL2Cache = MessageBuffer()
-        self.responseFromL2Cache.master = ruby_system.network.slave
+        self.responseFromL2Cache.out_port = ruby_system.network.in_port
         self.unblockToL2Cache = MessageBuffer()
-        self.unblockToL2Cache.slave = ruby_system.network.master
+        self.unblockToL2Cache.in_port = ruby_system.network.out_port
         self.L1RequestToL2Cache = MessageBuffer()
-        self.L1RequestToL2Cache.slave = ruby_system.network.master
+        self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
         self.responseToL2Cache = MessageBuffer()
-        self.responseToL2Cache.slave = ruby_system.network.master
+        self.responseToL2Cache.in_port = ruby_system.network.out_port
 
 
 class DirController(Directory_Controller):
@@ -272,16 +268,16 @@
         self.ruby_system = ruby_system
         self.directory = RubyDirectoryMemory()
         # Connect this directory to the memory side.
-        self.memory = mem_ctrls[0].port
+        self.memory_out_port = mem_ctrls[0].port
         self.connectQueues(ruby_system)
 
     def connectQueues(self, ruby_system):
         self.requestToDir = MessageBuffer()
-        self.requestToDir.slave = ruby_system.network.master
+        self.requestToDir.in_port = ruby_system.network.out_port
         self.responseToDir = MessageBuffer()
-        self.responseToDir.slave = ruby_system.network.master
+        self.responseToDir.in_port = ruby_system.network.out_port
         self.responseFromDir = MessageBuffer()
-        self.responseFromDir.master = ruby_system.network.slave
+        self.responseFromDir.out_port = ruby_system.network.in_port
         self.requestToMemory = MessageBuffer()
         self.responseFromMemory = MessageBuffer()
 
@@ -302,9 +298,9 @@
     def connectQueues(self, ruby_system):
         self.mandatoryQueue = MessageBuffer()
         self.responseFromDir = MessageBuffer(ordered = True)
-        self.responseFromDir.slave = ruby_system.network.master
+        self.responseFromDir.in_port = ruby_system.network.out_port
         self.requestToDir = MessageBuffer()
-        self.requestToDir.master = ruby_system.network.slave
+        self.requestToDir.out_port = ruby_system.network.in_port
 
 
 class MyNetwork(SimpleNetwork):
diff --git a/src/npb/configs/system/MI_example_caches.py b/src/npb/configs/system/MI_example_caches.py
index 9558f58..ca69eab 100755
--- a/src/npb/configs/system/MI_example_caches.py
+++ b/src/npb/configs/system/MI_example_caches.py
@@ -38,9 +38,6 @@
 
 """
 
-
-
-
 import math
 
 from m5.defines import buildEnv
@@ -87,9 +84,9 @@
                                 icache = self.controllers[i].cacheMemory,
                                 dcache = self.controllers[i].cacheMemory,
                                 clk_domain = self.controllers[i].clk_domain,
-                                pio_master_port = iobus.slave,
-                                mem_master_port = iobus.slave,
-                                pio_slave_port = iobus.master
+                                pio_request_port = iobus.cpu_side_ports,
+                                mem_request_port = iobus.cpu_side_ports,
+                                pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
                                         slave = port)
@@ -113,22 +110,22 @@
         # Set up a proxy port for the system_port. Used for load binaries and
         # other functional-only things.
         self.sys_port_proxy = RubyPortProxy()
-        system.system_port = self.sys_port_proxy.slave
-        self.sys_port_proxy.pio_master_port = iobus.slave
+        system.system_port = self.sys_port_proxy.in_ports
+        self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
 
         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
         for i,cpu in enumerate(cpus):
-            cpu.icache_port = self.sequencers[i].slave
-            cpu.dcache_port = self.sequencers[i].slave
+            cpu.icache_port = self.sequencers[i].in_ports
+            cpu.dcache_port = self.sequencers[i].in_ports
             cpu.createInterruptController()
             isa = buildEnv['TARGET_ISA']
             if isa == 'x86':
-                cpu.interrupts[0].pio = self.sequencers[i].master
-                cpu.interrupts[0].int_master = self.sequencers[i].slave
-                cpu.interrupts[0].int_slave = self.sequencers[i].master
+                cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+                cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
+                cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
             if isa == 'x86' or isa == 'arm':
-                cpu.itb.walker.port = self.sequencers[i].slave
-                cpu.dtb.walker.port = self.sequencers[i].slave
+                cpu.itb.walker.port = self.sequencers[i].in_ports
+                cpu.dtb.walker.port = self.sequencers[i].in_ports
 
 
 class L1Cache(L1Cache_Controller):
@@ -178,13 +175,13 @@
         """
         self.mandatoryQueue = MessageBuffer()
         self.requestFromCache = MessageBuffer(ordered = True)
-        self.requestFromCache.master = ruby_system.network.slave
+        self.requestFromCache.out_port = ruby_system.network.in_port
         self.responseFromCache = MessageBuffer(ordered = True)
-        self.responseFromCache.master = ruby_system.network.slave
+        self.responseFromCache.out_port = ruby_system.network.in_port
         self.forwardToCache = MessageBuffer(ordered = True)
-        self.forwardToCache.slave = ruby_system.network.master
+        self.forwardToCache.in_port = ruby_system.network.out_port
         self.responseToCache = MessageBuffer(ordered = True)
-        self.responseToCache.slave = ruby_system.network.master
+        self.responseToCache.in_port = ruby_system.network.out_port
 
 class DirController(Directory_Controller):
 
@@ -205,21 +202,21 @@
         self.ruby_system = ruby_system
         self.directory = RubyDirectoryMemory()
         # Connect this directory to the memory side.
-        self.memory = mem_ctrls[0].port
+        self.memory_out_port = mem_ctrls[0].port
         self.connectQueues(ruby_system)
 
     def connectQueues(self, ruby_system):
         self.requestToDir = MessageBuffer(ordered = True)
-        self.requestToDir.slave = ruby_system.network.master
+        self.requestToDir.in_port = ruby_system.network.out_port
         self.dmaRequestToDir = MessageBuffer(ordered = True)
-        self.dmaRequestToDir.slave = ruby_system.network.master
+        self.dmaRequestToDir.in_port = ruby_system.network.out_port
 
         self.responseFromDir = MessageBuffer()
-        self.responseFromDir.master = ruby_system.network.slave
+        self.responseFromDir.out_port = ruby_system.network.in_port
         self.dmaResponseFromDir = MessageBuffer(ordered = True)
-        self.dmaResponseFromDir.master = ruby_system.network.slave
+        self.dmaResponseFromDir.out_port = ruby_system.network.in_port
         self.forwardFromDir = MessageBuffer()
-        self.forwardFromDir.master = ruby_system.network.slave
+        self.forwardFromDir.out_port = ruby_system.network.in_port
         self.requestToMemory = MessageBuffer()
         self.responseFromMemory = MessageBuffer()
 
@@ -240,9 +237,9 @@
     def connectQueues(self, ruby_system):
         self.mandatoryQueue = MessageBuffer()
         self.requestToDir = MessageBuffer()
-        self.requestToDir.master = ruby_system.network.slave
+        self.requestToDir.out_port = ruby_system.network.in_port
         self.responseFromDir = MessageBuffer(ordered = True)
-        self.responseFromDir.slave = ruby_system.network.master
+        self.responseFromDir.in_port = ruby_system.network.out_port
 
 
 class MyNetwork(SimpleNetwork):
diff --git a/src/npb/configs/system/MOESI_CMP_directory.py b/src/npb/configs/system/MOESI_CMP_directory.py
index 372b792..5208e73 100755
--- a/src/npb/configs/system/MOESI_CMP_directory.py
+++ b/src/npb/configs/system/MOESI_CMP_directory.py
@@ -76,9 +76,9 @@
         self.controllers = \
             [L1Cache(system, self, cpu, self._numL2Caches) for cpu in cpus] + \
             [L2Cache(system, self, self._numL2Caches) for num in \
-            range(self._numL2Caches)] + \
-            [DirController(self, system.mem_ranges, mem_ctrls)] + \
-            [DMAController(self) for i in range(len(dma_ports))]
+            range(self._numL2Caches)] + [DirController(self, \
+            system.mem_ranges, mem_ctrls)] + [DMAController(self) for i \
+            in range(len(dma_ports))]
 
         # Create one sequencer per CPU and dma controller.
         # Sequencers for other controllers can be here here.
@@ -87,9 +87,9 @@
                                 icache = self.controllers[i].L1Icache,
                                 dcache = self.controllers[i].L1Dcache,
                                 clk_domain = self.controllers[i].clk_domain,
-                                pio_master_port = iobus.slave,
-                                mem_master_port = iobus.slave,
-                                pio_slave_port = iobus.master
+                                pio_request_port = iobus.cpu_side_ports,
+                                mem_request_port = iobus.cpu_side_ports,
+                                pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
                                         slave = port)
@@ -114,22 +114,22 @@
         # Set up a proxy port for the system_port. Used for load binaries and
         # other functional-only things.
         self.sys_port_proxy = RubyPortProxy()
-        system.system_port = self.sys_port_proxy.slave
-        self.sys_port_proxy.pio_master_port = iobus.slave
+        system.system_port = self.sys_port_proxy.in_ports
+        self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
 
         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
         for i,cpu in enumerate(cpus):
-            cpu.icache_port = self.sequencers[i].slave
-            cpu.dcache_port = self.sequencers[i].slave
+            cpu.icache_port = self.sequencers[i].in_ports
+            cpu.dcache_port = self.sequencers[i].in_ports
             cpu.createInterruptController()
             isa = buildEnv['TARGET_ISA']
             if isa == 'x86':
-                cpu.interrupts[0].pio = self.sequencers[i].master
-                cpu.interrupts[0].int_master = self.sequencers[i].slave
-                cpu.interrupts[0].int_slave = self.sequencers[i].master
+                cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+                cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
+                cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
             if isa == 'x86' or isa == 'arm':
-                cpu.itb.walker.port = self.sequencers[i].slave
-                cpu.dtb.walker.port = self.sequencers[i].slave
+                cpu.itb.walker.port = self.sequencers[i].in_ports
+                cpu.dtb.walker.port = self.sequencers[i].in_ports
 
 
 class L1Cache(L1Cache_Controller):
@@ -197,13 +197,13 @@
         """
         self.mandatoryQueue = MessageBuffer()
         self.requestFromL1Cache = MessageBuffer()
-        self.requestFromL1Cache.master = ruby_system.network.slave
+        self.requestFromL1Cache.out_port = ruby_system.network.in_port
         self.responseFromL1Cache = MessageBuffer()
-        self.responseFromL1Cache.master = ruby_system.network.slave
+        self.responseFromL1Cache.out_port = ruby_system.network.in_port
         self.requestToL1Cache = MessageBuffer()
-        self.requestToL1Cache.slave = ruby_system.network.master
+        self.requestToL1Cache.in_port = ruby_system.network.out_port
         self.responseToL1Cache = MessageBuffer()
-        self.responseToL1Cache.slave = ruby_system.network.master
+        self.responseToL1Cache.in_port = ruby_system.network.out_port
         self.triggerQueue = MessageBuffer(ordered = True)
 
 class L2Cache(L2Cache_Controller):
@@ -241,18 +241,18 @@
         """Connect all of the queues for this controller.
         """
         self.GlobalRequestFromL2Cache = MessageBuffer()
-        self.GlobalRequestFromL2Cache.master = ruby_system.network.slave
+        self.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
         self.L1RequestFromL2Cache = MessageBuffer()
-        self.L1RequestFromL2Cache.master = ruby_system.network.slave
+        self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
         self.responseFromL2Cache = MessageBuffer()
-        self.responseFromL2Cache.master = ruby_system.network.slave
+        self.responseFromL2Cache.out_port = ruby_system.network.in_port
 
         self.GlobalRequestToL2Cache = MessageBuffer()
-        self.GlobalRequestToL2Cache.slave = ruby_system.network.master
+        self.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
         self.L1RequestToL2Cache = MessageBuffer()
-        self.L1RequestToL2Cache.slave = ruby_system.network.master
+        self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
         self.responseToL2Cache = MessageBuffer()
-        self.responseToL2Cache.slave = ruby_system.network.master
+        self.responseToL2Cache.in_port = ruby_system.network.out_port
         self.triggerQueue = MessageBuffer(ordered = True)
 
 
@@ -276,18 +276,18 @@
         self.ruby_system = ruby_system
         self.directory = RubyDirectoryMemory()
         # Connect this directory to the memory side.
-        self.memory = mem_ctrls[0].port
+        self.memory_out_port = mem_ctrls[0].port
         self.connectQueues(ruby_system)
 
     def connectQueues(self, ruby_system):
         self.requestToDir = MessageBuffer()
-        self.requestToDir.slave = ruby_system.network.master
+        self.requestToDir.in_port = ruby_system.network.out_port
         self.responseToDir = MessageBuffer()
-        self.responseToDir.slave = ruby_system.network.master
+        self.responseToDir.in_port = ruby_system.network.out_port
         self.responseFromDir = MessageBuffer()
-        self.responseFromDir.master = ruby_system.network.slave
+        self.responseFromDir.out_port = ruby_system.network.in_port
         self.forwardFromDir = MessageBuffer()
-        self.forwardFromDir.master = ruby_system.network.slave
+        self.forwardFromDir.out_port = ruby_system.network.in_port
         self.requestToMemory = MessageBuffer()
         self.responseFromMemory = MessageBuffer()
 
@@ -308,11 +308,11 @@
     def connectQueues(self, ruby_system):
         self.mandatoryQueue = MessageBuffer()
         self.responseFromDir = MessageBuffer()
-        self.responseFromDir.slave = ruby_system.network.master
+        self.responseFromDir.in_port = ruby_system.network.out_port
         self.reqToDir = MessageBuffer()
-        self.reqToDir.master = ruby_system.network.slave
+        self.reqToDir.out_port = ruby_system.network.in_port
         self.respToDir = MessageBuffer()
-        self.respToDir.master = ruby_system.network.slave
+        self.respToDir.out_port = ruby_system.network.in_port
         self.triggerQueue = MessageBuffer(ordered = True)
 
 
diff --git a/src/npb/configs/system/caches.py b/src/npb/configs/system/caches.py
index 4630cea..0f03238 100755
--- a/src/npb/configs/system/caches.py
+++ b/src/npb/configs/system/caches.py
@@ -73,7 +73,7 @@
 
     def connectBus(self, bus):
         """Connect this cache to a memory-side bus"""
-        self.mem_side = bus.slave
+        self.mem_side = bus.cpu_side_ports
 
     def connectCPU(self, cpu):
         """Connect this cache's port to a CPU-side port
@@ -137,13 +137,13 @@
            Note: This creates a new crossbar
         """
         self.mmubus = L2XBar()
-        self.cpu_side = self.mmubus.master
+        self.cpu_side = self.mmubus.mem_side_ports
         for tlb in [cpu.itb, cpu.dtb]:
-            self.mmubus.slave = tlb.walker.port
+            self.mmubus.cpu_side_ports = tlb.walker.port
 
     def connectBus(self, bus):
         """Connect this cache to a memory-side bus"""
-        self.mem_side = bus.slave
+        self.mem_side = bus.cpu_side_ports
 
 class L2Cache(PrefetchCache):
     """Simple L2 Cache with default values"""
@@ -168,10 +168,10 @@
         self.size = opts.l2_size
 
     def connectCPUSideBus(self, bus):
-        self.cpu_side = bus.master
+        self.cpu_side = bus.mem_side_ports
 
     def connectMemSideBus(self, bus):
-        self.mem_side = bus.slave
+        self.mem_side = bus.cpu_side_ports
 
 class L3Cache(Cache):
     """Simple L3 Cache bank with default values
@@ -196,7 +196,7 @@
         self.size = (opts.l3_size)
 
     def connectCPUSideBus(self, bus):
-        self.cpu_side = bus.master
+        self.cpu_side = bus.mem_side_ports
 
     def connectMemSideBus(self, bus):
-        self.mem_side = bus.slave
+        self.mem_side = bus.cpu_side_ports
diff --git a/src/npb/configs/system/fs_tools.py b/src/npb/configs/system/fs_tools.py
index 22a43d2..5e5e2df 100755
--- a/src/npb/configs/system/fs_tools.py
+++ b/src/npb/configs/system/fs_tools.py
@@ -33,7 +33,7 @@
 
     def __init__(self, filename):
         super(CowDisk, self).__init__()
-        self.driveID = 'master'
+        self.driveID = 'device0'
         self.image = CowDiskImage(child=RawDiskImage(read_only=True),
                                   read_only=False)
         self.image.child.image_file = filename
diff --git a/src/npb/configs/system/ruby_system.py b/src/npb/configs/system/ruby_system.py
index 98feef1..4d313bb 100755
--- a/src/npb/configs/system/ruby_system.py
+++ b/src/npb/configs/system/ruby_system.py
@@ -81,7 +81,8 @@
             from .MOESI_CMP_directory import MOESICMPDirCache
             self.caches = MOESICMPDirCache()
         self.caches.setup(self, self.cpu, self.mem_cntrls,
-                          [self.pc.south_bridge.ide.dma, self.iobus.master],
+                          [self.pc.south_bridge.ide.dma,
+                          self.iobus.mem_side_ports],
                           self.iobus)
 
         if self._host_parallel:
@@ -139,9 +140,9 @@
 
     def _createMemoryControllers(self, num, cls):
         self.mem_cntrls = [
-            cls(range = self.mem_ranges[0])
+            MemCtrl(dram = cls(range = self.mem_ranges[0]))
             for i in range(num)
-        ]
+            ]
 
     def initFS(self, cpus):
         self.pc = Pc()
diff --git a/src/npb/configs/system/system.py b/src/npb/configs/system/system.py
index ff1fa5e..23b8b60 100755
--- a/src/npb/configs/system/system.py
+++ b/src/npb/configs/system/system.py
@@ -68,7 +68,7 @@
         self.membus.default = Self.badaddr_responder.pio
 
         # Set up the system port for functional access from the simulator
-        self.system_port = self.membus.slave
+        self.system_port = self.membus.cpu_side_ports
 
         self.initFS(self.membus, num_cpus)
 
@@ -207,9 +207,9 @@
             # For x86 only, connect interrupts to the memory
             # Note: these are directly connected to the memory bus and
             #       not cached
-            cpu.interrupts[0].pio = self.membus.master
-            cpu.interrupts[0].int_master = self.membus.slave
-            cpu.interrupts[0].int_slave = self.membus.master
+            cpu.interrupts[0].pio = self.membus.mem_side_ports
+            cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
+            cpu.interrupts[0].int_responder = self.membus.mem_side_ports
 
     # Memory latency: Using the smaller number from [3]: 96ns
     def createMemoryControllersDDR4(self):
@@ -221,14 +221,14 @@
         ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
 
         self.mem_cntrls = [
-            cls(range = ranges[i],
-                port = self.membus.master)
+            MemCtrl(dram = cls(range = ranges[i]),
+                    port = self.membus.mem_side_ports)
             for i in range(num)
         ] + [kernel_controller]
 
     def _createKernelMemoryController(self, cls):
-        return cls(range = self.mem_ranges[0],
-                   port = self.membus.master)
+        return MemCtrl(dram = cls(range = self.mem_ranges[0]),
+                       port = self.membus.mem_side_ports)
 
     def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
         from math import log
@@ -262,8 +262,8 @@
         # North Bridge
         self.iobus = IOXBar()
         self.bridge = Bridge(delay='50ns')
-        self.bridge.master = self.iobus.slave
-        self.bridge.slave = membus.master
+        self.bridge.mem_side_port = self.iobus.cpu_side_ports
+        self.bridge.cpu_side_port = membus.mem_side_ports
         # Allow the bridge to pass through:
         #  1) kernel configured PCI device memory map address: address range
         #  [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
@@ -283,8 +283,8 @@
         # Create a bridge from the IO bus to the memory bus to allow access
         # to the local APIC (two pages)
         self.apicbridge = Bridge(delay='50ns')
-        self.apicbridge.slave = self.iobus.master
-        self.apicbridge.master = membus.slave
+        self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
+        self.apicbridge.mem_side_port = membus.cpu_side_ports
         self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
                                             interrupts_address_space_base +
                                             cpus * APIC_range_size
@@ -303,8 +303,8 @@
                             size = '1kB',
                             tgts_per_mshr = 12,
                             addr_ranges = self.mem_ranges)
-        self.iocache.cpu_side = self.iobus.master
-        self.iocache.mem_side = self.membus.slave
+        self.iocache.cpu_side = self.iobus.mem_side_ports
+        self.iocache.mem_side = self.membus.cpu_side_ports
 
         self.intrctrl = IntrControl()