diff --git a/_data/documentation.yml b/_data/documentation.yml
index 5087db9..2a0a53f 100755
--- a/_data/documentation.yml
+++ b/_data/documentation.yml
@@ -76,6 +76,8 @@
           url: /documentation/gem5-stdlib/x86-full-system-tutorial
         - page: Developing Your Own Components Tutorial
           url: /documentation/gem5-stdlib/develop-own-components-tutorial
+        - page: How To Create Your Own Board Using The gem5 Standard Library
+          url: /documentation/gem5-stdlib/develop-stdlib-board
 
     - title: gem5 Resources
       id: gem5_resources
diff --git a/_pages/documentation/gem5-stdlib/4-tutorial-creating-stdlib-board.md b/_pages/documentation/gem5-stdlib/4-tutorial-creating-stdlib-board.md
new file mode 100644
index 0000000..05c510e
--- /dev/null
+++ b/_pages/documentation/gem5-stdlib/4-tutorial-creating-stdlib-board.md
@@ -0,0 +1,187 @@
+---
+layout: documentation
+title: How To Create Your Own Board Using The gem5 Standard Library
+parent: gem5-standard-library
+doc: gem5 documentation
+permalink: /documentation/gem5-stdlib/develop-stdlib-board
+author: Jasjeet Rangi, Kunal Pai
+---
+
+## How to Create Your Own Board Using the gem5 Standard Library
+
+In this tutorial we will cover how to create a custom  board using the gem5 Standard Library.
+
+
+This tutorial is based on the process used to make the _RiscvMatched_, a RISC-V prebuilt board that inherits from `MinorCPU`. This board can be found at `src/python/gem5/prebuilt/riscvmatched`.
+
+This tutorial will create a single-channeled DDR4 memory of size 2 GiB, a core using the MinorCPU and the RISC-V ISA though the same process can be used for another type or size of memory, ISA and core.
+
+Likewise, this tutorial will utilize the UniqueCacheHierarchy made in the [Developing Your Own Components Tutorial](https://www.gem5.org/documentation/gem5-stdlib/develop-own-components-tutorial), though anyother cache hierarchy may be used.
+
+First, we start by importing the components and stdlib features we require.
+
+``` python
+from gem5.components.cachehierarchies.classic.unique_cache_hierarchy import UniqueCacheHierarchy
+from gem5.components.boards.abstract_system_board import AbstractSystemBoard
+from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
+from gem5.components.processors.base_cpu_core import BaseCPUCore
+from gem5.components.boards.se_binary_workload import SEBinaryWorkload
+from gem5.components.memory import SingleChannelDDR4_2400
+from gem5.utils.override import overrides
+from gem5.isas import ISA
+from typing import List
+from m5.objects import AddrRange, IOXBar, Port
+from m5.objects import BaseMMU, Port, BaseCPU, Process
+from m5.objects.RiscvCPU import RiscvMinorCPU
+```
+
+We will begin development by creating a specialized CPU core for our board which inherits from an ISA-specific version of the chosen CPU.
+Since our ISA is RISC-V and the CPU type we desire is a MinorCPU, we will inherit from `RiscvMinorCPU`.
+This is done so that we can set our own parameters to tailor the CPU it to our requirements.
+In our example will override a single parameter:  `decodeToExecuteForwardDelay` (the default is 1).
+We have called this new CPU core type `UniqueCPU`.
+
+
+``` python
+class UniqueCPU(RiscvMinorCPU):
+    decodeToExecuteForwardDelay = 2
+```
+
+As `RiscvMinorCPU` inherits from `BaseCPU`, we can incorporate this into the standard library using `BaseCPUCore`, a Standard Library wrapper for `BaseCPU` objects (source code for this can be found at `src/python/gem5/components/processors/base_cpu_core.py`).
+The `BaseCPUCore` takes the `BaseCPU` as an argument during construction.
+Ergo, we can do the following:
+
+```python
+core = BaseCPUCore(core = UniqueCPU(core_id=0))
+```
+
+**Note**: `BaseCPU` objects require a unique `core_id` to be specified upon construction.
+
+Next we must define our processor.
+In the gem5 Standard Library a processor is a collection of cores.
+In cases, such as ours, we can utilize the library's `BaseCPUProcessor`, a processor which contains `BaseCPUCore` objects (source code can be found in `src/python/gem5/components/processors/base_cpu_processor.py`).
+The `BaseCPUProcessor` requires a list of `BaseCPUCore`s.
+Therefore:
+
+```python
+processor = BaseCPUProcessor(cores = [core])
+```
+
+Next we focus on the construction of the board to host our components.
+All boards must inherit from `AbstractBoard` and in most cases, gem5's `System` simobject.
+Therefore, our board will inherit from `AbstractSystemBoard` in this case; an abstract class that inherits from both.
+
+In order to run simulations with SE mode, we must also inherit from `SEBinaryWorkload`.
+
+All `AbstractBoard`s must specify `clk_freq` (the clock frequency), the `processor`, `memory`, and the `cache_hierarchy`.
+We already have our processor, and will use the `UniqueCacheHierarchy` for the `cache_hierarchy` and a `SingleChannelDDR4_2400`, with a size of 2GiB for the memory.
+
+We will call this the `UniqueBoard` and it should look like the following:
+
+``` python
+class UniqueBoard(AbstractSystemBoard, SEBinaryWorkload):
+    def __init__(
+        self,
+        clk_freq: str,
+    ) -> None:
+        core = BaseCPUCore(core = UniqueCPU(core_id=0))
+        processor = BaseCPUProcessor(cores = [core])
+        memory = SingleChannelDDR4_2400("2GiB")
+        cache_hierarchy = UniqueCacheHierarchy()
+        super().__init__(
+            clk_freq=clk_freq,
+            processor=processor,
+            memory=memory,
+            cache_hierarchy=cache_hierarchy,
+        )
+```
+
+With the contructor complete, we must implement the abstract methods in `AbstractSystemBoard`.
+It is useful here to look at the source for `AbstractBoard` in `/src/python/gem5/components/boards/abstract_system_board.py`.
+
+The abstract methods you choose to implement or not will depend on what type of system you are creating.
+In our example functions such as `_setup_board`, are unneeded so we will implement them with `pass`.
+In other instances we will use `NotImplementedError` for cases where a particular component/feature is not available on this board and an error should be returned if trying to access it.
+For example, our board will have no IO bus.
+We will therefore implement `has_io_bus` to return `False` and have `get_io_bus` raise a `NotImplementedError` if called.
+
+With the exception of `_setup_memory_ranges`, we do not implement many of the features the `AbstractSystemBoard` requires. The board should look like this:
+
+``` python
+class UniqueBoard(AbstractSystemBoard, SEBinaryWorkload):
+    def __init__(
+        self,
+        clk_freq: str,
+    ) -> None:
+        core = BaseCPUCore(core = UniqueCPU(core_id=0))
+        processor = BaseCPUProcessor(cores = [core])
+        memory = SingleChannelDDR4_2400("2GiB")
+        cache_hierarchy = UniqueCacheHierarchy()
+        super().__init__(
+            clk_freq=clk_freq,
+            processor=processor,
+            memory=memory,
+            cache_hierarchy=cache_hierarchy,
+        )
+
+    @overrides(AbstractSystemBoard)
+    def _setup_board(self) -> None:
+        pass
+
+    @overrides(AbstractSystemBoard)
+    def has_io_bus(self) -> bool:
+        return False
+
+    @overrides(AbstractSystemBoard)
+    def get_io_bus(self) -> IOXBar:
+        raise NotImplementedError(
+            "UniqueBoard does not have an IO Bus. "
+            "Use `has_io_bus()` to check this."
+        )
+
+    @overrides(AbstractSystemBoard)
+    def has_dma_ports(self) -> bool:
+        return False
+
+    @overrides(AbstractSystemBoard)
+    def get_dma_ports(self) -> List[Port]:
+        raise NotImplementedError(
+            "UniqueBoard does not have DMA Ports. "
+            "Use `has_dma_ports()` to check this."
+        )
+
+    @overrides(AbstractSystemBoard)
+    def has_coherent_io(self) -> bool:
+        return False
+
+    @overrides(AbstractSystemBoard)
+    def get_mem_side_coherent_io_port(self) -> Port:
+        raise NotImplementedError(
+            "UniqueBoard does not have any I/O ports. Use has_coherent_io to "
+            "check this."
+        )
+
+    @overrides(AbstractSystemBoard)
+    def _setup_memory_ranges(self) -> None:
+        memory = self.get_memory()
+        self.mem_ranges = [AddrRange(memory.get_size())]
+        memory.set_memory_range(self.mem_ranges)
+```
+
+
+This concludes the creation of your custom board for the gem5 standard library.
+From this you can create a runscript and test your board:
+
+``` python
+from .unqiue_board import UniqueBoard
+from gem5.resources.resource import Resource
+from gem5.simulate.simulator import Simulator
+
+board = UniqueBoard(clk_freq="1.2GHz")
+
+#As we are using the RISCV ISA, "riscv-hello" should work.
+board.set_se_binary_workload(Resource("riscv-hello"))
+
+simulator = Simulator(board=board)
+simulator.run()
+```
diff --git a/_pages/documentation/general_docs/building/index.md b/_pages/documentation/general_docs/building/index.md
index f56b3e5..44241e9 100644
--- a/_pages/documentation/general_docs/building/index.md
+++ b/_pages/documentation/general_docs/building/index.md
@@ -12,7 +12,7 @@
 ## Supported operating systems and environments
 
 gem5 has been designed with a Linux environment in mind. We test regularly
-on **Ubuntu 18.04** and **Ubuntu 20.04** to ensure gem5 functions well in
+on **Ubuntu 18.04**, **Ubuntu 20.04**, **Ubuntu 22.04** to ensure gem5 functions well in
 these environments. Though **any Linux based OS should function if the correct
 dependencies are installed**. We ensure that gem5 is compilable with both gcc
 and clang (see [Dependencies](#dependencies)  below for compiler version
@@ -38,9 +38,9 @@
 
 * **git** : gem5 uses git for version control.
 * **gcc**: gcc is used to compiled gem5. **Version >=7 must be used**. We
-support up to gcc Version 11.
+support up to gcc Version 12.
 * **Clang**: Clang can also be used. At present, we support Clang 6 to
-Clang 11 (inclusive).
+Clang 14 (inclusive).
 * **SCons** : gem5 uses SCons as its build environment. SCons 3.0 or greater
 must be used.
 * **Python 3.6+** : gem5 relies on Python development libraries. gem5 can be
@@ -51,10 +51,22 @@
 libraries. It is a necessary dependency if you wish to use the SystemC
 implementation.
 
+### Setup on Ubuntu 22.04 (gem5 >= v21.1)
+
+If compiling gem5 on Ubuntu 22.04, or related Linux distributions, you may
+install all these dependencies using APT:
+
+```
+sudo apt install build-essential git m4 scons zlib1g zlib1g-dev \
+    libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \
+    python3-dev libboost-all-dev pkg-config
+```
+
+
 ### Setup on Ubuntu 20.04 (gem5 >= v21.0)
 
 If compiling gem5 on Ubuntu 20.04, or related Linux distributions, you may
-install all these dependencies using API:
+install all these dependencies using APT:
 
 ```
 sudo apt install build-essential git m4 scons zlib1g zlib1g-dev \
@@ -78,21 +90,25 @@
 For users struggling to setup an environment to build and run gem5, we provide
 the following Docker Images:
 
-Ubuntu 20.04 with all optional dependencies:
-[gcr.io/gem5-test/ubuntu-20.04_all-dependencies:v22-0](
-https://gcr.io/gem5-test/ubuntu-20.04_all-dependencies:v22-0) ([source Dockerfile](
-https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile)).
+Ubuntu 22.04 with all optional dependencies:
+[gcr.io/gem5-test/ubuntu-22.04_all-dependencies:v22-1](
+https://gcr.io/gem5-test/ubuntu-22.04_all-dependencies:v22-1) ([source Dockerfile](
+https://gem5.googlesource.com/public/gem5/+/refs/tags/v22.1.0.0/util/dockerfiles/ubuntu-22.04_all-dependencies/Dockerfile)).
 
-Ubuntu 20.04 with minimum dependencies:
-[gcr.io/gem5-test/ubuntu-20.04_min-dependencies:v22-0](
-https://gcr.io/gem5-test/ubuntu-20.04_min-dependencies:v22-0) ([source Dockerfile](
-https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/util/dockerfiles/ubuntu-20.04_min-dependencies/Dockerfile)).
+Ubuntu 22.04 with minimum dependencies:
+[gcr.io/gem5-test/ubuntu-22.04_min-dependencies:v22-1](
+https://gcr.io/gem5-test/ubuntu-22.04_min-dependencies:v22-1) ([source Dockerfile](
+https://gem5.googlesource.com/public/gem5/+/refs/tags/v22.1.0.0/util/dockerfiles/ubuntu-22.04_min-dependencies/Dockerfile)).
+
+Ubuntu 20.04 with all optional dependencies:
+[gcr.io/gem5-test/ubuntu-20.04_all-dependencies:v22-1](
+https://gcr.io/gem5-test/ubuntu-20.04_all-dependencies:v22-1) ([source Dockerfile](
+https://gem5.googlesource.com/public/gem5/+/refs/tags/v22.1.0.0/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile)).
 
 Ubuntu 18.04 with all optional dependencies:
-[gcr.io/gem5-test/ubuntu-18.04_all-dependencies:v22-0](
-https://gcr.io/gem5-test/ubuntu-18.04_all-dependencies:v22-0) ([source Dockerfile](
-https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile)).
-
+[gcr.io/gem5-test/ubuntu-18.04_all-dependencies:v22-1](
+https://gcr.io/gem5-test/ubuntu-18.04_all-dependencies:v22-1) ([source Dockerfile](
+https://gem5.googlesource.com/public/gem5/+/refs/tags/v22.1.0.0/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile)).
 
 
 
@@ -116,7 +132,7 @@
 
 Where `<gem5 directory>` is the full path of the gem5 in your file system, and
 `<image>` is the image pulled (e.g.,
-`gcr.io/gem5-test/ubuntu-20.04_all-dependencies:v22-0`).
+`gcr.io/gem5-test/ubuntu-22.04_all-dependencies:v22-1`).
 
 From this environment, you will be able to build and run gem5 from the `/gem5`
 directory.
diff --git a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
index 561c517..4cee564 100644
--- a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
+++ b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
@@ -126,15 +126,20 @@
 ```
 
 Now, we can create a CPU. We'll start with the most simple timing-based
-CPU in gem5, *TimingSimpleCPU*. This CPU model executes each instruction
+CPU in gem5 for the X86 ISA, *X86TimingSimpleCPU*. This CPU model executes each instruction
 in a single clock cycle to execute, except memory requests, which flow
 through the memory system. To create the CPU you can simply just
 instantiate the object:
 
 ```
-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()
 ```
 
+If we wanted to use the RISCV ISA we could use `RiscvTimingSimpleCPU` or if
+we wanted to use the ARM ISA we could use `ArmTimingSimpleCPU`. However, we
+will continue to use the X86 ISA for this exercise.
+
+
 Next, we're going to create the system-wide memory bus:
 
 ```
@@ -346,12 +351,29 @@
 simulation should finish faster. Or, if you change the DDR controller to
 DDR4, the performance should be better.
 
-Additionally, you can change the CPU model to `MinorCPU` to model an
-in-order CPU, or `DerivO3CPU` to model an out-of-order CPU. However,
-note that `DerivO3CPU` currently does not work with simple.py, because
-`DerivO3CPU` requires a system with separate instruction and data caches
-(`DerivO3CPU` does work with the configuration in the next section). Also note
-that `MinorCPU` does not work with X86 as of gem5 version 22.0.0.
+Additionally, you can change the CPU model to `X86MinorCPU` to model an
+in-order CPU, or `X86O3CPU` to model an out-of-order CPU. However,
+note that `X86O3CPU` currently does not work with simple.py, because
+`X86O3CPU` requires a system with separate instruction and data caches
+(`X86O3CPU` does work with the configuration in the next section).
+
+All gem5 BaseCPU's take the naming format `{ISA}{Type}CPU`. Ergo, if we wanted
+a RISCV Minor CPU we'd use `RiscvMinorCPU`.
+
+The Valid ISAs are:
+* Riscv
+* Arm
+* X86
+* Sparc
+* Power
+* Mips
+
+The CPU types are:
+* AtomicSimpleCPU
+* O3CPU
+* TimingSimpleCPu
+* KvmCPU
+* MinorCPU
 
 Next, we will add caches to our configuration file to model a more
 complex system.
diff --git a/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md b/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
index fa48250..3f42b81 100644
--- a/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
+++ b/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
@@ -187,7 +187,7 @@
 m5out/config.ini. The CPU is shown on line 51:
 
     [system.cpu]
-    type=AtomicSimpleCPU
+    type=X86AtomicSimpleCPU
     children=interrupts isa mmu power_state tracer workload
     branchPred=Null
     checker=Null
diff --git a/_pages/documentation/learning_gem5/part2/part2_5_memoryobject.md b/_pages/documentation/learning_gem5/part2/part2_5_memoryobject.md
index 77cf7ee..22962e6 100644
--- a/_pages/documentation/learning_gem5/part2/part2_5_memoryobject.md
+++ b/_pages/documentation/learning_gem5/part2/part2_5_memoryobject.md
@@ -698,7 +698,7 @@
 system.mem_mode = 'timing'
 system.mem_ranges = [AddrRange('512MB')]
 
-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()
 
 system.memobj = SimpleMemobj()
 
@@ -782,7 +782,7 @@
      ...
 
 You may also want to change the CPU model to the out-of-order model
-(`DerivO3CPU`). When using the out-of-order CPU you will potentially see
+(`X86O3CPU`). When using the out-of-order CPU you will potentially see
 a different address stream since it allows multiple memory requests
 outstanding at a once. When using the out-of-order CPU, there will now
 be many stalls because the `SimpleMemobj` is blocking.
diff --git a/_pages/documentation/learning_gem5/part3/part3_08_configuration.md b/_pages/documentation/learning_gem5/part3/part3_08_configuration.md
index 0a76256..c6bed44 100644
--- a/_pages/documentation/learning_gem5/part3/part3_08_configuration.md
+++ b/_pages/documentation/learning_gem5/part3/part3_08_configuration.md
@@ -22,7 +22,7 @@
 First, so we can test our *coherence* protocol, let's use two CPUs.
 
 ```python
-system.cpu = [TimingSimpleCPU(), TimingSimpleCPU()]
+system.cpu = [X86TimingSimpleCPU(), X86TimingSimpleCPU()]
 ```
 
 Next, after the memory controllers have been instantiated, we are going
@@ -111,15 +111,12 @@
 
 def sendEvicts(self, cpu):
     """True if the CPU model or ISA requires sending evictions from caches
-       to the CPU. Two scenarios warrant forwarding evictions to the CPU:
+       to the CPU. Three scenarios warrant forwarding evictions to the CPU:
        1. The O3 model must keep the LSQ coherent with the caches
        2. The x86 mwait instruction is built on top of coherence
        3. The local exclusive monitor in ARM systems
     """
-    if type(cpu) is DerivO3CPU or \
-       buildEnv['TARGET_ISA'] in ('x86', 'arm'):
-        return True
-    return False
+    return True
 ```
 
 Finally, we need to implement `connectQueues` to connect all of the
diff --git a/_pages/documentation/learning_gem5/part3/part3_11_simple-MI_example.md b/_pages/documentation/learning_gem5/part3/part3_11_simple-MI_example.md
index 69362d9..c11be46 100644
--- a/_pages/documentation/learning_gem5/part3/part3_11_simple-MI_example.md
+++ b/_pages/documentation/learning_gem5/part3/part3_11_simple-MI_example.md
@@ -130,10 +130,7 @@
            2. The x86 mwait instruction is built on top of coherence
            3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or \
-           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
-            return True
-        return False
+        return True
 
     def connectQueues(self, ruby_system):
         """Connect all of the queues for this controller.
diff --git a/_pages/static/scripts/part1/simple.py b/_pages/static/scripts/part1/simple.py
index 69521fe..34defcd 100644
--- a/_pages/static/scripts/part1/simple.py
+++ b/_pages/static/scripts/part1/simple.py
@@ -53,7 +53,7 @@
 system.mem_ranges = [AddrRange('512MB')] # Create an address range
 
 # Create a simple CPU
-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()
 
 # Create a memory bus, a system crossbar, in this case
 system.membus = SystemXBar()
@@ -64,13 +64,12 @@
 
 # create the interrupt controller for the CPU and connect to the membus
 system.cpu.createInterruptController()
-
-# For x86 only, make sure the interrupts are connected to the memory
-# Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts[0].pio = system.membus.master
-    system.cpu.interrupts[0].int_master = system.membus.slave
-    system.cpu.interrupts[0].int_slave = system.membus.master
+system.cpu.interrupts[0].pio = system.membus.master
+# For x86 only, we make sure the interrupts are connected to the memory.
+# Note: These are directly connected to the memory bus and are not cached.
+# For other ISAs, the following two lines should be removed.
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
 
 # Create a DDR3 memory controller and connect it to the membus
 system.mem_ctrl = MemCtrl()
diff --git a/_pages/static/scripts/part1/two_level.py b/_pages/static/scripts/part1/two_level.py
index 64ee33c..4ca700e 100644
--- a/_pages/static/scripts/part1/two_level.py
+++ b/_pages/static/scripts/part1/two_level.py
@@ -53,7 +53,7 @@
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
 binary = os.path.join(thispath, '../../../',
-                      'tests/test-progs/hello/bin/', isa, 'linux/hello')
+                      'tests/test-progs/hello/bin/x86/linux/hello')
 
 # create the system we are going to simulate
 system = System()
@@ -68,7 +68,10 @@
 system.mem_ranges = [AddrRange('512MB')] # Create an address range
 
 # Create a simple CPU
-system.cpu = TimingSimpleCPU()
+# As this configuration script is for X86, we use `X86TimingSimpleCPU`
+# If a RISCV or ARM simple CPU is desired then `RiscvTimingSimpleCPU` or
+# `ArmTimingSimpleCPU` should be used.
+system.cpu = X86TimingSimpleCPU()
 
 # Create an L1 instruction and data cache
 system.cpu.icache = L1ICache()
@@ -97,13 +100,12 @@
 
 # create the interrupt controller for the CPU
 system.cpu.createInterruptController()
-
+system.cpu.interrupts[0].pio = system.membus.mem_side_ports
 # For x86 only, make sure the interrupts are connected to the memory
+# For other ISAs, these two lines should be removed
 # Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts[0].pio = system.membus.mem_side_ports
-    system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
-    system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
 
 # Connect the system up to the membus
 system.system_port = system.membus.cpu_side_ports
diff --git a/_pages/static/scripts/part1/two_level_opts.py b/_pages/static/scripts/part1/two_level_opts.py
index ce0dd47..91326f4 100644
--- a/_pages/static/scripts/part1/two_level_opts.py
+++ b/_pages/static/scripts/part1/two_level_opts.py
@@ -69,7 +69,7 @@
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
 binary = os.path.join(thispath, '../../../',
-                      'tests/test-progs/hello/bin/', isa, 'linux/hello')
+                      'tests/test-progs/hello/bin/x86/linux/hello')
 
 # If the executable is specified by user, run the hello program
 if hasattr(parser, "binary"):
@@ -88,7 +88,7 @@
 system.mem_ranges = [AddrRange('512MB')] # Create an address range
 
 # Create a simple CPU
-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()
 
 # Create an L1 instruction and data cache
 system.cpu.icache = L1ICache(options)
@@ -117,13 +117,9 @@
 
 # create the interrupt controller for the CPU
 system.cpu.createInterruptController()
-
-# For x86 only, make sure the interrupts are connected to the memory
-# Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts[0].pio = system.membus.mem_side_ports
-    system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
-    system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
+system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
 
 # Connect the system up to the membus
 system.system_port = system.membus.cpu_side_ports
diff --git a/_pages/static/scripts/part3/configs/msi_caches.py b/_pages/static/scripts/part3/configs/msi_caches.py
index 9228251..08664dd 100644
--- a/_pages/static/scripts/part3/configs/msi_caches.py
+++ b/_pages/static/scripts/part3/configs/msi_caches.py
@@ -153,10 +153,7 @@
            2. The x86 mwait instruction is built on top of coherence
            3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or \
-           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
-            return True
-        return False
+        return True
 
     def connectQueues(self, ruby_system):
         """Connect all of the queues for this controller.
diff --git a/_pages/static/scripts/part3/configs/ruby_caches_MI_example.py b/_pages/static/scripts/part3/configs/ruby_caches_MI_example.py
index 6103605..8556a27 100644
--- a/_pages/static/scripts/part3/configs/ruby_caches_MI_example.py
+++ b/_pages/static/scripts/part3/configs/ruby_caches_MI_example.py
@@ -148,10 +148,7 @@
            2. The x86 mwait instruction is built on top of coherence
            3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or \
-           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
-            return True
-        return False
+        return True
 
     def connectQueues(self, ruby_system):
         """Connect all of the queues for this controller.
diff --git a/_pages/static/scripts/part4/system.py b/_pages/static/scripts/part4/system.py
index ae0b620..623eb03 100644
--- a/_pages/static/scripts/part4/system.py
+++ b/_pages/static/scripts/part4/system.py
@@ -102,7 +102,7 @@
         # Note: If you use multiple CPUs, then the BIOS config needs to be
         #       updated as well.
 
-        self.cpu = AtomicSimpleCPU()
+        self.cpu = X86AtomicSimpleCPU()
         self.mem_mode = 'atomic'
         self.cpu.createThreads()