diff --git a/_data/documentation.yml b/_data/documentation.yml
index c312368..d79037c 100644
--- a/_data/documentation.yml
+++ b/_data/documentation.yml
@@ -70,9 +70,22 @@
   - title: gem5 101
     items:
       - title: gem5 101
-        id: gem5_101
         url: /gem5_101
 
+      - title: Hello World
+        url: /hello_world
+
+      - title: Adding An Instruction
+        url: /adding_an_instruction
+
+      - title: CPU Models
+        url: /cpu_models
+
       - title: Branch Prediction
-        id: branch_prediction
         url: /branch_prediction
+
+      - title: Caches
+        url: /caches
+
+      - title: Multi Core
+        url: /multi_core
diff --git a/_pages/documentation/gem5-101/adding_an_instruction.md b/_pages/documentation/gem5-101/adding_an_instruction.md
index 342c237..42e479c 100644
--- a/_pages/documentation/gem5-101/adding_an_instruction.md
+++ b/_pages/documentation/gem5-101/adding_an_instruction.md
@@ -1,10 +1,13 @@
 ---
-title: "Adding an instruction"
+layout: documentation
+title: Adding An Instruction
+doc: gem5 101
+permalink: /adding_an_instruction/
+author: Jason Lowe-Power
 date: 2018-05-12T23:00:45-04:00
-draft: false
-weight: 20
 ---
 
+## Part 2 Adding An Instruction
 For part II, we had used gem5 capabilities straight out of the box. Now,
 we will witness the flexibility and usefulness of gem5 by extending the
 simulator functionality. We walk you through the implementation of an
@@ -12,5 +15,3 @@
 introduce you to gem5's language for describing instruction sets, and
 illustrate how instructions are decoded and broken down into micro-ops
 which are ultimately executed by the processor.
-
-
diff --git a/_pages/documentation/gem5-101/branch_prediction.md b/_pages/documentation/gem5-101/branch_prediction.md
index 1792403..18e28b5 100644
--- a/_pages/documentation/gem5-101/branch_prediction.md
+++ b/_pages/documentation/gem5-101/branch_prediction.md
@@ -2,7 +2,6 @@
 layout: documentation
 title: Branch Prediction
 doc: gem5 101
-parent: introduction
 permalink: /branch_prediction/
 author: Jason Lowe-Power
 ---
diff --git a/_pages/documentation/gem5-101/caches.md b/_pages/documentation/gem5-101/caches.md
index 07a2ec4..306ecd5 100644
--- a/_pages/documentation/gem5-101/caches.md
+++ b/_pages/documentation/gem5-101/caches.md
@@ -1,14 +1,15 @@
 ---
-title: "Caches"
+layout: documentation
+title: Caches
+doc: gem5 101
+permalink: /caches/
+author: Jason Lowe-Power
 date: 2018-05-12T23:01:31-04:00
-draft: false
-weight: 50
 ---
 
+## Part 5 Caches
 After looking at the processor core, we now turn our attention to the
 cache hierarchy. We continue our focus on experimentation, and consider
 tradeoffs in cache design such as replacement policies and
 set-associativity. Furthermore, we also learn more about the gem5
 simulator, and create our first simObject\!
-
-
diff --git a/_pages/documentation/gem5-101/cpu_models.md b/_pages/documentation/gem5-101/cpu_models.md
index 77eff47..5335e6a 100644
--- a/_pages/documentation/gem5-101/cpu_models.md
+++ b/_pages/documentation/gem5-101/cpu_models.md
@@ -1,15 +1,15 @@
 ---
-title: "CPU models"
-date: 2018-05-12T23:01:03-04:00
-draft: false
-weight: 30
+layout: documentation
+title: CPU Models
+doc: gem5 101
+permalink: /cpu_models/
+author: Jason Lowe-Power
 ---
 
+## Part 3 CPU Models
 From the ISA, we now move on to the processor micro-architecture. Part
 III introduces the various different cpu models implemented in gem5, and
 analyzes the performance of a pipelined implementation. Specifically,
 you will learn how the latency and bandwidth of different pipeline
 stages affect overall performance. Also, a sample usage of gem5
 pseudo-instructions is also included at no additional cost.
-
-
diff --git a/_pages/documentation/gem5-101/gem5_101.md b/_pages/documentation/gem5-101/gem5_101.md
index 62db868..b85e0df 100644
--- a/_pages/documentation/gem5-101/gem5_101.md
+++ b/_pages/documentation/gem5-101/gem5_101.md
@@ -7,6 +7,7 @@
 date: 2016-04-27
 ---
 
+# Gem5 101
 
 This is a six part course which will help you pick up the basics of gem5, and
 illustrate some common uses. This course is based around the assignments from a
diff --git a/_pages/documentation/gem5-101/hello_world.md b/_pages/documentation/gem5-101/hello_world.md
index 8c80d65..d163519 100644
--- a/_pages/documentation/gem5-101/hello_world.md
+++ b/_pages/documentation/gem5-101/hello_world.md
@@ -1,15 +1,16 @@
 ---
-title: "Hello world"
-date: 2018-05-12T23:00:17-04:00
-draft: false
-weight: 10
+layout: documentation
+title: Hello World
+doc: gem5 101
+id: gem5_101
+permalink: /hello_world/
+author: Jason Lowe-Power
 ---
 
+## Part 1 Hello World
 In part I, you will first learn to download and build gem5 correctly,
 create a simple configuration script for a simple system, write a simple
 C program and run a gem5 simulation. You will then introduce a two-level
 cache hierarchy in your system (fun stuff). Finally, you get to view the
 effect of changing system parameters such as memory types, processor
 frequency and complexity on the performance of your simple program.
-
-
diff --git a/_pages/documentation/gem5-101/multi_core.md b/_pages/documentation/gem5-101/multi_core.md
index fc62a42..4e576e0 100644
--- a/_pages/documentation/gem5-101/multi_core.md
+++ b/_pages/documentation/gem5-101/multi_core.md
@@ -1,10 +1,12 @@
 ---
-title: "Multi Core"
-date: 2018-05-12T23:01:57-04:00
-draft: false
-weight: 60
+layout: documentation
+title: Multi Core
+doc: gem5 101
+permalink: /multi_core/
+author: Jason Lowe-Power
 ---
 
+## Part 6 Multi Core
 For this last part, we go both multi-core and full system at the same
 time\! We analyze the performance of a simple application on giving it
 more computational resources (cores). We also boot a full-fledged
@@ -12,5 +14,3 @@
 gem5. Most importantly, we teach you how to create your own, simpler
 version of the dreaded fs.py configuration script, one that you can feel
 comfortable modifying.
-
-