Adjust styles
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
diff --git a/_data/documentation.yml b/_data/documentation.yml
index 754de07..8d9cdd8 100644
--- a/_data/documentation.yml
+++ b/_data/documentation.yml
@@ -4,7 +4,8 @@
- title: Architecture Support
items:
- title: Architecture Support
- url: /documentation/general_docs/architecture_support/index
+ url: /documentation/general_docs/architecture_support/
+
- title: ARM Implementation
url: /documentation/general_docs/architecture_support/arm_implementation
diff --git a/_pages/documentation/general_docs/architecture_support/arm_implementation.md b/_pages/documentation/general_docs/architecture_support/arm_implementation.md
index 3634dc1..0cdb84d 100644
--- a/_pages/documentation/general_docs/architecture_support/arm_implementation.md
+++ b/_pages/documentation/general_docs/architecture_support/arm_implementation.md
@@ -4,7 +4,6 @@
doc: ARM implementation
parent: architecture_support
permalink: /documentation/general_docs/architecture_support/arm_implementation
-author: "?"
---
# ARM Implementation
@@ -13,7 +12,10 @@
## Supported features and modes
-The ARM Architecture models within gem5 support an [ARMv8-A](https://www.arm.com/products/processors/armv8-architecture.php) profile of the ARM® architecture allowing for multi-processor simulation of 64-bit ARM (AArch64) cores. Additionally, gem5 still support ARMv7-a profile of the ARM® architecture with multi-processor extensions for 32-bit simulation. Specifically, this include support for Thumb®, Thumb-2, VFPv3 (32 double register variant), [NEON™](https://www.arm.com/products/processors/technologies/neon.php), and [Large Physical Address Extensions (LPAE)](https://www.arm.com/products/processors/technologies/virtualization-extensions.php). Optional features of the architecture that are not currently supported are [TrustZone®](https://www.arm.com/products/processors/technologies/trustzone.php), ThumbEE, [Jazelle®](http://www.arm.com/products/processors/technologies/jazelle.php), and [Virtualization](https://www.arm.com/products/processors/technologies/virtualization-extensions.php).
+The ARM Architecture models within gem5 support an [ARMv8-A](https://www.arm.com/products/processors/armv8-architecture.php) profile of the ARM® architecture allowing for multi-processor simulation of 64-bit ARM (AArch64) cores.
+Additionally, gem5 still support ARMv7-a profile of the ARM® architecture with multi-processor extensions for 32-bit simulation.
+Specifically, this include support for Thumb®, Thumb-2, VFPv3 (32 double register variant), [NEON™](https://www.arm.com/products/processors/technologies/neon.php), and [Large Physical Address Extensions (LPAE)](https://www.arm.com/products/processors/technologies/virtualization-extensions.php).
+Optional features of the architecture that are not currently supported are [TrustZone®](https://www.arm.com/products/processors/technologies/trustzone.php), ThumbEE, [Jazelle®](http://www.arm.com/products/processors/technologies/jazelle.php), and [Virtualization](https://www.arm.com/products/processors/technologies/virtualization-extensions.php).
## Pertinent Non-supported Features
@@ -44,4 +46,5 @@
For the AArch32 boot loader: The initial conditions of the bootloader running are the same as those ffor Linux, `r0 = 0; r1 = machine number; r2 = atags ptr;` and some special registers for the boot loader to use `r3 = start address of kernel; r4 = address of GIC; r5 = adderss of flags register`.
The bootloader works by reading the MPIDR register to determine the CPU number.
CPU0 jumps immediately to the kernel while CPUn enables their interrupt interface and and wait for an interrupt.
-When CPU0 generates an IPI, CPUn reads the flags register until it is non-zero and then jumps to that address.
\ No newline at end of file
+When CPU0 generates an IPI, CPUn reads the flags register until it is non-zero and then jumps to that address.
+
diff --git a/_pages/documentation/general_docs/architecture_support/index.md b/_pages/documentation/general_docs/architecture_support/index.md
index e7f8584..83481b1 100644
--- a/_pages/documentation/general_docs/architecture_support/index.md
+++ b/_pages/documentation/general_docs/architecture_support/index.md
@@ -4,7 +4,6 @@
doc: Architecture Support
parent: architecture_support
permalink: /documentation/general_docs/architecture_support/
-author: "?"
---
# Architecture Support
@@ -66,4 +65,5 @@
## MIPS
-## RISC-V
\ No newline at end of file
+## RISC-V
+
