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-About content goes here.
+The gem5 simulator is a modular platform for computer-system architecture research, encompassing system-level architecture as well as processor microarchitecture.
-* A list item
-* Another list item
+gem5 is an open source computer architecture simulator used in academia and in industry.
+gem5 has been under development for the past 15 years initially at the University of Michigan as the m5 project and at the University of Wisconsin as the GEMS project.
+Since the [merger of m5 and GEMS in 2011](/publications/#original-paper), gem5 has been cited by over [2900 publications](https://scholar.google.com/scholar?cites=5769943816602695435).
+gem5 is used by many industrial research labs including ARM Research, AMD Research, Google, Micron, Metempsy, HP, Samsung, and others.
+
+
+## Features
+
+### Multiple interchangeable CPU models.
+gem5 provides four interpretation-based CPU models: a simple one-CPI CPU; a
+detailed model of an in-order CPU, and a detailed model of an out-of-order CPU.
+These CPU models use a common high-level ISA description. In addition, gem5
+features a KVM-based CPU that uses virtualisation to accelerate simulation.
+
+### [Event-driven memory system.](Media:2015_ws_02_hansson_gem5_workshop_2015.pdf "wikilink")
+gem5 features a detailed, event-driven memory system including caches,
+crossbars, snoop filters, and a fast and accurate DRAM controller model, for
+capturing the impact of current and emerging memories, e.g. LPDDR3/4/5, DDR3/4,
+GDDR5, HBM1/2/3, HMC, WideIO1/2. The components can be arranged flexibly,
+e.g., to model complex multi-level non-uniform cache hierarchies with
+heterogeneous memories.
+
+### [Multiple ISA support](Supported Architectures "wikilink")
+gem5 decouples ISA semantics from its CPU models, enabling effective support
+of multiple ISAs. Currently gem5 supports the Alpha, ARM, SPARC, MIPS, POWER,
+RISC-V and x86 ISAs. However, all guest platforms aren't
+supported on all host platforms (most notably Alpha requires
+little-endian hardware).
+
+### Homogeneous and heterogeneous multi-core
+The CPU models and caches can be combined in arbitrary topologies, creating
+homogeneous, and heterogeneous multi-core systems. A MOESI snooping cache
+coherence protocol keeps the caches coherent.
+
+### Full-system capability
+ - **ARM**: gem5 can model up to 64 (heterogeneous) cores of a
+ Realview ARM platform, and boot [unmodified
+ Linux](ARM_Linux_Kernel "wikilink") and
+ [Android](Android_Marshmallow "wikilink") with a combination of
+ in-order and out-of-order CPUs. The ARM implementation supports
+ 32 or 64-bit kernels and applications.
+ - **x86**: The gem5 simulator supports a standard PC platform and boots unmodified Linux
+ - **RISC-V**: Support for RISC-V privileged ISA spec is a work in progress.
+ - **SPARC**: The gem5 simulator models a single core of a
+ UltraSPARC T1 processor with sufficient detail to boot Solaris
+ in a similar manner as the Sun T1 Architecture simulator tools
+ (building the hypervisor with specific defines and using the
+ HSMID virtual disk driver).
+ - **Alpha**: gem5 models a DEC Tsunami system in sufficient detail
+ to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio.
+ We have also booted HP/Compaq's Tru64 5.1 operating system in
+ the past, though we no longer actively maintain that capability.
+
+### Application-only support
+In application-only (non-full-system) mode, gem5 can execute a variety of
+architecture/OS binaries with Linux emulation.
+
+### Multi-system capability
+Multiple systems can be instantiated within a single simulation process. In
+conjunction with full-system modeling, this feature allows simulation of entire
+client-server networks.
+
+### Power and energy modeling
+gem5’s objects are arranged in OS-visible power and clock domains, enabling a
+range of experiments in power- and energy-efficiency. With out-of-the-box
+support for OS-controller Dynamic Voltage and Frequency (DVFS) scaling, gem5
+provides a complete platform for research in future energy-efficient systems.
+See [how to run your own DVFS experiments](Running_gem5#Experimenting_with_DVFS
+"wikilink").
+
+
+### [A trace-based CPU](TraceCPU "wikilink")
+CPU model that plays back elastic traces, which are dependency and timing
+annotated traces generated by a probe attached to the out-of-order CPU model.
+The focus of the Trace CPU model is to achieve memory-system (cache-hierarchy,
+interconnects and main memory) performance exploration in a fast and reasonably
+accurate way instead of using the detailed CPU model.
+
+### [Co-simulation with SystemC.](Media:2015_ws_09_2015-06-14_Gem5_ISCA.pptx "wikilink")
+gem5 can be included in a SystemC simulation, effectively running as a
+thread inside the SystemC event kernel, and keeping the events and timelines
+synchronized between the two worlds. This functionality enables the gem5
+components to interoperate with a wide range of System on Chip (SoC) component
+models, such as interconnects, devices and accelerators. A wrapper for SystemC
+Transaction Level Modelling (TLM) is provided.
+
+### [A NoMali GPU model.](Media:2015_ws_04_ISCA_2015_NoMali.pdf "wikilink")
+gem5 comes with an integrated NoMali GPU model that is compatible with the
+Linux and Android GPU driver stack, and thus removes the need for software
+rendering. The NoMali GPU does not produce any output, but ensures that
+CPU-centric experiments produce representative results.
+
+
+## Licensing
+The gem5 simulator is released under a Berkeley-style open source license.
+Roughly speaking, you are free to use our code however you wish, as long as you
+leave our copyright on it. For more details, see the LICENSE file included in
+the source download. Note that the portions of gem5 derived from other sources
+are also subject to the licensing restrictions of the original sources.
+
+## Acknowledgments
+
+The gem5 simulator has been developed with generous support from several
+sources, including the National Science Foundation, AMD, ARM,
+Hewlett-Packard, IBM, Intel, MIPS, and Sun. Individuals working on gem5
+have also been supported by fellowships from Intel, Lucent, and the
+Alfred P. Sloan Foundation.
+
+Any opinions, findings and conclusions or recommendations expressed in
+this material are those of the author(s) and do not necessarily reflect
+the views of the National Science Foundation (NSF) or any other sponsor.
diff --git a/_pages/events/arm-summit-2017.md b/_pages/events/arm-summit-2017.md
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+---
+title: "ARM research summit 2017"
+date: 2018-05-13T18:51:37-04:00
+draft: false
+weight: 1000
+---
+
+The [ARM Research Summit](https://developer.arm.com/research/summit) is
+an academic summit to discuss future trends and disruptive technologies
+across all sectors of computing. On the first day of the Summit, ARM
+Research will host a gem5 workshop to give a brief overview of gem5 for
+computer engineers who are new to gem5 and dive deeper into some of
+gem5's more advanced capabilities. The attendees will learn what gem5
+can and cannot do, how to use and extend gem5, as well as how to
+contribute back to gem5.
+
+The ARM Research Summit will take place in Cambridge (UK) over the days
+of 11-13 September 2017. The gem5 workshop will be a full day event on
+the 11th September.
+
+# Streaming & Offline viewing
+
+The workshop is being streamed live and all talks will be available on
+YouTube after the workshop. See the [main summit
+page](https://developer.arm.com/research/summit/summit-live) for
+details.
+
+# Target Audience
+
+The primary audience is researchers who are using, or planning to use,
+gem5 for architecture research.
+
+**Prerequisites**: Attendees are expected to have a working knowledge of
+C++, Python, and computer systems.
+
+# Registration
+
+See the main [ARM Research Summit
+website](https://developer.arm.com/research/summit) for details about
+registration.
+
+# Schedule
+
+The workshop will take place on Monday the 11th September 2017 at
+Robinson College in Cambridge (UK). The workshop starts at 9.00 and runs
+in parallel with the main Summit program until 16.30 when it joins the
+main
+program.
+
+| Time | Topic |
+| ----------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
+| 09.00-09.30 | Welcome and introduction to gem5 — [slides](Media:Summit2017_Intro_to_gem5.pdf "wikilink") |
+| 09.30-09.45 | [Interacting with gem5 using workload-automation & devlib](#WA "wikilink") — [slides](Media:Summit2017_wa_devlib.pdf "wikilink") |
+| 09.45-10.00 | [ARM Research Starter Kit: System Modeling using gem5](#StarterKit "wikilink") — [slides](Media:Summit2017_starterkit.pdf "wikilink") |
+| 10.00-10.15 | Break |
+| 10.15-10.30 | [Debugging a target-agnostic JIT compiler with GEM5](#JIT_Debugging "wikilink") |
+| 10.30-11.00 | [Learning gem5: Modeling Cache Coherence with gem5](#Ruby "wikilink") — [slides](Media:Summit2017_learning_gem5_ruby.pdf "wikilink") |
+| 11.00-11.15 | Break (overlaps with main program break) |
+| 11.15-11.45 | [A Detailed On-Chip Network Model inside a Full-System Simulator](#Garnet2 "wikilink") — [slides](Media:Summit2017_garnet2.0_tutorial.pdf "wikilink") |
+| 11.45-12.00 | [Integrating and quantifying the impact of low power modes in the DRAM controller in gem5](#DRAMPower "wikilink") — [slides](Media:Summit2017_drampower.pdf "wikilink") |
+| 12.00-12.15 | Break |
+| 12.15-12.45 | [CPU power estimation using PMCs and its application in gem5](#PowMon "wikilink") — [slides](Media:Summit2017_powmon.pdf "wikilink") |
+| 12.45-13.00 | [gem5: empowering the masses](#PowerFramework "wikilink") — [slides](Media:Summit2017_powerframework.pdf "wikilink") |
+| 13.00-14.15 | Lunch |
+| 14.15-14.45 | [Trace-driven simulation of multithreaded applications in gem5](#ElasticSimMATE "wikilink") — [slides](Media:Summit2017_elasticsimmate.pdf "wikilink") |
+| 14.45-15.00 | [Generating Synthetic Traffic for Heterogeneous Architectures](#TraceGeneration "wikilink") — [slides](Media:Summit2017_trace_generation.pdf "wikilink") |
+| 15:00-15:15 | Break |
+| 15:15-16:45 | [System Simulation with gem5, SystemC and other Tools](#SystemC "wikilink") — [slides](Media:Summit2017_systemc.pdf "wikilink") |
+| 15:45-16:00 | [COSSIM: An Integrated Solution to Address the Simulator Gap for Parallel Heterogeneous Systems](#COSSIM "wikilink") — [slides](Media:Summit2017_COSSIM.pdf "wikilink") |
+| 16:00-16:15 | [Simulation of Complex Systems Incorporating Hardware Accelerators](#ComplexSystems "wikilink") — [slides](Media:Summit2017_complex_fs_incorporating_accelerators.pdf "wikilink") |
+| 16:15-16:30 | Break |
+| 16:30-18:15 | Introduction to ARM Research |
+| 18:20-20.00 | Poster Session & Pre-Dinner Drinks |
+| 20.00-21.30 | Buffet Dinner |
+
+# Talks
+
+<span id="ElasticSimMATE">
+
+## Trace-driven simulation of multithreaded applications in gem5
+
+The gem5 modular simulator provides a rich set of CPU models which
+permits balancing simulation speed and accuracy. The growing interest in
+using gem5 for design-space exploration however requires higher
+simulation speeds so as to enable scalability analysis with systems
+comprising tens to hundreds of cores. One relevant approach for enabling
+significant speedups lies in using trace-driven simulation, in which CPU
+cores are abstracted away thereby enabling to refocus simulation effort
+on memory/interconnect subsystems which play a key role on performance.
+This talk describes some of the work carried out on the Mont-Blanc
+european projects on trace-driven simulation and discusses the related
+challenges for multicore architectures in which trace injection requires
+to account for the API synchronization of the underlying running
+application. The ElasticSimMATE tool is presented as an initiative
+towards combining Elastic Traces and SimMATE so as to enable fast and
+accurate simulation of multithreaded applications on ARM multicore
+systems.
+
+> **Dr Gilles Sassatelli** is a CNRS senior scientist at LIRMM, a
+> CNRS-University of Montpellier academic research unit with a staff of
+> over 400. He is vice-head of the microelectronics department and leads
+> a group of 20 researchers working in the area of smart embedded
+> digital systems. He has authored over 200 peer-reviewed papers and has
+> occupied key roles in a number of international conferences. Most of
+> his research is conducted in the frame of international EU-funded
+> projects such as the DreamCloud and Mont-Blanc projects.
+
+> **Alejandro Nocua** received the Ph.D. degree in Microelectronics from
+> the University of Montpellier, France, in 2016. Currently, he is a
+> postdoctoral researcher at the French National Center for Scientific
+> Research (CNRS). His research interests include the analysis of
+> high-performance and energy-efficiency design methodologies. He
+> received his Master degree in Science from the National Institute of
+> Astrophysics, Optics and Electronics (INAOE), Mexico, in 2013.
+> Alejandro was awarded his BS degree in Electronics Engineering from
+> Industrial University of Santander (UIS), Colombia in 2011.
+
+> **Florent Bruguier** received the M.S. and Ph.D. degrees in
+> microelectronics from the University of Montpellier, France, in 2009
+> and 2012, respectively. From 2012 to 2015, he was a Scientific
+> Assistant with the Montpellier Laboratory of Informatics, Robotics,
+> and Microelectronics, University of Montpellier. Since 2015, he is a
+> Permanent Associate Professor. He has co-authored over 30
+> publications. His research interests are focused on self-adaptive and
+> secure approaches for embedded systems.
+
+> **Anastasiia Butko**, Ph.D. is a Postdoctoral Fellow in the
+> Computational Research Division at Lawrence Berkeley National
+> Laboratory (LBNL), CA. Her research interests lie in the general area
+> of computer architecture, with particular emphasis on high-performance
+> computing, emerging and heterogeneous technologies, associated
+> parallel programming and architectural simulation techniques. Broadly,
+> her reasearch addresses the question of how alternative technologies
+> can provide continuing performance scaling in the approaching
+> Post-Moore’s Law era. Her primary research projects include
+> development of the EDA tools for fast superconducting logic design,
+> development of the classical ISA for quantum processor control,
+> development of the fast and flexible System-on-Chip generators using
+> Chisel DSL. Dr. Butko co-leads Open Source Supercomputing project and
+> is a technical committee member of the RISC-V foundation.
+>
+> Dr. Butko received her Ph.D. in Microelectronics from the University
+> of Montpellier, France (2015). Her doctoral thesis developed fast and
+> accurate simulation techniques for many-core architectures
+> exploration. Her graduate work has been conducted within the European
+> project MontBlanc, which aims to design a new supercomputer
+> architecture using low-power embedded technologies.
+>
+> Dr. Butko received her MSc. Degree in Microelectronics from UM2,
+> France and MSc and BSc Degrees in Digital Electronics from NTUU "KPI",
+> Ukraine. During her Master she participated on the international
+> program of double diploma between Montpellier and Kiev universities.
+
+</span>
+
+<span id="Ruby">
+
+## Modeling Cache Coherence with gem5
+
+Correctly implementing cache coherence protocols is hard and these
+implementation details can affect the system's performance. Therefore,
+it is important to robustly model the detailed cache coherence
+implementation. The popular computer architecture simulator gem5 uses
+Ruby as its cache coherence model providing higher fidelity cache
+coherence modeling than many other simulators.
+
+In this talk, I will give a brief overview of Ruby, including SLICC: the
+domain-specific language Ruby uses to specify cache protocols. I will
+show the extreme flexibility of this model and details of a simple cache
+coherence protocol. After this talk, you will be able to dive in and
+begin writing your own coherence protocols\!
+
+> **Jason Lowe-Power** is an Assistant Professor at University of
+> California, Davis in the Computer Science department. Jason's research
+> focuses on increasing the energy efficiency and performance of
+> end-to-end applications like analytic database operations used by
+> Amazon, Google, Target, etc. One important aspect of this research is
+> adding hardware mechanisms to systems that enable all programmers to
+> use emerging hardware accelerators like GPUs. Additionally, Jason is a
+> leader of the open-source architectural simulator, gem5, used by over
+> 1500 academic papers. Jason received his PhD from University of
+> Wisconsin-Madison in Summer 2017. He was awarded the Wisconsin
+> Distinguished Graduate Fellowship Cisco Computer Sciences Award in
+> 2014 and 2015.
+
+</span>
+
+<span id="Garnet2">
+
+## A Detailed On-Chip Network Model inside a Full-System Simulator
+
+Compute systems are ubiquitous, with form factors ranging from
+smartphones at the edge to datacenters in the cloud. Chips in all these
+systems today comprise 10s to 100s of homogeneous/heterogeneous cores or
+processing elements. The growing emphasis on parallelism, distributed
+computing, heterogeneity, and energy-efficiency across all these systems
+makes the design of the Network-on-Chip (NoC) fabric connecting the
+cores critical to both high-performance and low power consumption.
+
+It is imperative to model the details of the NoC when architecting and
+exploring the design-space of a complex many-core system. If ignored, an
+inaccurate NoC model could lead to over-design or under-design due to
+incorrect trade-off choices, causing performance losses at runtime. To
+this end, we have designed and integrated a detailed on-chip network
+model called Garnet inside the gem5 (www.gem5.org) full-system
+architectural simulator which is being used extensively by both industry
+and academia. Together with Garnet, gem5 provides plug-and-play models
+of cores, caches, cache coherence protocols, NoC, memory controller, and
+DRAM, with varying levels of details, enabling computer architects and
+designers to trade-off simulation speed and accuracy.
+
+In this talk, we will first introduce the basic building blocks of NoCs
+and present the state-of-the-art used in chips today. We will then
+present Garnet, and demonstrate how it faithfully models the
+state-of-the-art, while also offering immense flexibility in modifying
+various parts of the microarchitecture to serve the needs of both
+homogeneous many-cores and heterogeneous accelerator-based systems of
+the future via case studies and code-snippets. Finally, we will
+demonstrate how Garnet works within the entire gem5 ecosystem.
+
+> **Tushar Krishna** is an Assistant Professor in the Schools of ECE and
+> CS at Georgia Tech. He received a Ph.D. in Electrical Engineering and
+> Computer Science from the Massachusetts Institute of Technology in
+> 2014. Prior to that he received a M.S.E from Princeton University in
+> 2009, and a B.Tech from the Indian Institute of Technology (IIT) Delhi
+> in 2007, both in Electrical Engineering.
+>
+> Before joining Georgia Tech in 2015, Dr. Krishna was a post-doctoral
+> researcher in the VSSAD Group at Intel, Massachusetts, and then at the
+> Singapore-MIT Alliance for Research and Technology at MIT.
+>
+> Dr. Krishna's research interests are in computer architecture,
+> interconnection networks, networks-on-chip, deep learning
+> accelerators, and FPGAs.
+
+</span>
+
+<span id="SystemC">
+
+## System Simulation with gem5, SystemC and other Tools
+
+SystemC TLM based virtual prototypes have become the main tool in
+industry and research for concurrent hardware and software development,
+as well as hardware design space exploration. However, there exists a
+lack of accurate, free, changeable and realistic SystemC models of
+modern CPUs. Therefore, many researchers use the cycle accurate open
+source system simulator gem5, which has been developed in parallel to
+the SystemC standard. In this tutorial we present the coupling of gem5
+with SystemC that offers full interoperability between both simulation
+frameworks, and therefore enables a huge set of possibilities for system
+level design space exploration. Furthermore, we show several examples
+for coupling gem5 with SystemC and other tools.
+
+> **Matthias Jung** received his PhD degree in Electrical Engineering
+> from the University of Kaiserslautern Germany in 2017. His research
+> interest are SystemC based virtual prototypes, especially with the
+> focus on the modeling of memory systems and memory controller design.
+> Since may 2017 he is a researcher at Fraunhofer IESE, Kaiserslautern,
+> Germany.
+
+> **Christian Menard** received a Diploma degree in Information Systems
+> Technology from TU Dresden in Germany in 2016 and joined the chair for
+> compiler construction as a Ph.D. student within the excellence cluster
+> cfaed in TU Dresden. His current research includes system-level
+> modeling of widely heterogeneous hardware as well dataflow compilers
+> for heterogeneous MPSoC platforms.
+
+</span>
+
+<span id="PowMon">
+
+## CPU power estimation using PMCs and its application in gem5
+
+Fast and accurate estimation of CPU power consumption is necessary to
+inform run-time power management approaches and allow effective design
+space exploration. Power simulators, combined with a full-system
+architectural simulator such as gem5, enable power-performance
+trade-offs to be investigated early in the design of a system. However,
+the accuracy of existing power simulators is known to be low, and this
+can lead to incorrect conclusions being made. In this talk, I will
+present our statistically rigorous methodology for building accurate
+run-time power models using Performance Monitoring Counters (PMCs) for
+mobile and embedded devices, and demonstrate how our models make more
+efficient use of limited training data and better adapt to unseen
+scenarios by uniquely considering stability. Models built using the
+methodology for both ARM Cortex-A7 and Cortex-A15 CPUs exhibit a 3.8%
+and 2.8% average error respectively. I will also present online
+resources that we have made available from the work, including software
+tools, documentation, raw data and further results. I will also present
+results from an investigation into the correlation between gem5 activity
+statistics and hardware PMCs. Based on this, a gem5 power model for a
+simulated quadcore ARM Cortex-A15 has been created, built using the
+above methodology, and its accuracy compared against experimental
+results obtained from hardware.
+
+> **Geoff Merrett** is an Associate Professor in the Department of
+> Electronics and Computer Science at the University of Southampton. He
+> received the BEng (1st, Hons) and PhD degrees in Electronic
+> Engineering from Southampton in 2004 and 2009 respectively. His
+> research interests are in energy-aware and self-powered computing
+> systems, with application across the spectrum from highly constrained
+> IoT devices to many-core mobile and embedded systems. He has published
+> over 100 peer-reviewed articles in these areas, and given invited
+> talks at a number of international events. Dr Merrett is a
+> Co-Investigator on the EPSRC-funded £5.6M PRiME Programme Grant (where
+> he leads the applications and cross-layer interaction theme),
+> "Continuous on-line adaptation in many-core systems: From graceful
+> degradation to graceful amelioration", and deputy-lead on the
+> "Wearable and Autonomous Computing for Future Smart Cities" Platform
+> Grant. He is technical manager of Southampton’s ARM-ECS Research
+> Centre, an award-winning industry-academia collaboration between the
+> University of Southampton and ARM. He coordinates IoT research at the
+> University, and leads the wireless sensing theme of its Pervasive
+> Systems Centre. He is an Associate Editor for the IET CDS journal,
+> serves as a reviewer for a number of leading journals, and on TPCs for
+> a range of conferences. He co-manages the UK’s Energy Harvesting
+> Network, was General Chair of the ACM Workshop on Energy-Harvesting
+> and Energy-Neutral Sensing Systems in 2013, 2014, and 2015, and was
+> the General Chair of the European Workshop on Microelectronics
+> Education 2016. He is a member of the IEEE, IET and Fellow of the HEA.
+
+</span>
+
+# Short Talks
+
+<span id="JIT_Debugging">
+
+## Debugging a target-agnostic JIT compiler with GEM5
+
+**Author:** Boris Shingarov - LabWare
+
+We explain how GEM5 enabled us to develop a target-agnostic JIT
+compiler, in which no knowledge about the target ISA is coded by the
+human programmer; instead, the backend is inferred, using logic
+programming, from a formal machine description written in a Processor
+Description Language. Debugging such a JIT presents some challenges
+which can not be addressed using traditional approaches. One such
+challenge is the impedance mismatch between the high-level abstractions
+in the PDL and the low-level inferred implementation. In this talk, we
+present a new debugger based on simulating the execution of the target
+runtime VM in GEM5; the debugger frontend connects to this simulation
+using the RSP wire protocol.
+</span>
+
+<span id="COSSIM">
+
+## COSSIM: An Integrated Solution to Address the Simulator Gap for Parallel Heterogeneous Systems
+
+In an era of complex networked heterogeneous systems, simulating
+independently only parts, components or attributes of a
+system-under-design is not a viable, accurate or efficient option. The
+interactions are too many and too complicated to produce meaningful
+results and the optimization opportunities are severely limited when
+considering each part of a system in an isolated manner. COSSIM offers a
+framework that can handle the simulation of a complete system-of-systems
+including processors, peripherals and networks that can appeal to
+Parallel (Heterogeneous) Systems designers and application developers in
+an integrated way.
+
+The framework is based on gem5 as the main simulation engine for
+processor-based systems and extends its capabilities by integrating it
+with the OMNET++ network simulator. This integration allows independent
+gem5 instances to be networked with all network protocols and
+hierarchies that can be supported by OMNET++, thus creating a very
+flexible solution. The integration of the two main simulation tools is
+realized through the IEEE 1516 High-Level Architecture standard (HLA),
+through which all communication tasks are performed. Through HLA and
+custom libraries, a two-level (per node and global) synchronization
+scheme is also implemented to ensure a coherent notion of time between
+all nodes.
+
+Since HLA is IP-based all gem5 instances and OMNET++ can be executed on
+the same physical machine or on any distributed system (or any
+combination in between). The overall framework – the set of gem5 nodes,
+the OMNET++ simulator and the CERTI HLA – are integrated in a unified
+Eclipse-based GUI that has been developed to provide easy simulation
+set-up, execution and visualization of results. McPAT is also integrated
+in a semi-automated way through the GUI in order to provide power and
+energy estimations for each node, while OMNET++ provides power
+estimations for networking-related components (NICs and network
+devices).
+
+> **Andreas Brokalakis** is a senior hardware engineer at Synelixis
+> Solutions Ltd. At the same time he is pursuing a PhD degree at the
+> Technical University of Crete, Greece. He holds a Bachelor degree in
+> Computer Engineering from University of Patras, Greece and a Master’s
+> Degree on Hardware/Software Co-design from the same university.
+> Current work and research interests involve computer architecture and
+> arithmetic, as well as design of ASIC and FPGA systems and
+> accelerators.
+
+> **Nikolaos Tampouratzis** is a PhD student at Technical University of
+> Crete, working on simulation tools for computing systems. He has
+> joined Telecommunication Systems Institute, Technical University of
+> Crete since October 2012 as a research associate, providing research
+> and development services to several EU-funded research projects. He
+> received his Computer Science diploma from the University of Crete
+> (UOC, Greece), with specialization in Hardware Design and FPGAs. He
+> continued his studies in the Technical University of Crete (TUC
+> Greece) where he received his Master Diploma in Electronic and
+> Computer Engineering in which he specialized in Computer Architecture
+> and Hardware Design.
+
+</span>
+
+<span id="ComplexSystems">
+
+## Simulation of Complex Systems Incorporating Hardware Accelerators
+
+The breakdown of Dennard scaling coupled with the persistently growing
+transistor counts increased the importance of application-specific
+hardware acceleration; such an approach offers significant performance
+and energy benefits compared to general-purpose solutions. In order to
+thoroughly evaluate such architectures, the designer should perform a
+quite extensive design space exploration so as to evaluate the
+trade-offs across the entire system. The design, until recently, has
+been predominantly done using Register Transfer Level languages such as
+Verilog and VHDL, which, however, lead to a prohibitively long and
+costly design effort. In order to reduce the design time a wide range of
+both commercial and academic High-Level Synthesis (HLS) tools have
+emerged; most of these tools, handle hardware accelerators that are
+described in synthesizable SystemC. The problem today, however, is that
+most simulators used for evaluating the complete user applications (i.e.
+full-system CPU/Mem/Peripheral simulators) lack any type of SystemC
+accelerator support.
+
+Within this context, we extend gem5 to support the simulation of generic
+SystemC accelerators. We introduce a novel flow that enables us to
+rapidly prototype synthesisable SystemC hardware accelerators in
+conjunction with gem5. The proposed solution handles automatically all
+communication and synchronisation issues.
+
+Compared to a standard gem5 system, several changes at different levels
+are required, from the OS and device drivers level down to the
+implementation of a device model in the gem5 simulator. Instead of using
+files to write data for an external accelerator, perform the simulation
+and then read back the results, our approach communicates with the
+SystemC simulator through programmed I/Os and DMA engines, supporting
+full global synchronisation. Apart from the apparent benefits concerning
+the implementation and simulation accuracy, the proposed solution is
+also orders of magnitude faster.
+
+> **Nikolaos Tampouratzis** is a PhD student at Technical University of
+> Crete, working on simulation tools for computing systems. He has
+> joined Telecommunication Systems Institute, Technical University of
+> Crete since October 2012 as a research associate, providing research
+> and development services to several EU-funded research projects. He
+> received his Computer Science diploma from the University of Crete
+> (UOC, Greece), with specialization in Hardware Design and FPGAs. He
+> continued his studies in the Technical University of Crete (TUC
+> Greece) where he received his Master Diploma in Electronic and
+> Computer Engineering in which he specialized in Computer Architecture
+> and Hardware Design.
+
+</span>
+
+<span id="TraceGeneration">
+
+## Generating Synthetic Traffic for Heterogeneous Architectures
+
+Modern system-on-chip architectures consist of many heterogeneous
+processing elements. The communication fabric and memory hierarchy
+supporting these processing elements heavily influence the system’s
+overall performance. Exploring the design space of these heterogeneous
+architectures with detailed models of each processing element can be
+time-consuming. Statistical simulation has been shown to be an effective
+tool for quickly evaluating architectures by abstracting away
+complexity.
+
+This talk describes work done on modelling the spatial and temporal
+behaviour of a processing element’s address stream. We present a
+methodology that can automatically characterize a processing element by
+observing its reads and writes. Using these characteristics we can
+stimulate a communication fabric connecting many different processing
+elements by synthetically recreating their addresses. These addresses
+arrive at their destination in the memory hierarchy, spawning new
+messages and responses to read and write requests. Architects can now
+combine ynthetic processing elements that represent various different
+components on current and future systems-on-chip to evaluate the impact
+of changes at the interconnection network and memory hierarchy.
+
+> **Mario Badr** is a PhD Candidate at the University of Toronto working
+> under the supervision of Dr. Natalie Enright Jerger. He received his
+> B.A.Sc. and M.A.Sc from the University of Toronto in Electrical
+> Engineering and Computer Engineering, respectively. He has interned
+> with Qualcomm Research Silicon Valley and received the Roberto
+> Padovani Scholarship for his outstanding technical contributions. In
+> addition, he has been recognized at the university and departmental
+> levels for excellence as a teaching assistant. His research interests
+> include performance evaluation in computer architecture, heterogeneous
+> architectures, and multi-threaded workloads.
+
+</span>
+
+<span id="StarterKit">
+
+## ARM Research Starter Kit: System Modeling using gem5
+
+ARM Research Enablement aims to enhance computing research by enabling
+researchers worldwide to easily access ARM-based IP and technologies,
+and helping them to increase their research impact. As a part of our
+research enablement activities, we provide a System Modeling Research
+Starter Kit using gem5. We have released a High Performance In-order
+(HPI) CPU timing model based on ARMv8-A in gem5. I will present a
+high-level overview of the released system, its documentation and
+benchmark scripts. This talk will target those who are new to gem5 as
+well as those who would like to promote gem5 in research.
+
+> **Ashkan Tousi** is a Senior Research Engineer at ARM Cambridge and an
+> Honorary Lecturer at the University of Glasgow. He received his PhD in
+> computing science (parallel computing) in 2015. He currently leads
+> research enablement activities at ARM, which cover a range of
+> different research areas from SoC design to IoT and data science.
+
+</span>
+
+<span id="WA">
+
+## Interacting with gem5 using workload-automation & devlib
+
+Running workloads on gem5 is often not straightforward. This talk will
+discuss workload-automation and devlib, 2 new open-source tools to
+interact with gem5. These frameworks, written to interact with various
+hardware platforms, have recently been extended to include gem5 as a
+platform. We will discuss use cases and advantages/disadvantages of each
+tool and show how they can make your gem5 work easier.
+
+> **Anouk Van Laer** is a Modelling Engineer in Architecture: Systems &
+> Technology group at ARM. She obtained her PhD at University College
+> London, where she investigated the effects of optical interconnects on
+> the performance of chip multiprocessors, using gem5.
+
+</span>
+
+<span id="PowerFramework">
+
+## gem5: empowering the masses
+
+This talk will give an overview of the state of power modelling in gem5.
+After discussing the basic power modelling infrastructure, it will cover
+the state of CPU DVFS as well as recent improvements in how CPU power
+states are controlled for the ARM architecture in gem5. The talk will
+cover these improvements in power modelling, highlighting the way in
+which the accuracy and versatility of the simulator have been improved.
+
+> **Sascha Bischoff** is a Senior Software Engineer in the Architecture:
+> Systems & Technology group at ARM in Cambridge. Whilst completing his
+> PhD with the University of Southampton, he spent 3.5 years based in
+> ARM Research in Cambridge. He has spent a large part of the last 6
+> years working with gem5, typically with a focus on power management,
+> ideally without impacting the delivered
+performance.
+
+</span>
+
+<span id="DRAMPower">
+
+## Integrating and quantifying the impact of low power modes in the DRAM controller in gem5
+
+Across applications, DRAM is a significant contributor to the overall
+system power, with the DRAM access energy per bit up to three orders of
+magnitude higher compared to on-chip memory accesses. To improve the
+power efficiency, DRAM technology incorporates multiple low power modes,
+each with different trade-offs between achievable power savings and
+performance impact due to entry and exit delay requirements. Accurate
+modeling of these low power modes and entry and exit control is crucial
+to analyze the trade-offs across controller configurations and workloads
+with varied memory access characteristics.
+
+In this talk, we will give an overview of the decision making logic we
+added to the DRAM controller in gem5 that triggers transitions to/from
+the power-down modes. Integrating this functionality makes gem5 the
+first publicly available DRAM low power full-system simulator, providing
+the research community a tool for DRAM power analysis for a breadth of
+use cases. We will conclude with simulation data that characterises the
+low power behaviour and shows energy and performance trade-offs for
+realistic workloads.
+
+**Note:** This talk is based on a paper accepted at MEMSYS 17. Authors
+from ARM: Radhika Jagtap, Wendy Elsasser and Andreas Hansson. Authors
+from University of Kaiserslautern: Matthias Jung and Norbert Wehn.
+
+> **Radhika Jagtap** is a Senior Research Engineer working in the Memory
+> & Systems research group. She has plenty of experience with gem5
+> (elastic traces, interconnect, memory controller) and is involved in
+> several collaborative research projects, especially with academics.
+> Currently she is exploring the problem of energy efficient data
+> movement for sparse data workloads.
+
+</span>
+
diff --git a/_pages/events/asplos-2008.md b/_pages/events/asplos-2008.md
new file mode 100644
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--- /dev/null
+++ b/_pages/events/asplos-2008.md
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+---
+title: "ASPLOS 2008"
+date: 2018-05-13T18:51:37-04:00
+draft: false
+weight: 1000
+---
+
+Using the M5 Simulator ASPLOS 2008 Tutorial Sunday March 2nd, 2008
+
+## Introduction
+
+This half-day tutorial will introduce participants to the [M5 simulator
+system](Main_Page "wikilink"). M5 is a modular platform for computer
+system architecture research, encompassing system-level architecture as
+well as processor microarchitecture.
+
+We will be discussing version 2.0 of the M5 simulator and specifically
+its new features including:
+
+ - Multiple ISA support (Alpha, ARM, MIPS, and SPARC)
+ - An execute-in-execute out-of-order SMT CPU timing model, with no
+ SimpleScalar license encumbrance
+ - Message-oriented interface for memory system objects, designed to
+ simplify the development of non-bus interconnects
+ - New caches models that are easier to modify
+ - New multi-level bus-based coherence protocol
+ - More extensive Python integration and scripting support
+ - Performance improvements
+ - Generating checkpoints for simpoints
+
+
+
+Because the primary focus of the M5 development team has been simulation
+of network-oriented server workloads, M5 incorporates several features
+not commonly found in other simulators.
+
+ - Full-system simulation using unmodified Linux 2.4/2.6, FreeBSD, or
+ Solaris (More are on the way)
+ - Detailed timing of I/O device accesses and DMA operations
+ - Accurate, deterministic simulation of multiple networked systems
+ - Flexible, script-driven configuration to simplify specification of
+ complex multi-system configurations
+ - Included network workloads such as Apache, NAT, and NFS
+ - Support for storing results from multiple simulations in a unified
+ database (e.g. MySQL) for automated reporting and graph generation
+
+M5 also integrates a number of other desirable features, including
+pervasive object orientation, multiple interchangeable CPU models, an
+event-driven memory system model, and multiprocessor capability.
+Additionally, M5 is also capable of application-only simulation using
+syscall emulation.
+
+M5 is freely distributable under a BSD-style license, and does not
+depend on any commercial or restricted-license software.
+
+## Intended Audience
+
+Researchers in academia or industry looking for a free, open-source,
+full-system simulation environment for processor, system, or platform
+architecture studies. Please register via the
+[ASPLOS 2008](http://research.microsoft.com/asplos08/registration.htm)
+web page.
+
+## Tentative Topics
+
+The following topics will be discussed in detail during the tutorial:
+
+ - M5 structure
+ - Object structures
+ - Specifying configurations
+ - Object serialization (checkpoints)
+ - Events
+ - CPU models
+ - Memory/Cache models
+ - I/O devices
+ - Full-system modeling
+ - Statistics
+ - Debugging techniques
+ - ISA description language
+ - Future directions
+
+## Speakers
+
+ - Ali G. Saidi is a Ph.D. candidate in the EECS Department at the
+ University of Michigan, and wrote much of the platform code for
+ Linux full-system simulation. He received a BS in electrical
+ engineering from the University of Texas at Austin and an MSE in
+ computer science and engineering from the University of Michigan.
+
+<!-- end list -->
+
+ - Steven K. Reinhardt is an associate professor in the EECS Department
+ at the University of Michigan, and a principal developer of M5. He
+ received a BS from Case Western Reserve University and an MS from
+ Stanford University, both in electrical engineering, and a PhD in
+ computer science from the University of Wisconsin-Madison. While at
+ Wisconsin, he was the principal developer of the Wisconsin Wind
+ Tunnel parallel architecture simulator.
+
+<!-- end list -->
+
+ - Nathan L. Binkert is currently a Senior Research Scientist with HP
+ Labs and a principal developer of M5. He received a BSE in
+ electrical engineering and an MS and a PhD in computer science both
+ from the University of Michigan. As an intern at Compaq VSSAD, he
+ was a principal developer of the ASIM simulator, currently in
+ widespread use at Intel.
+
+<!-- end list -->
+
+ - Steve Hines is a Ph.D. candidate in the CS Department at Florida
+ State University, and created the ARM port of M5. He received a BS
+ from Illinois Institute of Technology and an MS from Florida State
+ University.
+
+__NOTOC__
+
diff --git a/_pages/events/asplos-2017.md b/_pages/events/asplos-2017.md
new file mode 100644
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--- /dev/null
+++ b/_pages/events/asplos-2017.md
@@ -0,0 +1,57 @@
+---
+title: "ASPLOS 2017"
+date: 2018-05-13T18:51:37-04:00
+draft: false
+---
+
+Architectural Exploration with gem5
+
+# Abstract
+
+This tutorial will give a brief introduction to gem5 for computer
+engineers who are new to gem5. The attendees will learn what gem5 can
+and can not do, how to use and extend gem5, as well as how to contribute
+back to gem5.
+
+# Target Audience
+
+The primary audience is junior computer architecture engineers (e.g.,
+first or second year graduate students, as well as junior engineers) who
+are planning on using gem5 for future architecture research. We also
+invite others who want a high-level idea of how gem5 works and its
+applicability to architecture research.
+
+The tutorial is free to attend (no registration fee required),
+registration is required via ASPLOS.
+
+Prerequisites: Attendees are expected to have a working knowledge of
+C++, Python, and computer systems.
+
+# Slides
+
+The slides from the tutorial can be downloaded
+[here](:file:ASPLOS2017_gem5_tutorial.pdf "wikilink").
+
+# Schedule
+
+The tutorial is scheduled on the Sunday afternoon 9th April 2017 at The
+Westin Xi'an hotel.
+
+| Topic | Time |
+| --------------------------------------- | ----------- |
+| Introduction | 13:00-13:10 |
+| Getting started with gem5 | 13:10-13:30 |
+| Advanced configurations | 13:30-13:55 |
+| Debug & Trace | 13:55-14:05 |
+| Creating SimObjects | 14:05-14:30 |
+| |
+| Break | 14:30-15:00 |
+| Introduction to memory subsystems | 15:00-15:45 |
+| Introduction to CPU models | 15:45-16:10 |
+| Advanced gem5 features and capabilities | 16:10-16:40 |
+| How to contribute to gem5 | 16:40-17:00 |
+
+# Presenters
+
+This tutorial is organised by Andreas Sandberg, Stephan Diestelhorst and
+William Wang of ARM Research
diff --git a/_pages/events/dist-gem5.md b/_pages/events/dist-gem5.md
new file mode 100644
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--- /dev/null
+++ b/_pages/events/dist-gem5.md
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+---
+title: "ISCA2017 - distributed gem5"
+date: 2018-05-13T17:02:19-04:00
+draft: false
+weight: 10
+---
+
+<big>
+
+<center>
+
+**Title: dist-gem5: Modeling and Simulating a Distributed Computer
+System Using Multiple Simulation**
+
+**Sunday, June 25, 9:00 to 12:30**
+
+**`44th`` ``International`` ``Symposium`` ``on`` ``Computer``
+``Architecture,`` ``June`` ``24-28,`` ``2017,`` ``Toronto,`` ``ON,``
+``Canada`**
+
+</center>
+
+</big>
+
+-----
+
+__TOC__
+
+## List of organisers/presenters
+
+ - Nam Sung Kim, University of Illinois, Urbana-Champaign
+ - Mohammad Alian, University of Illinois, Urbana-Champaign
+ - Nikos Nikoleris, ARM Ltd.
+ - Radhika Jagtap, ARM Ltd.
+ - Gabor Dozsa, ARM Ltd.
+ - Stephan Diestelhorst, ARM Ltd.
+
+## Abstract
+
+The single-thread performance improvement of processors has been
+sluggish for the past decade as Dennard’s scaling is approaching its
+fundamental physical limit. Thus, the importance of efficiently running
+applications on a **parallel/distributed computer system** has continued
+to increase and diverse applications based on parallel/distributed
+computing models such as MapReduce and MPI have thrived.
+
+In a parallel/distributed computing system, the complex interplay
+amongst processor, node, and network architectures strongly affects the
+performance and power efficiency. In particular, we observe that all the
+hardware and software aspects of the network, which encompasses
+interface technology, switch/router capability, link bandwidth,
+topology, traffic patterns, and protocols, significantly impact the
+processor and node activities. Therefore, to maximize performance and
+power efficiency, it is critical to develop various optimization
+strategies cutting across processor, node, and network architectures, as
+well as their software stacks, necessitating **full-system simulation**.
+However, our community lacks a proper research infrastructure to study
+the interplay of these subsystems. Facing such a challenge, we have
+released a gem5-based simulation infrastructure dubbed **dist-gem5** to
+support full-system simulation of a parallel/distributed computer system
+using multiple simulation host. This tutorial will cover an introduction
+to dist-gem5 including relevant background knowledge.
+
+## Objectives
+
+![Packet-forwarding-highlevel.png](Packet-forwarding-highlevel.png
+"Packet-forwarding-highlevel.png")
+
+More specifically, the tutorial will provide the following.
+
+ - Introduction of parallel/distributed system architecture.
+ - Details of enhanced gem5 components to enable simulation of a
+ parallel/distributed computer system.
+ - Network interface and switch models to connect multiple
+ simulated nodes (as shown in the Figure).
+ - Synchronization amongst multiple simulated nodes running across
+ multiple simulation hosts.
+ - Simulating a region of interest of a given benchmark using
+ check-point creation/restoration enhanced for simulating
+ multiple simulated nodes using multiple simulation hosts.
+ - Examples of modeling parallel/distributed computer systems using a
+ few network topologies.
+
+| | |
+| ------------- | ---------------------------- |
+| 09:00 – 10:00 | Introduction (60 min) |
+| 10:00 – 10:15 | Break (15 min) |
+| 10:15 – 11:15 | dist-gem5 deep dive (60 min) |
+| 11:15 – 11:30 | Break (15 min) |
+| 11:30 – 12:00 | dist-gem5 examples (30 min) |
+
+Program for the tutorial
+
+## Slides
+
+ - The slides from the tutorial can be downloaded
+ [here](:file:isca2017-dist-gem5.pdf "wikilink").
+
+## Publications
+
+ - Mohammad Alian, Gabor Dozsa, Umur Darbaz, Stephan Diestelhorst,
+ Daehoon Kim, and Nam Sung Kim. *“dist-gem5: Distributed Simulation
+ of Computer Clusters”*, IEEE International Symposium on Performance
+ Analysis of Systems (ISPASS), April 2017 (Nominated for the Best
+ Paper Award)
+
+<!-- end list -->
+
+ - Mohammad Alian, Daehoon Kim, and Nam Sung Kim. *“pd-gem5: Simulation
+ Infrastructure for Parallel/Distributed Computer Systems”*, IEEE
+ Computer Architecture Letters (CAL), Jan 2016
+ [paper](http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7114236)
+
+<!-- end list -->
+
+ - [**dist-gem5 website**](https://publish.illinois.edu/icsl-pdgem5/)
+
+## Pre-requisites
+
+ - Basic knowledge of computer architecture
+ - No prior experience with simulators is required
+
+## Previous tutorials
+
+ - [dist-gem5 tutorial at
+ MICRO 2015](https://publish.illinois.edu/icsl-pdgem5/micro-48-tutorial/)
+ - [gem5 tutorial at ASPLOS 2017](http://gem5.org/ASPLOS2017_tutorial)
diff --git a/_pages/events/ics-2018.md b/_pages/events/ics-2018.md
new file mode 100644
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--- /dev/null
+++ b/_pages/events/ics-2018.md
@@ -0,0 +1,63 @@
+---
+layout: page
+title: "ISC-2018 Vector Architecture Exploration"
+parent: events
+---
+
+# Vector Architecture Exploration with gem5 (Arm)
+
+## Abstract
+
+The Arm Scalable Vector Extension (SVE) is a key enabling technology to
+accelerate HPC and machine learning workloads on future Arm-based
+processors. SVE does not set a specific vector length, which is
+microarchitecture-specific. This vector-length agnosticism increases
+design space complexity and exacerbates the importance of having
+flexible and accurate modeling tools.
+
+gem5 is an open-source full-system microarchitectural simulator that is
+widely used in academia and industry. Arm is a major contributor to gem5
+and has developed and upstreamed many features and models. SVE support
+in gem5 is being finalized to be made publicly available to enable users
+to simulate multi-core architectures with SVE using Arm-provided timing
+models.
+
+This tutorial covers the features of SVE, the trade-offs of designing a
+multi-core that uses vectors, and the publicly available tools to model
+the performance of such vector architectures, with an emphasis on gem5
+with SVE support. In addition to gem5, the tutorial will also cover
+other analysis tools for SVE, such as the Arm Instruction Emulator,
+which will be made available to the participants through docker images
+to provide a quick start in these environments.
+
+## Target Audience
+
+The primary audience are computer architect engineers both in academia
+(e.g., graduate students) and in industry who want to learn about the
+Arm Scalable Vector Extension (SVE) and the Arm tools for SVE, or are
+planning to use gem5 for architecture research, especially if they plan
+to explore Arm vector architectures. The tutorial is also expected to be
+useful as a high-level introduction to gem5 and how it can be used for
+architecture research.
+
+Prerequisites: working knowledge of computer systems, vector
+architectures, C++ and Python is recommended.
+
+## Schedule (tentative)
+
+| Topic | Time |
+| ------------------------------------ | ------ |
+| Introduction | 10 min |
+| The Arm Scalable Vector Extension | 30 min |
+| Vector Architecture Design and Tools | 30 min |
+| Introduction to gem5 | 15 min |
+| |
+| Break | 30 min |
+| gem5 Basics | 45 min |
+| gem5 Advanced Features | 45 min |
+| SVE gem5 Simulation | 30 min |
+| Closing | 5 min |
+
+## Organizers
+
+Tutorial organized by Alex Rico and Jose Joao of Arm
diff --git a/_pages/events/index.md b/_pages/events/index.md
new file mode 100644
index 0000000..fbb9e9d
--- /dev/null
+++ b/_pages/events/index.md
@@ -0,0 +1,141 @@
+---
+layout: toc
+title: "Events"
+parent: events
+permalink: /events/
+---
+* TOC
+{:toc}
+
+We have held a handful of tutorials on M5/gem5s at various conferences. Though
+the material in these tutorials can be out of date, the tutorial
+materials present a more organized (and in some cases more in-depth)
+overview than the wiki documentation. We highly recommend taking a look
+at the most recent tutorial as a complement to the documentation on the
+wiki.
+
+The slides and handouts are the same material except that the handouts
+are formatted with two slides per page.
+
+## ICS 2018: Vector Architecture Exploration with gem5
+
+[Vector Architecture Exploration with
+gem5](ics-2018)
+
+International Conference on Supercomputing, Beijing (China), June 2018
+
+This tutorial covers the Arm Scalable Vector Extension (SVE) and how to
+use gem5 to explore system architecture designs of microarchitectures
+implementing SVE.
+
+## Arm Research Starter Kit on System Modeling using gem5
+
+<https://github.com/arm-university/arm-gem5-rsk>
+
+Getting started instructions and an overview of the HPI model.
+
+## ISCA 45: AMD gem5 APU Model
+
+[AMD gem5 APU Simulator: Modeling GPUs Using the Machine
+ISA](isca-2018)
+
+This tutorial covers the gem5 APU model in detail. In particular, we
+discuss the model's support for executing GPU machine ISA instructions
+and the full user space ROCm stack.
+
+## Arm Research Summit 2017: gem5 workshop
+
+[ARM Research Summit 2017
+Workshop](arm-summit-2017) covers many
+advanced topics in gem5 such as Ruby, Garnet, and SystemC.
+
+## dist-gem5 at ISCA-44 (Toronto, 2017)
+
+dist-gem5 is a gem5-based simulation infrastructure which enables
+full-system simulation of a parallel/distributed computer system using
+multiple simulation hosts.
+
+ - [Tutorial web
+ site](dist-gem5)
+
+## ASPLOS 22
+
+[Full day tutorial on gem5 at
+ASPLOS 2017](asplos-2017)
+
+## HiPEAC Computer Systems Week
+
+This tutorial was held in Gothenburg, Sweden in April 2012. It covers
+gem5 although for information about Ruby you should look at the ISCA 38
+tutorial. We recorded video of the tutorial which is available
+ below.
+
+ - [Slides](http://gem5.org/dist/tutorials/hipeac2012/gem5_hipeac.pdf)
+ - [Overview](http://gem5.org/dist/tutorials/hipeac2012/01.overview.m4v)
+ - [Introduction](http://gem5.org/dist/tutorials/hipeac2012/02.introduction.m4v)
+ - [Basics](http://gem5.org/dist/tutorials/hipeac2012/03.basics.m4v)
+ - [Running
+ Experiments](http://gem5.org/dist/tutorials/hipeac2012/04.running_experiment.m4v)
+ - [Debugging](http://gem5.org/dist/tutorials/hipeac2012/05.debugging.m4v)
+ - [Memory](http://gem5.org/dist/tutorials/hipeac2012/06.memory.m4v)
+ - [CPU
+ Models](http://gem5.org/dist/tutorials/hipeac2012/07.cpu_models.m4v)
+ - [Common
+ Tasks](http://gem5.org/dist/tutorials/hipeac2012/08.common_tasks.m4v)
+ - [Configuration](http://gem5.org/dist/tutorials/hipeac2012/09.configuration.m4v)
+ - [Conclusion](http://gem5.org/dist/tutorials/hipeac2012/10.conclusions.m4v)
+
+## ISCA 38
+
+This tutorial, held in June 2011 at ISCA-38, it covered gem5 (the merger
+between M5 and GEMS). It was extremely well attended with 65 people
+participating.
+
+[ISCA 2011](isca-2011)
+
+ - [Slides](http://www.gem5.org/dist/tutorials/isca_pres_2011.pdf)
+ - Podcasts/video coming soon provided there are no technical
+ difficulties
+
+## ASPLOS-13
+
+This tutorial, held in March 2008 at ASPLOS XIII in Seattle, covered M5
+2.0 and included several small examples on creating SimObjects and
+adding parameters.
+
+ - [Slides](http://www.m5sim.org/dist/tutorials/asplos_pres.pdf)
+ - [Handouts](http://www.m5sim.org/dist/tutorials/asplos_hand.pdf)
+ - Video
+ - [Introduction](http://www.m5sim.org/dist/tutorials/introduction.mov)
+ -- A brief overview of M5, its capabilities and concepts
+ - [Running](http://www.m5sim.org/dist/tutorials/running.mov) --
+ How to compile and run M5
+ - [Full
+ System](http://www.m5sim.org/dist/tutorials/fullsystem.mov) --
+ Full system benchmarks, disk images, and scripts
+ - [Objects](http://www.m5sim.org/dist/tutorials/objects.mov) -- An
+ overview of the various object models that are available out of
+ the box
+ - [Extending](http://www.m5sim.org/dist/tutorials/extending.mov)
+ -- M5 internals, defining new objects & parameters, statistics,
+ ISA descriptions, ARM & X86 support, future development
+ - [Debugging](http://www.m5sim.org/dist/tutorials/debugging.mov)
+ -- Facilities in M5 to aid debugging
+ - [Description](asplos-2008)
+
+## ISCA-33
+
+This tutorial, held in June 2006 at ISCA 33 in Boston, was the first one
+to cover M5 2.0.
+
+ - [Slides](http://www.m5sim.org/dist/tutorials/isca_pres.pdf)
+ - [Handouts](http://www.m5sim.org/dist/tutorials/isca_hand.pdf)
+ - [Description](isca-2006)
+
+## ISCA-32
+
+Our first tutorial, held in June 2005 at ISCA 32 in Madison, is rather
+dated as it covered M5 1.X and not 2.0.
+
+ - [Slides](http://www.m5sim.org/dist/tutorials/tutorial.ppt)
+ - [Handouts](http://www.m5sim.org/dist/tutorials/tutorial.pdf)
diff --git a/_pages/events/isca-2006.md b/_pages/events/isca-2006.md
new file mode 100644
index 0000000..397c6b4
--- /dev/null
+++ b/_pages/events/isca-2006.md
@@ -0,0 +1,146 @@
+---
+layout: page
+title: "ISCA 2006"
+parent: event
+---
+
+Using the M5 Simulator ISCA 2006 Tutorial Sunday June 18th, 2006
+
+## Introduction
+
+This half-day tutorial will introduce participants to the [M5 simulator
+system](Main_Page "wikilink"). M5 is a modular platform for computer
+system architecture research, encompassing system-level architecture as
+well as processor microarchitecture.
+
+We will be releasing version 2.0 of M5 in conjunction with this
+tutorial. Features new in 2.0 include:
+
+ - Multiple ISA support (Alpha, MIPS, and SPARC)
+ - An all-new, execute-in-execute out-of-order SMT CPU timing model,
+ with no SimpleScalar license encumbrance
+ - All-new, message-oriented interface for memory system objects,
+ designed to simplify the development of non-bus interconnects
+ - More extensive Python integration and scripting support
+
+Because the primary focus of the M5 development team has been simulation
+of network-oriented server workloads, M5 incorporates several features
+not commonly found in other simulators.
+
+ - Full-system simulation using unmodified Linux 2.4/2.6, HP Tru64 5.1,
+ or [L4Ka::Pistachio](http://l4ka.org/projects/pistachio)) (Alpha
+ only at this time... coming in the future for MIPS and SPARC)
+ - Detailed timing of I/O device accesses and DMA operations
+ - Accurate, deterministic simulation of multiple networked systems
+ - Flexible, script-driven configuration to simplify specification of
+ complex multi-system configurations
+ - Included network workloads such as Apache, NAT, and NFS
+ - Support for storing results from multiple simulations in a unified
+ database (e.g. MySQL) for automated reporting and graph generation
+
+M5 also integrates a number of other desirable features, including
+pervasive object orientation, multiple interchangeable CPU models, an
+event-driven memory system model, and multiprocessor capability.
+Additionally, M5 is also capable of application-only simulation using
+syscall emulation.
+
+M5 is freely distributable under a BSD-style license, and does not
+depend on any commercial or restricted-license software.
+
+## Intended Audience
+
+Researchers in academia or industry looking for a free, open-source,
+full-system simulation environment for processor, system, or platform
+architecture studies. Please register via the
+[ISCA 2006](http://www.ece.neu.edu/conf/isca2006) web page.
+
+## Tentative Outline
+
+ - M5 structure
+ - Object structure
+ - Intro to SimObjects
+ - Object builder
+ - Configuration language
+ - Specialization using C++ templates
+ - Object serialization (checkpointing)
+ - Events
+ - CPU models
+ - Simple functional model
+ - Detailed out-of-order model
+ - Sampling and warm-up support
+ - Memory & I/O system overview
+ - Cache models
+ - Interconnect models (busses, point-to-point networks)
+ - Coherence support
+ - I/O modeling
+ - Programmed I/O (uncached accesses)
+ - DMA I/O
+ - Ethernet model
+ - NIC device models
+ - Linux driver
+ - Link layer model
+ - Full-system modeling
+ - Building disk images
+ - Console and PAL code
+ - Running benchmarks via system init scripts
+ - Target kernel introspection support
+ - Statistics
+ - Built-in statistics types
+ - Adding new statistics
+ - Using the database back end
+ - Setting up a results database
+ - Using scripts to generate reports and graphs from the
+ database
+ - Debugging techniques
+ - Built-in debugging support
+ - Tracing
+ - Runtime checking
+ - Gdb hooks
+ - Debugging target code (including kernels) using remote gdb
+ - ISA description language
+ - Adding your own instructions to the ISA
+ - Adding support for new ISAs
+
+## Speakers
+
+ - Steven K. Reinhardt is an associate professor in the EECS Department
+ at the University of Michigan, and a principal developer of M5. He
+ received a BS from Case Western Reserve University and an MS from
+ Stanford University, both in electrical engineering, and a PhD in
+ computer science from the University of Wisconsin-Madison. While at
+ Wisconsin, he was the principal developer of the Wisconsin Wind
+ Tunnel parallel architecture simulator.
+
+<!-- end list -->
+
+ - Nathan L. Binkert received his Ph.D. candidate from the EECS
+ Department at the University of Michigan, and a principal developer
+ of M5. He received a BSE in electrical engineering and MS in
+ computer science both from the University of Michigan. As an intern
+ at Compaq VSSAD, he was a principal developer of the ASIM simulator,
+ currently in use at Intel and is currently with Arbor Networks.
+
+<!-- end list -->
+
+ - Ronald G. Dreslinski is a Ph.D. student in the EECS Department at
+ the University of Michigan, and a developer of M5's memory system.
+ He received a BSE in electrical engineering, a BSE in computer
+ engineering, and a MSE in computer science and engineering all from
+ the University of Michigan.
+
+<!-- end list -->
+
+ - Kevin T. Lim is a Ph.D. student in the EECS Department at the
+ University of Michigan, and the developer of M5's detailed CPU
+ model. He received a BSE in computer engineering and an MSE in
+ computer science and engineering from the University of Michigan.
+
+<!-- end list -->
+
+ - Ali G. Saidi is a Ph.D. candidate in the EECS Department at the
+ University of Michigan, and wrote much of the platform code for
+ Linux full-system simulation. He received a BS in electrical
+ engineering from the University of Texas at Austin and an MSE in
+ computer science and engineering from the University of Michigan.
+
+__NOTOC__
diff --git a/_pages/events/isca-2011.md b/_pages/events/isca-2011.md
new file mode 100644
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--- /dev/null
+++ b/_pages/events/isca-2011.md
@@ -0,0 +1,42 @@
+---
+title: "ISCA 2011"
+date: 2018-05-13T18:51:37-04:00
+draft: false
+weight: 150
+---
+
+Call for Participation: ISCA 2011 Tutorial
+gem5: A Multiple-ISA Full System Simulator with Detailed Memory
+Modeling
+Sunday, June 5, 2011 8:30 am
+<http://www.gem5.org>
+The gem5 simulator is a merger of two of the computer architecture
+community’s most popular, open source simulators: M5 and GEMS. The best
+features of each simulator have been combined to provide an
+infrastructure capable of simulating multiple ISAs, CPU models, memory
+system components, cache coherence protocols and interconnection
+networks. The gem5 simulation team invites users, developers, and all
+other interested parties to participate in a tutorial that will
+highlight the key aspects of the gem5 simulator .
+
+The first half of this full-day tutorial will be an organized
+presentation focusing on gem5 usage and capabilities. The second half is
+intended to be more free form where we will answer audience questions on
+specific usage, including modification of the simulator to enable new
+features.
+
+Topics to be discussed include:
+
+ - Multiple ISA support (e.g. ARM and x86)
+ - Detailed and simple CPU models including “execute-in-execute”
+ in-order and out-of-order pipeline models.
+ - Cache coherence protocols using SLICC
+ - Interconnection network modeling (Crossbar, Mesh, etc.)
+ - Checkpointing and fast-forwarding
+
+We look forward to your participation in the gem5 tutorial and hope that
+by the end of the tutorial you’ll be able to utilize the gem5
+infrastructure in your future research.
+
+Thanks,
+The gem5 Simulation Team
diff --git a/_pages/events/isca-2015.md b/_pages/events/isca-2015.md
new file mode 100644
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--- /dev/null
+++ b/_pages/events/isca-2015.md
@@ -0,0 +1,78 @@
+---
+title: "ISCA 2015 - 2nd User Workshop"
+date: 2018-05-13T18:51:37-04:00
+draft: false
+weight: 90
+---
+
+<table>
+<tbody>
+<tr class="odd">
+<td><table>
+<tbody>
+<tr class="odd">
+<td><div style="font-size:202%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">
+<p>Second gem5 User Workshop</p>
+</div>
+<div style="font-size:140%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">
+<p>June 14th, 2015; Portland, OR</p>
+</div></td>
+</tr>
+</tbody>
+</table></td>
+</tr>
+</tbody>
+</table>
+
+Following up from a successful [2012
+workshop](User_workshop_2012 "wikilink"), it is time for the 2015
+edition of the gem5 user workshop. The primary objective of this
+workshop is to bring together groups across the community who are
+actively using gem5. Discussion topics will include the activity of the
+gem5 community, how we can best leverage each others contributions, and
+how we continue to make gem5 a successful, community-supported
+simulation framework. Those who will get the most out of the workshop
+are current users of gem5, although anyone is welcome to attend.
+
+The key part of the workshop is a set of presentations from the
+community about how individuals or groups are using the simulator, any
+features you have added that might be useful to others, and any major
+pain points, and what can be done to make gem5 better and more broadly
+adopted. The hope is that this will provide a forum for people with
+similar uses or needs to connect with each
+other.
+
+### Final Program
+
+| Topic | Time | Presenter | Affiliation |
+| ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------- | ----------------------- | ----------------------------------- |
+| [Introduction & Overview of Changes](Media:2015_ws_01_introduction.pdf "wikilink") | 9:00 AM | Steve Reinhardt | AMD |
+| [Classic Memory System Re-visited](Media:2015_ws_02_hansson_gem5_workshop_2015.pdf "wikilink") | 9:30 AM | Andreas Hansson | ARM |
+| User Perspectives |
+| [AMD's gem5 APU Simulator](Media:2015_ws_03_amd-apu-model.pdf "wikilink") | 10:00 AM | Brad Beckmann | AMD |
+| [NoMali: Understanding the Impact of Software Rendering Using a Stub GPU](Media:2015_ws_04_ISCA_2015_NoMali.pdf "wikilink") | 10:15 AM | Andreas Sandberg | ARM |
+| Cycle-Accurate STT-MRAM model in gem5 | 10:30 AM | Cong Ma | University of Minnesota |
+| [An Accurate and Detailed Prefetching Simulation Framework for gem5](Media:2015_ws_06_TorrentsM_gem5_prefetcher.pdf "wikilink") | 10:45 AM | Martí Torrents Lapuerta | Polytechnic University of Catalonia |
+| Break | 11:00 AM | | |
+| [Supporting Native PThreads in SE Mode](Media:2015_ws_07_pthread.pdf "wikilink") | 11:30 AM | Brandon Potter | AMD |
+| [Dynamically Linked Executables in SE Mode](Media:2015_ws_08_dynamic-linker.pdf "wikilink") | 11:45 AM | Brandon Potter | AMD |
+| [Coupling gem5 with SystemC TLM 2.0 Virtual Platforms](Media:2015_ws_09_2015-06-14_Gem5_ISCA.pptx "wikilink") | 12:00 PM | Matthias Jung | University of Kaiserslautern |
+| [SST/gem5 Integration](Media:2015_ws_10_sstGem5ISCA.pptx "wikilink") | 12:15 PM | Simon D. Hammond | Sandia |
+| Lunch | 12:30 PM | | |
+| [Full-System Simulation at Near Native Speed](Media:2015_ws_11_20150614_-_Trevor_E._Carlson_-_gem5_workshop.pptx "wikilink") | 1:30 PM | Trevor Carlson | Uppsala University |
+| [Enabling x86 KVM-Based CPU Model in Syscall Emulation Mode](Media:2015_ws_12_KVM-in-SE.pdf "wikilink") | 1:45 PM | Alexandru Dutu | AMD |
+| [Parallel gem5 Simulation of Many-Core Systems with Software-Progammable Memories](Media:2015_ws_13_gem5-manycore-spm.pdf "wikilink") | 2:00 PM | Bryan Donyanavard | UC Irvine |
+| [Infrastructure for AVF Modeling](Media:2015_ws_14_AVFInfrastructure.pdf "wikilink") | 2:15 PM | Mark Wilkening | AMD |
+| [gem5-Aladdin Integration for Heterogeneous SoC Modeling](Media:2015_ws_15_isca2015-gem5-aladdin.pptx "wikilink") | 2:30 PM | Y. Sophia Shao | Harvard University |
+| [Experiences Implementing Tinuso in gem5](Media:2015_ws_16_gem5-workshop_mwalter.pptx "wikilink") | 2:45 PM | Maxwell Walter | Technical University of Denmark |
+| [Experiences with gem5](Media:2015_ws_17_mmoreto-gem5userworkshop-2015.pptx "wikilink") | 3:00 PM | Miquel Moretó Planas | BSC/UPC |
+| [Little Shop of gem5 Horrors](https://docs.google.com/presentation/d/1QGA5UVaVJkkMITF2TXCY_KlwmfWef1KBzfDP6ocbj7I/pub?start=false&loop=false&delayms=3000) (see also [Jason's blog post](http://www.lowepower.com/jason/gem5-horrors-and-what-we-can-do-about-it.html)) | 3:15pm | Jason Power | University of Wisconsin |
+| Break | 3:30 PM | | |
+| Breakout Sessions |
+| Breakout Sessions | 4:00 PM | Breakout Groups | |
+| Wrap-Up | 5:00 PM | Everyone | |
+| |
+| [Conclusions](Media:2015_ws_19_gem5_workshop_conclusions.pptx "wikilink") | 5:30 PM | Ali Saidi | ARM |
+
+__NOTOC__
+
diff --git a/_pages/events/isca-2018.md b/_pages/events/isca-2018.md
new file mode 100644
index 0000000..b85624e
--- /dev/null
+++ b/_pages/events/isca-2018.md
@@ -0,0 +1,100 @@
+---
+title: "ISCA 2018"
+date: 2018-05-13T18:51:37-04:00
+draft: false
+weight: 10
+---
+
+<div style="font-size:150%;border:none;margin: 0;padding:.1em;text-align:center;color:#000">
+
+AMD gem5 APU Simulator: Modeling GPUs Using the Machine
+ISA
+
+</div>
+
+<div style="font-size:120%;border:none;margin:0;padding:.1em;text-align:center;color#000">
+
+Held in conjunction with [ISCA 2018](http://iscaconf.org/isca2018/).
+June 2nd, 2018.
+
+</div>
+
+# Important Dates
+
+The tutorial will be held on day one of the conference - June 2nd, 2018
+
+ISCA 2018 early registration and hotel reservation deadline - April
+16th, 2018
+
+# Abstract
+
+AMD Research has developed an APU (Accelerated Processing Unit) model
+that extends gem5 \[1\] with a GPU timing model that executes the GCN
+(Graphics Core Next) generation 3 machine ISA \[2, 3\]. In addition to
+supporting a modern machine ISA, the model supports running the
+open-source Radeon Open Compute platform (ROCm) stack without
+modification. This allows users to run a wide variety of applications
+written in several high-level languages, including C++, HIP, OpenMP, and
+OpenCL. This provides researchers the ability to evaluate many different
+types of workloads, from traditional compute applications to emerging
+modern GPU workloads, such as task parallel and machine learning
+applications. The resulting AMD gem5 APU simulator is a cycle-level,
+flexible research model that is capable of representing many different
+APU configurations, on-chip cache hierarchies, and system designs. Our
+APU extensions allow researchers to model both CPU and GPU memory
+requests and the interactions between them. In particular, the model
+uses SLICC and Ruby to implement a wide variety of coherence and
+synchronization solutions, which is a critical research area in
+heterogeneous computing. The model has been used in several top-tier
+computer architecture publications in the last several years \[MICRO
+2013, HPCA 2014, ASPLOS 2014, ISCA 2014, HPCA 2015, ASPLOS 2015, MICRO
+2016, HPCA 2017, ISCA 2017, HPCA 2018\].
+
+In this tutorial, we will describe the capabilities of the AMD gem5 APU
+simulator that will be publically released with a liberal BSD license
+before ISCA 2018. We will detail the simulated APU architecture, review
+the execution flow, and describe how the simulator has been used. The
+presentation will also discuss key design decisions and tradeoffs. For
+example, we use the system-call emulation mode to avoid running a full
+OS and kernel driver, therefore we will describe the simulator’s
+system-call emulation interface, and how the ROCm runtime and user space
+drivers interact with it. Also, our GPU model now directly executes
+native machine ISA instructions rather than the HSAIL intermediate
+language representation. Previously relying on executing the
+intermediate language simplified workload compilation, but was less
+accurate when modeling hardware behavior. In this tutorial, we will
+highlight many of the improvements enabled by executing the GCN3 ISA.
+
+\[1\]. Nathan Binkert et al. [The gem5
+Simulator](https://doi.org/10.1145/2024716.2024718). In SIGARCH Computer
+Architecture News, vol. 39, no. 2, pp. 1-7, Aug. 2011.
+
+\[2\]. AMD. [AMD GCN3 ISA Architecture
+Manual](https://gpuopen.com/compute-product/amd-gcn3-isa-architecture-manual/)
+
+\[3\]. Anthony Gutierrez et al. [Lost in Abstraction: Pitfalls of
+Analyzing GPUs at the Intermediate Language
+Level](https://doi.org/10.1109/HPCA.2018.00058). In HPCA 2018.
+
+# Slides
+
+# Schedule
+
+| Topic | Presenter | Time |
+| ------------------------------- | -------------- | -------------- |
+| Background | Tony | 8:00-8:15 am |
+| ROCm Stack, GCN3 ISA, and uArch | Tony | 8:15-9:15 am |
+| HSA Queuing | Sooraj | 9:15-10:00 am |
+| Break | 10:00-10:30 am |
+| Ruby and GPU Protocol Tester | Tuan | 10:30-11:15 am |
+| Demo/Workloads and Q+A | TBD | 11:15-12:00 pm |
+
+# Presenters
+
+Tony Gutierrez (AMD Research)
+
+Sooraj Puthoor (AMD Research)
+
+Brad Beckmann (AMD Research)
+
+Tuan Ta (Cornell)
diff --git a/_pages/events/micro-2012.md b/_pages/events/micro-2012.md
new file mode 100644
index 0000000..26bae6d
--- /dev/null
+++ b/_pages/events/micro-2012.md
@@ -0,0 +1,76 @@
+---
+title: "MISCO 2012 - 1st user workshop"
+date: 2018-05-13T18:51:37-04:00
+draft: false
+weight: 100
+---
+
+<table>
+<tbody>
+<tr class="odd">
+<td><table>
+<tbody>
+<tr class="odd">
+<td><div style="font-size:202%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">
+<p>First gem5 User Workshop</p>
+</div>
+<div style="font-size:140%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">
+<p>December 2012; Vancouver, BC</p>
+</div></td>
+</tr>
+</tbody>
+</table></td>
+</tr>
+</tbody>
+</table>
+
+The primary objective of this workshop is to bring together groups
+across the community who are actively using gem5, discuss what is going
+on in the gem5 community, how we can best leverage each others
+contributions, and how we continue to make gem5 a successful
+community-supported simulation framework. Those who will get the most
+out of the conference are current users of gem5, although anyone is
+welcome to
+attend.
+
+### Program
+
+| Topic | Time | Presenter | Affiliation |
+| -------------------------------------------------------------------------------------------------------------------------------------------------------- | -------- | ------------------------------------- | ----------------------------------- |
+| [Introduction](Media:gem5_user_workshop_intro.pdf "wikilink") | 8:30 AM | Ali Saidi | ARM |
+| Recent Contributions |
+| [Memory System Enhancements](Media:2012_12_01_gem5_workshop_Memory.pdf "wikilink") | 8:45 AM | Andreas Hannson | ARM |
+| [Visualizing stats via Streamline](Media:2012_12_01_gem5_workshop_Streamline.pdf "wikilink") | 9:05 AM | Dam Sunwoo | ARM |
+| User Perspectives |
+| [HAsim: FPGA-Based Micro-Architecture Simulator](Media:201212_HAsim_GEM5.pdf "wikilink") | 9:20 AM | Michael Adler | Intel |
+| [VLIW DSPs/MIPS FS mode](Media:Tsinghua's_Presentation_for_gem5_Workshop_2012.pdf "wikilink") | 9:35 AM | Deyuan Guo and Hu He | Tsinghua Univ. |
+| [Eclipse Integration](Media:Tsinghua's_Presentation_for_gem5_Workshop_2012.pdf "wikilink") | 9:50 AM | Deyuan Guo and Hu He | Tsinghua Univ. |
+| Break | 10:05 AM | | |
+| [Full-System Workloads and Asymmetric Multi-Core Simulation](Media:Gutierrez_gem5_workshop_2012.pdf "wikilink") | 10:30 AM | Anthony Gutierrez | Univ. of Michigan |
+| [ARM SoC exploration](Media:Gem5_workshop_arm_soc_exploration_ext.pdf "wikilink") | 10:45 AM | Alexandre Romana and Abhilash Nair | Texas Instruments |
+| [SystemC integration](Media:Gem5_workshop_systemC_integration_ext.pdf "wikilink") | 11:00 AM | Alexandre Romana | Texas Instruments |
+| [Composite Cores](Media:Performance_Prediction_Models_gem5_workshop.pdf "wikilink") | 11:15 AM | Shruti Padmanabha and Andrew Lukefahr | Univ. of Michigan |
+| [Customized InOrder CPU Modeling](Media:2012_workshop_gem5_inorder_modeling.pdf "wikilink") | 11:30 AM | Korey Sewell | Univ. of Michigan (now at Qualcomm) |
+| [Cross-Cutting Infrastructure for Evaluating Managed Languages and Future Architectures](Media:2012_gem5_modern_languages_infrastructure.pdf "wikilink") | 11:45 AM | Paul Gratz | Texas A\&M Univ. |
+| Lunch | 12:00 PM | | |
+| [Simplifying SLICC via Atomic Messages](Media:Atomic_interfaces_micro_2012_final.pdf "wikilink") | 1:00 PM | Brad Beckmann | AMD |
+| [Accelerating Simulation with Virtual Machines](Media:2012_12_gem5_workshop_kvm.pdf "wikilink") | 1:15 PM | Ali Saidi | ARM |
+| [gem5-gpu: A Simulator for Heterogeneous Processors](Media:2012_12_gem5_gpu.pdf "wikilink") | 1:30 PM | Jason Power and Marc Orr | Univ. of Wisconsin-Madison |
+| Breakout Sessions |
+| [Breakout Sessions](Media:2012_gem5_micro_breakout.pdf "wikilink") | 1:45 PM | Breakout Groups | |
+| Break | 3:00 PM | | |
+| Wrap-Up/Next Steps | 3:30 PM | Everyone | |
+| |
+| Conclusions | 4:00 PM | Steve Reinhardt | AMD |
+
+### Location
+
+The workshop is co-located with
+[MICRO-45](http://www.microsymposia.org/micro45/) in Vancouver, BC.
+
+### Date
+
+Sunday December 2nd from 8:30 - 16:30.
+
+__NOTOC__
+
