These microops typically take two sources and produce one result. Most have a version that operates on only registers and a version which operates on registers and an immediate value. Some optionally set flags according to their operation. Some of them can be predicated.
Addition.
Dest # Dest <- Src1 + Src2
Adds the contents of the Src1 and Src2 registers and puts the result in the Dest register.
Dest # Dest <- Src1 + Imm
Adds the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
Flag | Meaning |
---|---|
CF and ECF | The carry out of the most significant bit. |
ZF and EZF | Whether the result was zero. |
PF | The parity of the result. |
AF | The carry from the fourth to fifth bit positions. |
SF | The sign of the result. |
OF | Whether there was an overflow. |
Add with carry.
Dest # Dest <- Src1 + Src2 + CF
Adds the contents of the Src1 and Src2 registers and the carry flag and puts the result in the Dest register.
Dest # Dest <- Src1 + Imm + CF
Adds the contents of the Src1 register, the immediate Imm, and the carry flag and puts the result in the Dest register.
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
Flag | Meaning |
---|---|
CF and ECF | The carry out of the most significant bit. |
ZF and EZF | Whether the result was zero. |
PF | The parity of the result. |
AF | The carry from the fourth to fifth bit positions. |
SF | The sign of the result. |
OF | Whether there was an overflow. |
Subtraction.
Dest # Dest <- Src1 - Src2
Subtracts the contents of the Src2 register from the Src1 register and puts the result in the Dest register.
Dest # Dest <- Src1 - Imm
Subtracts the contents of the immediate Imm from the Src1 register and puts the result in the Dest register.
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
Flag | Meaning |
---|---|
CF and ECF | The borrow into of the most significant bit. |
ZF and EZF | Whether the result was zero. |
PF | The parity of the result. |
AF | The borrow from the fourth to fifth bit positions. |
SF | The sign of the result. |
OF | Whether there was an overflow. |
Subtract with borrow.
Dest # Dest <- Src1 - Src2 - CF
Subtracts the contents of the Src2 register and the carry flag from the Src1 register and puts the result in the Dest register.
Dest # Dest <- Src1 - Imm - CF
Subtracts the immediate Imm and the carry flag from the Src1 register and puts the result in the Dest register.
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
Flag | Meaning |
---|---|
CF and ECF | The borrow into of the most significant bit. |
ZF and EZF | Whether the result was zero. |
PF | The parity of the result. |
AF | The borrow from the fourth to fifth bit positions. |
SF | The sign of the result. |
OF | Whether there was an overflow. |
Signed multiply.
ProdHi:ProdLo # Src1 * Src2
Multiplies the unsigned contents of the Src1 and Src2 registers and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.
ProdHi:ProdLo # Src1 * Imm
Multiplies the unsigned contents of the Src1 register and the immediate Imm and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.
This microop does not set any flags.
Unsigned multiply.
ProdHi:ProdLo # Src1 * Src2
Multiplies the unsigned contents of the Src1 and Src2 registers and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.
ProdHi:ProdLo # Src1 * Imm
Multiplies the unsigned contents of the Src1 register and the immediate Imm and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.
This microop does not set any flags.
Unload multiply result low.
Dest # Dest <- ProdLo
Moves the value of the internal ProdLo register into the Dest register.
This microop does not set any flags.
Unload multiply result high.
Dest # Dest <- ProdHi
Moves the value of the internal ProdHi register into the Dest register.
This microop optionally sets the CF, ECF, and OF flags.
Flag | Meaning |
---|---|
CF and ECF | Whether ProdHi is non-zero. |
OF | Whether ProdHi is zero. |
First stage of division.
Quotient * Src2 + Remainder # Src1 Divisor # Src2
Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the contents of SrcReg2 is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.
Quotient * Imm + Remainder # Src1 Divisor # Imm
Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the immediate Imm is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.
This microop does not set any flags.
Second and later stages of division.
Quotient * Divisor + Remainder # original Remainder with bits shifted in from Src1
Dest # Dest <- Src2 - number of bits shifted in above
Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The contents of the register Src2 denote the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.
If there are no remaining bits in Src1, this instruction does nothing except optionally compute flags.
Quotient * Divisor + Remainder # original Remainder with bits shifted in from Src1
Dest # Dest <- Imm - number of bits shifted in above
Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The immediate Imm denotes the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.
If there are no remaining bits in Src1, this instruction does nothing except optionally compute flags.
This microop optionally sets the EZF flag.
Flag | Meaning |
---|---|
EZF | Whether there are any remaining bits in Src1 after this step. |
Unload division quotient.
Dest # Dest <- Quotient
Moves the value of the internal Quotient register into the Dest register.
This microop does not set any flags.
Unload division remainder.
Dest # Dest <- Remainder
Moves the value of the internal Remainder register into the Dest register.
This microop does not set any flags.
Logical or.
Dest # Dest <- Src1 | Src2
Computes the bitwise or of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
Dest # Dest <- Src1 | Imm
Computes the bitwise or of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.
Flag | Meaning |
---|---|
CF and ECF | Cleared. |
ZF and EZF | Whether the result was zero. |
PF | The parity of the result. |
AF | Undefined. |
SF | The sign of the result. |
OF | Cleared. |
Logical And
Dest # Dest <- Src1 & Src2
Computes the bitwise and of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
Dest # Dest <- Src1 & Imm
Computes the bitwise and of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.
Flag | Meaning |
---|---|
CF and ECF | Cleared. |
ZF and EZF | Whether the result was zero. |
PF | The parity of the result. |
AF | Undefined. |
SF | The sign of the result. |
OF | Cleared. |
Logical exclusive or.
Dest # Dest <- Src1 | Src2
Computes the bitwise xor of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
Dest # Dest <- Src1 | Imm
Computes the bitwise xor of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.
Flag | Meaning |
---|---|
CF and ECF | Cleared. |
ZF and EZF | Whether the result was zero. |
PF | The parity of the result. |
AF | Undefined. |
SF | The sign of the result. |
OF | Cleared. |
Logical left shift.
Dest # Dest <- Src1 << Src2
Shifts the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
Dest # Dest <- Src1 << Imm
Shifts the contents of the Src1 register to the left by the value in the immediate Imm and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.
Flag | Meaning |
---|---|
CF and ECF | The last bit shifted out of the result. |
OF | The exclusive OR of what this instruction would set the CF flag to, if requested, and the most significant bit of the result. |
Logical right shift.
Dest # Dest <- Src1 >>(logical) Src2
Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
Dest # Dest <- Src1 >>(logical) Imm
Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.
Flag | Meaning |
---|---|
CF and ECF | The last bit shifted out of the result. |
SF | The most significant bit of the original value to shift. |
Arithmetic right shift.
Dest # Dest <- Src1 >>(arithmetic) Src2
Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
Dest # Dest <- Src1 >>(arithmetic) Imm
Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.
Flag | Meaning |
---|---|
CF and ECF | The last bit shifted out of the result. |
OF | Cleared. |
Rotate right.
Rotates the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Rotates the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.
Flag | Meaning |
---|---|
CF and ECF | The most significant bit of the result. |
OF | The exclusive OR of the most two significant bits of the original value. |
Rotate right through carry.
Rotates the contents of the Src1 register through the carry flag and to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Rotates the contents of the Src1 register through the carry flag and to the right by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.
Flag | Meaning |
---|---|
CF and ECF | The last bit shifted out of the result. |
OF | The exclusive OR of the CF flag before the rotate and the most significant bit of the original value. |
Rotate left.
Rotates the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Rotates the contents of the Src1 register to the left by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.
Flag | Meaning |
---|---|
CF and ECF | The least significant bit of the result. |
OF | The exclusive OR of the most and least significant bits of the result. |
Rotate left through carry.
Rotates the contents of the Src1 register through the carry flag and to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Rotates the contents of the Src1 register through the carry flag and to the left by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.
Flag | Meaning |
---|---|
CF and ECF | The last bit rotated out of the result. |
OF | The exclusive OR of CF before the rotate and the most significant bit of the result. |
Move.
Dest # Src1 <- Src2
Merge the contents of the Src2 register into the contents of Src1 and put the result into the Dest register.
Dest # Src1 <- Imm
Merge the contents of the immediate Imm into the contents of Src1 and put the results into the Dest register.
This microop does not set any flags. It is optionally predicated.
Sign extend.
Dest # Dest <- sign_extend(Src1, Imm)
Sign extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.
This microop does not set any flags.
Zero extend.
Dest # Dest <- zero_extend(Src1, Imm)
Zero extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.
This microop does not set any flags.
Read user flag.
Reads the user level flag stored in the bit position specified by the immediate Imm and stores it in the register Dest.
The mapping between values of Imm and user level flags is show in the following table.
Imm | Flag |
---|---|
0 | CF (carry flag) |
2 | PF (parity flag) |
3 | ECF (emulation carry flag) |
4 | AF (auxiliary flag) |
5 | EZF (emulation zero flag) |
6 | ZF (zero flag) |
7 | CF (sign flag) |
10 | CF (direction flag) |
11 | CF (overflow flag) |
The EZF flag is always set. In the future this may become optional.
Read all user flags.
Dest # user flags
Store the user level flags into the Dest register.
This microop does not set any flags.
Write all user flags.
user flags # Src1 ^ Src2
Set the user level flags to the exclusive or of the Src1 and Src2 registers.
user flags # Src1 ^ Imm
Set the user level flags to the exclusive or of the Src1 register and the immediate Imm.
See above.
Read the instruction pointer.
Dest # rIP
Set the Dest register to the current value of rIP.
This microop does not set any flags.
Write the instruction pointer.
rIP # Src1 + Src2
Set the rIP to the sum of the Src1 and Src2 registers. This causes a macroop branch at the end of the current macroop.
micropc # Src1 + Imm
Set the rIP to the sum of the Src1 register and immediate Imm. This causes a macroop branch at the end of the current macroop.
This microop does not set any flags. It is optionally predicated.
Check selector.
Not yet implemented.
Load.
Loads the integer register Data from memory.
Load floating point.
Loads the floating point register Data from memory.
Load multimedia.
Load the multimedia register Data from memory. This is not implemented and may never be.
Load with store check.
Load the integer register Data from memory while also checking if a store to that location would succeed. This is not implemented currently.
Load with store check, locked.
Load the integer register Data from memory while also checking if a store to that location would succeed, and also provide the semantics of the “LOCK” instruction prefix. This is not implemented currently.
Store.
Stores the integer register Data to memory.
Store floating point.
Stores the floating point register Data to memory.
Store multimedia.
Store the multimedia register Data to memory. This is not implemented and may never be.
Store with base update.
Store the integer register Data to memory and update the base register.
Load effective address.
Calculates the address for this combination of parameters and stores it in Data.
Check data address.
Check whether the data address is valid. This is not implemented currently.
CDA with cache line flush.
Check whether the data address is valid, and flush cache lines This is not implemented currently.
Check instruction address.
Check whether the instruction address is valid. This is not implemented currently.
TLB invalidate address
Invalidate the tlb entry which corresponds to this address. This is not implemented currently.
Stores the 64 bit immediate Imm into the integer register Dest.
Dest # Src
Move the contents of the floating point register Src into the floating point register Dest.
This instruction is predicated.
Dest # Src1 ^ Src2
Compute the bitwise exclusive or of the floating point registers Src1 and Src2 and put the result in the floating point register Dest.
Dest # sqrt(Src)
Compute the square root of the floating point register Src and put the result in floating point register Dest.
Dest # Src1 + Src2
Compute the sum of the floating point registers Src1 and Src2 and put the result in the floating point register Dest.
Dest # Src1 - Src2
Compute the difference of the floating point registers Src1 and Src2 and put the result in the floating point register Dest.
Dest # Src1 * Src2
Compute the product of the floating point registers Src1 and Src2 and put the result in the floating point register Dest.
Dest # Src1 / Src2
Divide Src1 by Src2 and put the result in the floating point register Dest.
Compare floating point registers Src1 and Src2.
Convert integer register Src into a double floating point value and store the result in the lower part of Dest.
Convert integer register Src into a double floating point value and store the result in the upper part of Dest.
Convert floating point register Src into an integer value and store the result in the integer register Dest.
Generate a fault.
Uses the C++ code fault_code to allocate a Fault object to return.
Set the default handler for a fault. This is not implemented currently.
Set the alternate handler for a fault This is not implemented currently.
These microops are used for control flow withing microcode
Microcode branch. This is never considered the last microop of a sequence. If it appears at the end of a macroop, it is assumed that it branches to microcode in the ROM.
micropc # target
Set the micropc to the 16 bit immediate target.
This microop does not set any flags. It is optionally predicated.
Return from emulation. This instruction is always considered the last microop in a sequence. When executing from the ROM, it is the only way to return to normal instruction decoding.
Return from emulation.
This microop does not set any flags. It is optionally predicated.