| commit | 9f95d688af3295caacfd1960538bfa6dea9a84bd | [log] [tgz] |
|---|---|---|
| author | Andrea Mondelli <andrea.mondelli@huawei.com> | Tue Nov 02 18:33:54 2021 +0800 |
| committer | Andrea Mondelli <mondelli.huawei@gmail.com> | Thu Nov 04 09:09:35 2021 +0000 |
| tree | 1a242e58247784036a48ef6d46696d7aec6ae75e | |
| parent | 137f6bab14cedb227bf1f069a0d239cdd178f854 [diff] |
website: added RISCV to the valid ISAs list Change-Id: Ief7746d2bf65cd119dd223b96027d825cc2cb481 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-website/+/52343 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
diff --git a/_pages/documentation/general_docs/building/index.md b/_pages/documentation/general_docs/building/index.md index d4cebda..ab5a8ba 100644 --- a/_pages/documentation/general_docs/building/index.md +++ b/_pages/documentation/general_docs/building/index.md
@@ -153,6 +153,7 @@ * NULL * MIPS * POWER +* RISCV * SPARC * X86