diff --git a/_data/documentation.yml b/_data/documentation.yml
index 33cfcc7..215a320 100755
--- a/_data/documentation.yml
+++ b/_data/documentation.yml
@@ -56,6 +56,8 @@
           url: http://doxygen.gem5.org/release/v21-2-0-0/index.html
         - page: v21.2.1.0
           url: http://doxygen.gem5.org/release/v21-2-1-0/index.html
+        - page: v21.2.1.1
+          url: http://doxygen.gem5.org/release/v21-2-1-1/index.html
 
     - title: gem5 standard library
       id: gem5-standard-library
diff --git a/_pages/documentation/general_docs/building/index.md b/_pages/documentation/general_docs/building/index.md
index a2af8e8..713f788 100644
--- a/_pages/documentation/general_docs/building/index.md
+++ b/_pages/documentation/general_docs/building/index.md
@@ -51,18 +51,7 @@
 libraries. It is a necessary dependency if you wish to use the SystemC
 implementation.
 
-### Setup on Ubuntu 18.04
-
-If compiling gem5 on Ubuntu 18.04, or related Linux distributions, you may
-install all these dependencies using APT:
-
-```
-sudo apt install build-essential git m4 scons zlib1g zlib1g-dev \
-    libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \
-    python3-dev python3-six python libboost-all-dev pkg-config
-```
-
-### Setup on Ubuntu 20.04
+### Setup on Ubuntu 20.04 (gem5 >= v21.0)
 
 If compiling gem5 on Ubuntu 20.04, or related Linux distributions, you may
 install all these dependencies using API:
@@ -70,7 +59,18 @@
 ```
 sudo apt install build-essential git m4 scons zlib1g zlib1g-dev \
     libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \
-    python3-dev python3-six python-is-python3 libboost-all-dev pkg-config
+    python3-dev python-is-python3 libboost-all-dev pkg-config
+```
+
+### Setup on Ubuntu 18.04 (gem5 >= v21.0)
+
+If compiling gem5 on Ubuntu 18.04, or related Linux distributions, you may
+install all these dependencies using APT:
+
+```
+sudo apt install build-essential git m4 scons zlib1g zlib1g-dev \
+    libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \
+    python3-dev python libboost-all-dev pkg-config
 ```
 
 ### Docker
@@ -84,7 +84,7 @@
 https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile)).
 
 Ubuntu 20.04 with minimum dependencies:
-[gcr.io/gem5-test/ubuntu-20.04_all-dependencies:v21-2](
+[gcr.io/gem5-test/ubuntu-20.04_min-dependencies:v21-2](
 https://gcr.io/gem5-test/ubuntu-20.04_min-dependencies:v21-2) ([source Dockerfile](
 https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/util/dockerfiles/ubuntu-20.04_min-dependencies/Dockerfile)).
 
diff --git a/_pages/documentation/general_docs/cpu_models/minor_cpu.md b/_pages/documentation/general_docs/cpu_models/minor_cpu.md
index 39a7cdd..643180f 100644
--- a/_pages/documentation/general_docs/cpu_models/minor_cpu.md
+++ b/_pages/documentation/general_docs/cpu_models/minor_cpu.md
@@ -258,23 +258,23 @@
 http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1_1_1IcachePort.html#aec62b3d89dfe61e8528cdcdf3729eeab))
 and cause the pipeline to be woken up to service advancing request queues.
 
-[Ticked](http://doxygen.gem5.org/release/current/classTicked.html) (sim/ticked.hh)
+[Ticked](http://doxygen.gem5.org/release/current/classgem5_1_1Ticked.html) (sim/ticked.hh)
 is a base class bringing together an evaluate member function and a provided
-[SimObject](http://doxygen.gem5.org/release/current/classSimObject.html). It
+[SimObject](http://doxygen.gem5.org/release/current/classgem5_1_1SimObject.html). It
 provides a [Ticked::start](
 http://doxygen.gem5.org/release/current/classTicked.html#a798d1e248c27161de6eb2bc6fef5e425)/stop
 interface to start and pause clock events from being periodically issued.
-[Pipeline](http://doxygen.gem5.org/release/current/classMinor_1_1Pipeline.html) is
+[Pipeline](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Pipeline.html) is
 a derived class of Ticked.
 
 During evaluate calls, stages can signal that they still have work to do in the
 next cycle by calling either [MinorCPU::activityRecorder](
-http://doxygen.gem5.org/release/current/classMinorCPU.html#ae3b03c96ee234e2c5c6c68f4567245a7)->activity()
+http://doxygen.gem5.org/release/current/classgem5_1_1MinorCPU.html#ae3b03c96ee234e2c5c6c68f4567245a7)->activity()
 (for non-callable related activity) or MinorCPU::wakeupOnEvent(<stageId>) (for
 stage callback-related 'wakeup' activity).
 
 [Pipeline::evaluate](
-http://doxygen.gem5.org/release/current/classMinor_1_1Pipeline.html#af07fdce00c8937e9de5b6450a1cd62bf)
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Pipeline.html#af07fdce00c8937e9de5b6450a1cd62bf)
 contains calls to evaluate for each unit and a test for pipeline idling which
 can turns off the clock tick if no unit has signalled that it may become active
 next cycle.
@@ -289,9 +289,9 @@
 configurable delay which can be set as low as 0 cycles.
 
 The [MinorCPU::activateContext](
-http://doxygen.gem5.org/release/current/classMinorCPU.html#a854596342bfb9dd889437e494c4ddb27)
+http://doxygen.gem5.org/release/current/classgem5_1_1MinorCPU.html#a854596342bfb9dd889437e494c4ddb27)
 and [MinorCPU::suspendContext](
-http://doxygen.gem5.org/release/current/classMinorCPU.html#ae6aa9b1bb798d8938f0b35e11d9e68b8)
+http://doxygen.gem5.org/release/current/classgem5_1_1MinorCPU.html#ae6aa9b1bb798d8938f0b35e11d9e68b8)
 interface can be called to start and pause threads (threads in the MT sense)
 and to start and pause the pipeline. Executing instructions can call this
 interface (indirectly through the ThreadContext) to idle the CPU/their threads.
@@ -734,18 +734,18 @@
 |Debug flag      | Unit which will generate debugging output |
 |:---------------|:------------------------------------------|
 |Activity        | [Debug](http://doxygen.gem5.org/release/current/namespaceDebug.html) ActivityMonitor actions |
-|Branch          | [Fetch2](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) and [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) branch prediction decisions |
-|[MinorCPU](http://doxygen.gem5.org/release/current/classMinorCPU.html)      | CPU global actions such as wakeup/thread suspension |
-|[Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html) | [Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html) |
-|MinorExec       | [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) behaviour |
-|Fetch           |[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) and [Fetch2](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) |
-|MinorInterrupt  | [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) interrupt handling  |
-|MinorMem        | [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) memory interactions |
-|MinorScoreboard | [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) scoreboard activity |
+|Branch          | [Fetch2](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Fetch2.html) and [Execute](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) branch prediction decisions |
+|[MinorCPU](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1MinorCPU.html)      | CPU global actions such as wakeup/thread suspension |
+|[Decode](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Decode.html) | [Decode](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Decode.html) |
+|MinorExec       | [Execute](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) behaviour |
+|Fetch           |[Fetch1](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Fetch1.html) and [Fetch2](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Fetch2.html) |
+|MinorInterrupt  | [Execute](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) interrupt handling  |
+|MinorMem        | [Execute](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) memory interactions |
+|MinorScoreboard | [Execute](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) scoreboard activity |
 |MinorTrace      | Generate MinorTrace cyclic state trace output (see below) |
 |MinorTiming     | MinorTiming instruction timing modification operations    |
 
-The group flag [Minor](http://doxygen.gem5.org/release/current/namespaceMinor.html)
+The group flag [Minor](http://doxygen.gem5.org/release/current/namespaceminor.html)
 enables all the flags beginning with [Minor](
 http://doxygen.gem5.org/release/current/namespaceMinor.html).
 
@@ -772,7 +772,7 @@
 
 #### MinorInst - summaries of instructions issued by Decode
 
-[Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html)
+[Decode](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Decode.html)
 
 For example:
 
@@ -785,7 +785,7 @@
 
 #### MinorLine - summaries of line fetches issued by Fetch1
 
-[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html)
+[Fetch1](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Fetch1.html)
 
 For example:
 
@@ -899,8 +899,8 @@
 their outputs (to the right).
 
 The backwards FIFO between [Fetch2](
-http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) and [Fetch1](
-http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) shows branch
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Fetch2.html) and [Fetch1](
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Fetch1.html) shows branch
 prediction data.
 
 In general, all displayed data is correct at the end of a cycle's activity at
@@ -915,28 +915,28 @@
 stage from generating output.
 
 Fetch queues and [LSQ](
-http://doxygen.gem5.org/release/current/classMinor_1_1LSQ.html) show the
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1LSQ.html) show the
 lines/instructions in the queues of each interface and show the number of
 lines/instructions in TLB and memory in the two striped colours of the top of
 their frames.
 
 Inside [Execute](
-http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html), the horizontal
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html), the horizontal
 bars represent the individual FU pipelines. The vertical bar to the left is the
 input buffer and the bar to the right, the instructions committed this cycle.
 The background of [Execute](
-http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) shows
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) shows
 instructions which are being committed this cycle in their original FU pipeline
 positions.
 
 The strip at the top of the [Execute](
-http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) block shows the
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) block shows the
 current streamSeqNum that [Execute](
-http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) is committing.
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) is committing.
 A similar stripe at the top of [Fetch1](
-http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) shows that
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Fetch1.html) shows that
 stage's expected streamSeqNum and the stripe at the top of [Fetch2](
-http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) shows its
+http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Fetch2.html) shows its
 issuing predictionSeqNum.
 
 The scoreboard shows the number of instructions in flight which will commit a
@@ -944,7 +944,7 @@
 each integer and floating point register.
 
 The Execute::inFlightInsts queue shows all the instructions in flight in
-[Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) with
+[Execute](http://doxygen.gem5.org/release/current/classgem5_1_1minor_1_1Execute.html) with
 the oldest instruction (the next instruction to be committed) to the right.
 
 `Stage activity` shows the signalled activity (as E/1) for each stage (with CPU
diff --git a/_pages/documentation/general_docs/debugging_and_testing/debugging/debugger_based_debugging.md b/_pages/documentation/general_docs/debugging_and_testing/debugging/debugger_based_debugging.md
index 5b6bd39..84cb89f 100644
--- a/_pages/documentation/general_docs/debugging_and_testing/debugging/debugger_based_debugging.md
+++ b/_pages/documentation/general_docs/debugging_and_testing/debugging/debugger_based_debugging.md
@@ -108,7 +108,12 @@
 
 For Valgrind to function, the target gem5 binary must have been compiled to
 include debugging information. Therefore, the `gem5.debug` binaries must be
-used.
+used. Due to difficulties with Valgrind working with tcmalloc, `gem5.debug`
+must be compiled without using the `--without-tcmalloc` flag:
+
+```
+scons --without-tcmalloc build/{ISA}/gem5.debug
+```
 
 To run a check using Valgrind, execute the following:
 
diff --git a/_pages/documentation/general_docs/fullsystem/building_android_m.md b/_pages/documentation/general_docs/fullsystem/building_android_m.md
index 3b2b620..424ce4b 100644
--- a/_pages/documentation/general_docs/fullsystem/building_android_m.md
+++ b/_pages/documentation/general_docs/fullsystem/building_android_m.md
@@ -222,7 +222,7 @@
 sudo rm /mnt/androidRoot/system/bin/bootanimation
 ```
 
-Download and unpack the Mali drivers, for gem5 Android 4.4, from [here](http://malideveloper.arm.com/resources/drivers/arm-mali-midgard-gpu-user-space-drivers/). Then, make the directories for the drivers and copy them:
+Download and unpack the Mali drivers, for gem5 Android 4.4, from [here](https://developer.arm.com/downloads/-/mali-drivers/midgard-kernel). Then, make the directories for the drivers and copy them:
 
 ```
 sudo mkdir -p /mnt/androidRoot/system/vendor/lib/egl
diff --git a/_pages/documentation/general_docs/gpu_models/gcn3.md b/_pages/documentation/general_docs/gpu_models/gcn3.md
index 6a548e9..6528dfd 100644
--- a/_pages/documentation/general_docs/gpu_models/gcn3.md
+++ b/_pages/documentation/general_docs/gpu_models/gcn3.md
@@ -10,9 +10,9 @@
 
 Table of Contents
 
-1. [Using the model](##Using-the-model)
-2. [ROCm](##ROCm)
-3. [Documentation and Tutorials](##Documentation-and-Tutorials)
+1. [Using the model](#Using-the-model)
+2. [ROCm](#ROCm)
+3. [Documentation and Tutorials](#Documentation-and-Tutorials)
 
 The GCN3 GPU is a model that simulates a GPU at the ISA level, as opposed to the intermediate language level. This page will give you a general overview of how to use this model, the software stack the model uses, and provide resources that detail the model and how it is implemented.
 
@@ -20,7 +20,7 @@
 
 Currently, the GCN3 GPU model in gem5 is supported on the stable and develop branch.
 
-The [gem5 repository](https://gem5.goooglesource.com/public/gem5) comes with a dockerfile located in `util/dockerfiles/gcn-gpu/`. This dockerfile contains the drivers and libraries needed to run the GPU model. A pre-built version of the docker image is hosted at `gcr.io/gem5-test/gcn-gpu`.
+The [gem5 repository](https://gem5.googlesource.com/public/gem5) comes with a dockerfile located in `util/dockerfiles/gcn-gpu/`. This dockerfile contains the drivers and libraries needed to run the GPU model. A pre-built version of the docker image is hosted at `gcr.io/gem5-test/gcn-gpu`.
 
 The [gem5-resources repository](https://gem5.googlesource.com/public/gem5-resources/) also comes with a number of sample applications that can be used to verify that the model runs correctly.  We recommend users start with [square](https://resources.gem5.org/resources/square), as it is a simple, heavily tested application that should run relatively quickly.
 
diff --git a/_pages/documentation/general_docs/memory_system/gem5_memory_system.md b/_pages/documentation/general_docs/memory_system/gem5_memory_system.md
index 68c7169..d9c3927 100644
--- a/_pages/documentation/general_docs/memory_system/gem5_memory_system.md
+++ b/_pages/documentation/general_docs/memory_system/gem5_memory_system.md
@@ -33,7 +33,7 @@
 
 ## CPU
 
-Data [Cache](http://doxygen.gem5.org/release/current/classcache.html) object
+Data [Cache](http://doxygen.gem5.org/release/current/classgem5_1_1cache.html) object
 implements a standard cache structure:
 
 ![DCache Simulation Objet](/assets/img/gem5_MS_Fig2.PNG)
@@ -65,13 +65,13 @@
 
 ## Data Cache Object
 
-Data [Cache](http://doxygen.gem5.org/release/current/classCache.html) object
+Data [Cache](http://doxygen.gem5.org/release/current/classgem5_1_1Cache.html) object
 implements a standard cache structure:
 
 **Cached memory reads** that match particular cache tag (with Valid & Read
 flags) will be completed (by sending ReadResp to CPU) after a configurable
 time. Otherwise, the request is forwarded to Miss Status and Handling Register
-([MSHR](http://doxygen.gem5.org/release/current/classMSHR.html)) block.
+([MSHR](http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html)) block.
 
 **Cached memory writes** that match particular cache tag (with Valid, Read &
 Write flags) will be completed (by sending WriteResp CPU) after the same
@@ -79,36 +79,36 @@
 Handling Register(MSHR) block.
 
 **Uncached memory reads** are forwarded to [MSHR](
-http://doxygen.gem5.org/release/current/classMSHR.html) block.
+http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html) block.
 
 **Uncached memory writes** are forwarded to WriteBuffer block.
 
 **Evicted (& dirty) cache lines** are forwarded to WriteBuffer block.
 
 CPU’s access to Data [Cache](
-http://doxygen.gem5.org/release/current/classCache.html) is blocked if any of the
+http://doxygen.gem5.org/release/current/classgem5_1_1Cache.html) is blocked if any of the
 following is true:
 
-* [MSHR](http://doxygen.gem5.org/release/current/classMSHR.html) block is full.
+* [MSHR](http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html) block is full.
 (The size of MSHR’s buffer is configurable.)
 * Writeback block is full. (The size of the block’s buffer is configurable.)
 * The number of outstanding memory accesses against the same memory cache line
 has reached configurable threshold value – see [MSHR](
-http://doxygen.gem5.org/release/current/classMSHR.html) and Write Buffer for
+http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html) and Write Buffer for
 details.
 
-Data [Cache](http://doxygen.gem5.org/release/current/classCache.html) in block
+Data [Cache](http://doxygen.gem5.org/release/current/classgem5_1_1Cache.html) in block
 state will reject any request from slave port (from CPU) regardless of whether
 it would result in cache hit or miss. Note that incoming messages on master
 port (response messages and snoop requests) are never rejected.
 
-[Cache](http://doxygen.gem5.org/release/current/classCache.html) hit on uncachable
+[Cache](http://doxygen.gem5.org/release/current/classgem5_1_1Cache.html) hit on uncachable
 memory region (unpredicted behaviour according to ARM ARM) will invalidate
 cache line and fetch data from memory.
 
 ### Tags & Data Block
 
-[Cache](http://doxygen.gem5.org/release/current/classCache.html) lines (referred as
+[Cache](http://doxygen.gem5.org/release/current/classgem5_1_1Cache.html) lines (referred as
 blocks in source code) are organised into sets with configurable associativity
 and size. They have the following status flags:
 
@@ -127,7 +127,7 @@
 ### MSHR and Write Buffer Queues
 
 Miss Status and Handling Register ([MSHR](
-http://doxygen.gem5.org/release/current/classMSHR.html)) queue holds the list of
+http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html)) queue holds the list of
 CPU’s outstanding memory requests that require read access to lower memory
 level. They are:
 
@@ -143,11 +143,11 @@
 ![MSHR and Write Buffer Blocks](/assets/img/gem5_MS_Fig3.PNG)
 
 Each memory request is assigned to corresponding [MSHR](
-http://doxygen.gem5.org/release/current/classMSHR.html) object (READ or WRITE on
+http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html) object (READ or WRITE on
 diagram above) that represents particular block (cache line) of memory that has
 to be read or written in order to complete the command(s). As shown on gigure
 above, cached read/writes against the same cache line have a common [MSHR](
-http://doxygen.gem5.org/release/current/classMSHR.html) object and will be
+http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html) object and will be
 completed with a single memory access.
 
 The size of the block (and therefore the size of read/write access to lower
@@ -156,7 +156,7 @@
 * The size of cache line for cached access & writeback;
 * As specified in CPU instruction for uncached access.
 
-In general, Data [Cache](http://doxygen.gem5.org/release/current/classCache.html)
+In general, Data [Cache](http://doxygen.gem5.org/release/current/classgem5_1_1Cache.html)
 model distinguishes between just two memory types:
 
 * Normal Cached memory. It is always treated as write back, read and write
@@ -168,13 +168,13 @@
 
 An unique order number is assigned to each CPU read/write request(as they
 appear on slave port). Order numbers of [MSHR](
-http://doxygen.gem5.org/release/current/classMSHR.html) objects are copied from the
+http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html) objects are copied from the
 first assigned read/write.
 
 Memory read/writes from each of these two queues are executed in order
 (according to the assigned order number). When both queues are not empty the
 model will execute memory read from [MSHR](
-http://doxygen.gem5.org/release/current/classMSHR.html) block unless WriteBuffer is
+http://doxygen.gem5.org/release/current/classgem5_1_1MSHR.html) block unless WriteBuffer is
 full. It will, however, always preserve the order of read/writes on the same
 (or overlapping) memory cache line (block).
 
diff --git a/_pages/documentation/general_docs/thermal_model.md b/_pages/documentation/general_docs/thermal_model.md
index 4de1e76..2cbadf1 100644
--- a/_pages/documentation/general_docs/thermal_model.md
+++ b/_pages/documentation/general_docs/thermal_model.md
@@ -18,49 +18,49 @@
 
 Classes involved in the power model are:
 
-* [PowerModel](http://doxygen.gem5.org/release/current/classPowerModel.html):
+* [PowerModel](http://doxygen.gem5.org/release/current/classgem5_1_1ThermalResistor.html):
 Represents a power model for a hardware component.
 * [PowerModelState](
-http://doxygen.gem5.org/release/current/classPowerModelState.html): Represents a
+http://doxygen.gem5.org/release/current/classgem5_1_1PowerModelState.html): Represents a
 power model for a hardware component in a certain power state. It is an
 abstract class that defines an interface that must be implemented for each
 model.
 * [MathExprPowerModel](
-http://doxygen.gem5.org/release/current/classMathExprPowerModel.html): Simple
+http://doxygen.gem5.org/release/current/classgem5_1_1MathExprPowerModel.html): Simple
 implementation of [PowerModelState](
-http://doxygen.gem5.org/release/current/classPowerModelState.html) that assumes
+http://doxygen.gem5.org/release/current/classgem5_1_1PowerModelState.html) that assumes
 that power can be modeled using a simple power.
 
 Classes involved in the thermal model are:
 
-* [ThermalModel](http://doxygen.gem5.org/release/current/classThermalModel.html):
+* [ThermalModel](http://doxygen.gem5.org/release/current/classgem5_1_1ThermalModel.html):
 Contains the system thermal model logic and state. It performs the power query
 and temperature update. It also enables gem5 to query for temperature (for OS
 reporting).
-* [ThermalDomain](http://doxygen.gem5.org/release/current/classThermalDomain.html):
+* [ThermalDomain](http://doxygen.gem5.org/release/current/classgem5_1_1ThermalDomain.html):
 Represents an entity that generates heat. It's essentially a group of
-[SimObjects](http://doxygen.gem5.org/release/current/classSubSystem.html) grouped
+[SimObjects](http://doxygen.gem5.org/release/current/classgem5_1_1SubSystem.html) grouped
 under a SubSystem component that have its own thermal behaviour.
-* [ThermalNode](http://doxygen.gem5.org/release/current/classThermalNode.html):
+* [ThermalNode](http://doxygen.gem5.org/release/current/classgem5_1_1ThermalNode.html):
 Represents a node in the thermal circuital equivalent. The node has a
 temperature and interacts with other nodes through connections (thermal
 resistors and capacitors).
 * [ThermalReference](
-http://doxygen.gem5.org/release/current/classThermalReference.html): Temperature
+http://doxygen.gem5.org/release/current/classgem5_1_1ThermalReference.html): Temperature
 reference for the thermal model (essentially a thermal node with a fixed
 temperature), can be used to model air or any other constant temperature
 domains.
-* [ThermalEntity](http://doxygen.gem5.org/release/current/classThermalEntity.html):
+* [ThermalEntity](http://doxygen.gem5.org/release/current/classgem5_1_1ThermalEntity.html):
 A thermal component that connects two thermal nodes and models a thermal
 impedance between them. This class is just an abstract interface.
 * [ThermalResistor](
-http://doxygen.gem5.org/release/current/classThermalResistor.html): Implements
-[ThermalEntity](http://doxygen.gem5.org/release/current/classThermalEntity.html) to
+http://doxygen.gem5.org/release/current/classgem5_1_1ThermalResistor.html): Implements
+[ThermalEntity](http://doxygen.gem5.org/release/current/classgem5_1_1ThermalEntity.html) to
 model a thermal resistance between the two nodes it connects. Thermal
 resistances model the capacity of a material to transfer heat (units in K/W).
 * [ThermalCapacitor](
-http://doxygen.gem5.org/release/current/classThermalCapacitor.html): Implements
-[ThermalEntity](http://doxygen.gem5.org/release/current/classThermalEntity.html) to
+http://doxygen.gem5.org/release/current/classgem5_1_1ThermalCapacitor.html): Implements
+[ThermalEntity](http://doxygen.gem5.org/release/current/classgem5_1_1ThermalEntity.html) to
 model a thermal capacitance. Thermal capacitors are used to model material's
 thermal capacitance, this is, the ability to change a certain material
 temperature (units in J/K).
@@ -78,7 +78,7 @@
 entities (capacitors and resistors).
 
 Last step to conclude the thermal model is to create the [ThermalModel](
-http://doxygen.gem5.org/release/current/classThermalModel.html) instance itself and
+http://doxygen.gem5.org/release/current/classgem5_1_1ThermalModel.html) instance itself and
 attach all the instances used to it, so it can properly update them at runtime.
 Only one thermal model instance is supported right now and it will
 automatically report temperature when appropriate (ie. platform sensor
@@ -87,7 +87,7 @@
 ## Power model
 
 Every [ClockedObject](
-http://doxygen.gem5.org/release/current/classClockedObject.html) has a power model
+http://doxygen.gem5.org/release/current/classgem5_1_1ClockedObject.html) has a power model
 associated. If this power model is non-null power will be calculated at every
 stats dump (although it might be possible to force power evaluation at any
 other point, if the power model uses the stats, it is a good idea to keep both
@@ -100,7 +100,7 @@
 A power state model is essentially an interface that allows us to define two
 power functions for dynamic and static. As an example implementation a class
 called [MathExprPowerModel](
-http://doxygen.gem5.org/release/current/classMathExprPowerModel.html) has been
+http://doxygen.gem5.org/release/current/classgem5_1_1MathExprPowerModel.html) has been
 provided. This implementation allows the user to define a power model as an
 equation involving several statistics. There's also some automatic (or "magic")
 variables such as "temp", which reports temperature.
diff --git a/_pages/documentation/learning_gem5/part1/part1_6_extending_configs.md b/_pages/documentation/learning_gem5/part1/part1_6_extending_configs.md
index 23e2a89..4901587 100644
--- a/_pages/documentation/learning_gem5/part1/part1_6_extending_configs.md
+++ b/_pages/documentation/learning_gem5/part1/part1_6_extending_configs.md
@@ -55,11 +55,11 @@
 
 ```
 system.cpu.createInterruptController()
-#system.cpu.interrupts[0].pio = system.membus.master
-#system.cpu.interrupts[0].int_master = system.membus.slave
-#system.cpu.interrupts[0].int_slave = system.membus.master
+#system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+#system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+#system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
 
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 ```
 
 You can either delete or comment them out as above. Next let's set
diff --git a/_pages/documentation/learning_gem5/part2/part2_1_helloobject.md b/_pages/documentation/learning_gem5/part2/part2_1_helloobject.md
index 9b4e3e4..310d67f 100644
--- a/_pages/documentation/learning_gem5/part2/part2_1_helloobject.md
+++ b/_pages/documentation/learning_gem5/part2/part2_1_helloobject.md
@@ -71,6 +71,7 @@
 class HelloObject(SimObject):
     type = 'HelloObject'
     cxx_header = "learning_gem5/part2/hello_object.hh"
+    cxx_class = "gem5::HelloObject"
 ```
 
 [//]: # You can find the complete file
@@ -86,6 +87,10 @@
 of the SimObject with all lowercase and underscores, but this is only
 convention. You can specify any header file here.
 
+The `cxx_class` is an attribute specifying the newly created SimObject
+is declared within the gem5 namespace. Most SimObjects in the gem5 code
+base are declared within the gem5 namespace!
+
 Step 2: Implement your SimObject in C++
 ---------------------------------------
 
@@ -96,6 +101,9 @@
 gem5 wraps all header files in `#ifndef/#endif` with the name of the
 file and the directory its in so there are no circular includes.
 
+SimObjects should be declared within the gem5 namespace. Therefore,
+we declare our class within the `namespace gem5` scope.
+
 The only thing we need to do in the file is to declare our class. Since
 `HelloObject` is a SimObject, it must inherit from the C++ SimObject
 class. Most of the time, your SimObject's parent will be a subclass of
@@ -121,12 +129,17 @@
 #include "params/HelloObject.hh"
 #include "sim/sim_object.hh"
 
+namespace gem5
+{
+
 class HelloObject : public SimObject
 {
   public:
     HelloObject(const HelloObjectParams &p);
 };
 
+} // namespace gem5
+
 #endif // __LEARNING_GEM5_HELLO_OBJECT_HH__
 ```
 
@@ -148,11 +161,16 @@
 
 #include <iostream>
 
+namespace gem5
+{
+
 HelloObject::HelloObject(const HelloObjectParams &params) :
     SimObject(params)
 {
     std::cout << "Hello World! From a SimObject!" << std::endl;
 }
+
+} // namespace gem5
 ```
 
 **Note**: If the constructor of your SimObject follows the following
@@ -201,7 +219,7 @@
 ```python
 Import('*')
 
-SimObject('HelloObject.py')
+SimObject('HelloObject.py', sim_objects=['HelloObject'])
 Source('hello_object.cc')
 ```
 
diff --git a/_pages/documentation/learning_gem5/part2/part2_2_debugging.md b/_pages/documentation/learning_gem5/part2/part2_2_debugging.md
index 28aad86..ccc5d48 100644
--- a/_pages/documentation/learning_gem5/part2/part2_2_debugging.md
+++ b/_pages/documentation/learning_gem5/part2/part2_2_debugging.md
@@ -218,6 +218,7 @@
 In the `hello_object.cc` file, we need to include the header file.
 
 ```cpp
+#include "base/trace.hh"
 #include "debug/HelloExample.hh"
 ```
 
diff --git a/_pages/events/arm-summit-2017.md b/_pages/events/arm-summit-2017.md
index fbc78fb..d148f36 100644
--- a/_pages/events/arm-summit-2017.md
+++ b/_pages/events/arm-summit-2017.md
@@ -22,9 +22,9 @@
 # Streaming & Offline viewing
 
 The workshop is being streamed live and all talks will be available on
-YouTube after the workshop. See the [main summit
-page](https://developer.arm.com/research/summit/summit-live) for
-details.
+YouTube after the workshop.
+
+**An archive of the event can be found [here](https://youtube.com/playlist?list=PLgyFKd2HIZlY0E554m3qfp-ekm1a_Q7A4)**.
 
 # Target Audience
 
@@ -50,25 +50,25 @@
 
 | Time        | Topic                                                                                                                                                                             |
 | ----------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
-| 09.00-09.30 | Welcome and introduction to gem5 — [slides](Media:Summit2017_Intro_to_gem5.pdf "wikilink")                                                                                        |
-| 09.30-09.45 | [Interacting with gem5 using workload-automation & devlib](#WA "wikilink") — [slides](Media:Summit2017_wa_devlib.pdf "wikilink")                                                  |
-| 09.45-10.00 | [ARM Research Starter Kit: System Modeling using gem5](#StarterKit "wikilink") — [slides](Media:Summit2017_starterkit.pdf "wikilink")                                             |
+| 09.00-09.30 | Welcome and introduction to gem5                                                                                   |
+| 09.30-09.45 | [Interacting with gem5 using workload-automation & devlib](#WA "wikilink")                                               |
+| 09.45-10.00 | [ARM Research Starter Kit: System Modeling using gem5](#StarterKit "wikilink")                                            |
 | 10.00-10.15 | Break                                                                                                                                                                             |
 | 10.15-10.30 | [Debugging a target-agnostic JIT compiler with GEM5](#JIT_Debugging "wikilink")                                                                                                   |
-| 10.30-11.00 | [Learning gem5: Modeling Cache Coherence with gem5](#Ruby "wikilink") — [slides](Media:Summit2017_learning_gem5_ruby.pdf "wikilink")                                              |
+| 10.30-11.00 | [Learning gem5: Modeling Cache Coherence with gem5](#Ruby "wikilink")                                              |
 | 11.00-11.15 | Break (overlaps with main program break)                                                                                                                                          |
-| 11.15-11.45 | [A Detailed On-Chip Network Model inside a Full-System Simulator](#Garnet2 "wikilink") — [slides](Media:Summit2017_garnet2.0_tutorial.pdf "wikilink")                             |
-| 11.45-12.00 | [Integrating and quantifying the impact of low power modes in the DRAM controller in gem5](#DRAMPower "wikilink") — [slides](Media:Summit2017_drampower.pdf "wikilink")           |
+| 11.15-11.45 | [A Detailed On-Chip Network Model inside a Full-System Simulator](#Garnet2 "wikilink")                             |
+| 11.45-12.00 | [Integrating and quantifying the impact of low power modes in the DRAM controller in gem5](#DRAMPower "wikilink")            |
 | 12.00-12.15 | Break                                                                                                                                                                             |
-| 12.15-12.45 | [CPU power estimation using PMCs and its application in gem5](#PowMon "wikilink") — [slides](Media:Summit2017_powmon.pdf "wikilink")                                              |
-| 12.45-13.00 | [gem5: empowering the masses](#PowerFramework "wikilink") — [slides](Media:Summit2017_powerframework.pdf "wikilink")                                                              |
+| 12.15-12.45 | [CPU power estimation using PMCs and its application in gem5](#PowMon "wikilink")                                              |
+| 12.45-13.00 | [gem5: empowering the masses](#PowerFramework "wikilink")                                                              |
 | 13.00-14.15 | Lunch                                                                                                                                                                             |
-| 14.15-14.45 | [Trace-driven simulation of multithreaded applications in gem5](#ElasticSimMATE "wikilink") — [slides](Media:Summit2017_elasticsimmate.pdf "wikilink")                            |
-| 14.45-15.00 | [Generating Synthetic Traffic for Heterogeneous Architectures](#TraceGeneration "wikilink") — [slides](Media:Summit2017_trace_generation.pdf "wikilink")                          |
+| 14.15-14.45 | [Trace-driven simulation of multithreaded applications in gem5](#ElasticSimMATE "wikilink")                            |
+| 14.45-15.00 | [Generating Synthetic Traffic for Heterogeneous Architectures](#TraceGeneration "wikilink")                          |
 | 15:00-15:15 | Break                                                                                                                                                                             |
-| 15:15-16:45 | [System Simulation with gem5, SystemC and other Tools](#SystemC "wikilink") — [slides](Media:Summit2017_systemc.pdf "wikilink")                                                   |
-| 15:45-16:00 | [COSSIM: An Integrated Solution to Address the Simulator Gap for Parallel Heterogeneous Systems](#COSSIM "wikilink") — [slides](Media:Summit2017_COSSIM.pdf "wikilink")           |
-| 16:00-16:15 | [Simulation of Complex Systems Incorporating Hardware Accelerators](#ComplexSystems "wikilink") — [slides](Media:Summit2017_complex_fs_incorporating_accelerators.pdf "wikilink") |
+| 15:15-16:45 | [System Simulation with gem5, SystemC and other Tools](#SystemC "wikilink")                                                   |
+| 15:45-16:00 | [COSSIM: An Integrated Solution to Address the Simulator Gap for Parallel Heterogeneous Systems](#COSSIM "wikilink")          |
+| 16:00-16:15 | [Simulation of Complex Systems Incorporating Hardware Accelerators](#ComplexSystems "wikilink") |
 | 16:15-16:30 | Break                                                                                                                                                                             |
 | 16:30-18:15 | Introduction to ARM Research                                                                                                                                                      |
 | 18:20-20.00 | Poster Session & Pre-Dinner Drinks                                                                                                                                                |
@@ -76,7 +76,7 @@
 
 # Talks
 
-<span id="ElasticSimMATE">
+<span id="ElasticSimMATE"/>
 
 ## Trace-driven simulation of multithreaded applications in gem5
 
@@ -152,9 +152,7 @@
 > Ukraine. During her Master she participated on the international
 > program of double diploma between Montpellier and Kiev universities.
 
-</span>
-
-<span id="Ruby">
+<span id="Ruby"/>
 
 ## Modeling Cache Coherence with gem5
 
@@ -184,9 +182,7 @@
 > Distinguished Graduate Fellowship Cisco Computer Sciences Award in
 > 2014 and 2015.
 
-</span>
-
-<span id="Garnet2">
+<span id="Garnet2"/>
 
 ## A Detailed On-Chip Network Model inside a Full-System Simulator
 
@@ -234,9 +230,7 @@
 > interconnection networks, networks-on-chip, deep learning
 > accelerators, and FPGAs.
 
-</span>
-
-<span id="SystemC">
+<span id="SystemC"/>
 
 ## System Simulation with gem5, SystemC and other Tools
 
@@ -266,9 +260,7 @@
 > modeling of widely heterogeneous hardware as well dataflow compilers
 > for heterogeneous MPSoC platforms.
 
-</span>
-
-<span id="PowMon">
+<span id="PowMon"/>
 
 ## CPU power estimation using PMCs and its application in gem5
 
@@ -320,11 +312,9 @@
 > the General Chair of the European Workshop on Microelectronics
 > Education 2016. He is a member of the IEEE, IET and Fellow of the HEA.
 
-</span>
-
 # Short Talks
 
-<span id="JIT_Debugging">
+<span id="JIT_Debugging"/>
 
 ## Debugging a target-agnostic JIT compiler with GEM5
 
@@ -341,9 +331,8 @@
 present a new debugger based on simulating the execution of the target
 runtime VM in GEM5; the debugger frontend connects to this simulation
 using the RSP wire protocol.
-</span>
 
-<span id="COSSIM">
+<span id="COSSIM"/>
 
 ## COSSIM: An Integrated Solution to Address the Simulator Gap for Parallel Heterogeneous Systems
 
@@ -402,9 +391,7 @@
 > Computer Engineering in which he specialized in Computer Architecture
 > and Hardware Design.
 
-</span>
-
-<span id="ComplexSystems">
+<span id="ComplexSystems"/>
 
 ## Simulation of Complex Systems Incorporating Hardware Accelerators
 
@@ -453,9 +440,7 @@
 > Computer Engineering in which he specialized in Computer Architecture
 > and Hardware Design.
 
-</span>
-
-<span id="TraceGeneration">
+<span id="TraceGeneration"/>
 
 ## Generating Synthetic Traffic for Heterogeneous Architectures
 
@@ -491,9 +476,7 @@
 > include performance evaluation in computer architecture, heterogeneous
 > architectures, and multi-threaded workloads.
 
-</span>
-
-<span id="StarterKit">
+<span id="StarterKit"/>
 
 ## ARM Research Starter Kit: System Modeling using gem5
 
@@ -513,9 +496,7 @@
 > research enablement activities at ARM, which cover a range of
 > different research areas from SoC design to IoT and data science.
 
-</span>
-
-<span id="WA">
+<span id="WA"/>
 
 ## Interacting with gem5 using workload-automation & devlib
 
@@ -531,9 +512,7 @@
 > London, where she investigated the effects of optical interconnects on
 > the performance of chip multiprocessors, using gem5.
 
-</span>
-
-<span id="PowerFramework">
+<span id="PowerFramework"/>
 
 ## gem5: empowering the masses
 
@@ -552,9 +531,8 @@
 > ideally without impacting the delivered
 performance.
 
-</span>
 
-<span id="DRAMPower">
+<span id="DRAMPower"/>
 
 ## Integrating and quantifying the impact of low power modes in the DRAM controller in gem5
 
@@ -587,6 +565,3 @@
 > several collaborative research projects, especially with academics.
 > Currently she is exploring the problem of energy efficient data
 > movement for sparse data workloads.
-
-</span>
-
diff --git a/_pages/events/boot-camp-2022.md b/_pages/events/boot-camp-2022.md
index ca413ae..0ac0ede 100644
--- a/_pages/events/boot-camp-2022.md
+++ b/_pages/events/boot-camp-2022.md
@@ -5,13 +5,17 @@
 
 We are happy to announce the first gem5 Boot Camp, to be held at UC Davis from July 11th to July 15th 2022.
 The purpose of the gem5 Boot Camp is for junior computer architecture researchers, particularly PhD. students, to learn how to use gem5 in their projects.
-The Boot Camp, held over 5 days, will take attendees through setting up basic system simulations, creating your own components, learning to interpret gem5 status, and up to running and modifying simulations comparable to real-world systems.
+The Boot Camp, held over 5 days, will take attendees through setting up basic system simulations, creating bespoke components, learning to interpret gem5 stats, and up to running and modifying simulations comparable to real-world systems.
 
-**This event is free for all accepted attendees**. There is no cost for registration, accommodation and meals will be provided, and travel grants are available.
+**This event is free for all accepted attendees**. There is no cost for registration.
+Accommodation and meals will be provided, and travel grants will be available.
+
+**Important Note:** Registration for this event is now closed.
 
 ## Key Dates
 
 * Boot camp: **July 11th to July 15th 2022**
+* ~~Application deadline: **May 18th 2022** (Apply [here](https://forms.gle/3wWPsMDfXyaChmQ68))~~
 
 ## When and where is the Boot Camp?
 
@@ -45,9 +49,11 @@
 
 ## How can I apply?
 
-We are not yet ready to process applications to attend this event.
-If you wish to be notified when we are ready, please register your interest here: <https://forms.gle/AztSG3mD2BqQ4f967>.
+Registration for this event this event is now closed.
 
+~~Those wishing to attend can fill out the following Google Form by **May 18th**: <https://forms.gle/3wWPsMDfXyaChmQ68>~~
+
+~~If your application was successful you will be contacted, via the email address provided, by June 1st.~~
 
 ## What does it cost?
 
@@ -56,3 +62,27 @@
 Accommodation on the UC Davis campus, meals, and social events will be provided as part of the event.
 
 We will be offering travel grants which can be applied for to cover transport expenses after the event.
+
+## Tentative schedule
+
+|Session| Topic | Objectives|
+| :---  | :---  | :--- |
+| Monday Morning | Welcome and Introduction | |
+| | Building gem5 |- Learn about the gem5 dependencies <br> - Be introduced to SCons <br> - Understand the different gem5 binary types (opt, debug, fast)|
+| | Python basics | - A recap of basic Python skills needed to use gem5 <br> - Object-oriented programming reminder <br> - Run a simple python script in gem5 |
+| | Using gem5 basics | - Understand gem5 configuration scripts and its python interpreter <br> - Understand what the `m5` and `gem5` libraries are <br> - Get a general architecture outline of gem5 <br> - Obtain and understand the stats output <br> - Understand the `config.ini` file |
+| | About simulation | - Learn about common gem5 terminology: "host", "guest", etc. <br> - Learn about the difference between Full-System and Syscall emulation mode |
+| Monday Afternoon | The gem5 standard library | - Use the stdlib components to build a simulated system <br> - Use the stdlib `resource` class to automatically obtain gem5-resources to use in their experiment <br> - Create a gem5 resource custom resource <br> - Set workloads for a simulated system via the `set_workload` functions <br> - Create functions to run on specific exit events <br> - Create an stdlib component|
+| | **Welcome dinner** | |
+|Tuesday Morning | Using gem5 models | - Use different gem5 CPU models (Timing Simple, Atomic, O3, Minor, Trace, etc.) <br> - Use classic caches in a simulation <br> - Use Ruby caches in a simulation (understand the different coherence protocols, how to compile them and how to create a cache hierarchy via a simple network) |
+| | Using gem5 to run things | - Use traffic generators to test memory systems <br> - Incorporate the m5 utility into workloads <br> - Learn to use cross-compilers for non-host ISA workloads <br> - Learn how to output and parse stats|
+| Tuesday Afternoon| Full system simulation | - Create a disk image for FS simulations <br> - Create and add and modify gem5 resources <br> - Learn how to use the `m5 readfile` interface|
+| | Accelerating Simulation | - Create checkpoints <br> - Load from checkpoints <br> - Fastforward a simulation <br> - Employ sampling techniques <br> - Learn about KVM |
+| Wednesday Morning| Creating your own SimObjects| - Understand how a request travels through the system <br> - Implement a SimObject <br> - Learn how to model real-world hardware timing <br> - Learn how to add SimStats and how it maps to real-world hardware <br> - Debug a gem5 SimObject |
+| Wednesday Afternoon| Adding your own instructions| - Understand the details of the ISA sub-system <br> - Extend gem5 to simulate an unsupported instruction <br> - Understand the differences between modeling a user-mode and supervisor mode instruction <br> - Understand gem5 debug traces for a particular execution |
+| Thursday Morning | Advanced topics in memory systems | - Learn how to extend a packet with a new MemCmd <br> - Learn how to use Garnet (How to create different network topologies with specific characteristics; using the Garnet synthetic traffic; and understanding the output statistics) <br> -  Create and extend cache coherence protocols (create a classic coherence protocol; design a Ruby coherence protocol)|
+| Thursday Afternoon | The gem5 GPU Model | [TBD] |
+| | **Group Social Event** | |
+| Friday Morning | Writing tests and contributing to gem5 | - Write a GTest to test a piece of CPP code <br> - Write a PyUnit test to test a python function <br> - Use testlib to test a gem5 simulation condition <br> - Run Testlib/PyUnit/GUnit tests for gem5 <br> - Understand gem5's quick/Kokoro, long/Nightly, very-long/Weekly test structure <br> - Understand gem5's code-formatting guidelines <br> - Use git to add code to the repo <br> - Review patches on Gerrit <br> - Respond to feedback on Gerrit |
+| Friday Afternoon | gem5 extensions and other simulators | - Incorporate SST into a simulation <br> - Incorporate DRAMSim into a simulation <br> - Use SystemC in gem5 and gem5 in SystemC |
+| | Wrapping things up | |
diff --git a/_pages/events/isca-2006.md b/_pages/events/isca-2006.md
index 699a1a0..db5d669 100644
--- a/_pages/events/isca-2006.md
+++ b/_pages/events/isca-2006.md
@@ -28,7 +28,7 @@
 not commonly found in other simulators.
 
   - Full-system simulation using unmodified Linux 2.4/2.6, HP Tru64 5.1,
-    or [L4Ka::Pistachio](http://l4ka.org/projects/pistachio)) (Alpha
+    or [L4Ka::Pistachio](https://www.l4ka.org/65.php) (Alpha
     only at this time... coming in the future for MIPS and SPARC)
   - Detailed timing of I/O device accesses and DMA operations
   - Accurate, deterministic simulation of multiple networked systems
diff --git a/_pages/events/isca-2020.md b/_pages/events/isca-2020.md
index df62d49..aef9d87 100644
--- a/_pages/events/isca-2020.md
+++ b/_pages/events/isca-2020.md
@@ -8,7 +8,7 @@
 
 **Update on the gem5 Tutorial:** The gem5 tutorial will be postponed.
 We are planning to hold an online class this summer.
-Stay tuned and subscribe to the [gem5-users](https://lists.gem5.org/postorius/lists/gem5-users.gem5.org/) and [gem5-announce](https://lists.gem5.org/postorius/lists/gem5-announce.gem5.org/) mailing list for more information.
+Stay tuned and subscribe to the [gem5-users and gem5-announce mailing list](/mailing_lists) for more information.
 
 ## 3rd gem5 Users' Workshop (The first virtual version!)
 
diff --git a/_pages/events/isca-2022.md b/_pages/events/isca-2022.md
index bc4c4ac..e26908d 100644
--- a/_pages/events/isca-2022.md
+++ b/_pages/events/isca-2022.md
@@ -3,7 +3,7 @@
 permalink: events/isca-2022
 ---
 
-We are happy to announce the gem5 Tutorial and Users' Workshop, to be co-located with [ISCA 2022](https://iscaconf.org/isca2022/), in New York City, on **Saturday June 11th 2022**. **We intend for this event to be held in person** assuming no worsening COVID travel restrictions.
+We are happy to announce the gem5 Tutorial and Users' Workshop, to be co-located with [ISCA 2022](https://iscaconf.org/isca2022/), in New York City, on **Saturday June 18th 2022**. **We intend for this event to be held in person** assuming no worsening COVID travel restrictions.
 
 The gem5 Tutorial will be held in the morning session and will focus on teaching those new to gem5 how to use the latest version.
 It will be "crash course" in gem5 and assume no prior knowledge of using computer architecture simulators.
@@ -17,16 +17,16 @@
 
 ## Key Dates
 
-* Workshop presentation proposal deadline: **April 19th 2022** (Presentation abstracts can be submitted [here](https://forms.gle/VZxXsWBniUPGBQdw5))
-* Workshop acceptance notifications: **May 2nd 2022**
-* ISCA Conference: **June 11th to June 15th 2022**
-* gem5 Tutorial: **June 11th 2022 (Morning Session)**
-* gem5 Users' Workshop: **June 11th 2022 (Afternoon Session)**
+* ~~Workshop presentation proposal deadline: **April 26th 2022** (Presentation abstracts can be submitted [here](https://forms.gle/VZxXsWBniUPGBQdw5))~~
+* ~~Workshop acceptance notifications: **May 9th 2022**~~
+* ISCA Conference: **June 18th to June 22th 2022**
+* gem5 Tutorial: **June 18th 2022 (Morning Session)**
+* gem5 Users' Workshop: **June 18th 2022 (Afternoon Session)**
 
 ## The 4th gem5 Tutorial
 
 The gem5 tutorial is designed to give computer architecture researchers, particularly those with no prior experience using a computer architecture simulator, the opportunity to learn how to use gem5.
-It will be held on the morning session of **Saturday June 11th 2022**.
+It will be held on the morning session of **Saturday June 18th 2022**.
 
 Please keep an eye on the [ISCA 2022 event page](https://iscaconf.org/isca2022/) for details on registering for this event.
 
@@ -58,20 +58,41 @@
 
 ## The 4th gem5 Users' Workshop
 
-The gem5 User's workshop will be held on **Saturday June 11th 2022**, in the afternoon session.
+The gem5 User's workshop will be held on **Saturday June 18th 2022**, in the afternoon session.
 The workshop will start with a 30 minute keynote presentation by Prof. Jason Lowe-Power titled "Recent Advancements in Mainline gem5 v20.0 -- v21.2".
 This will be followed by a series of 15 minutes presentations.
 These presentations are an opportunity for users of gem5 to present gem5-related work and foster discussion.
 
-Presentations are solicited on a broad ranges of topics relating to gem5, including (but not limited to):
+### Schedule
 
-* New gem5 features and models
-* Improved models.
-* Validation against real hardware.
-* Software engineering related to gem5.
-* Experiences using gem5.
-* Tools, visualizations, data analysis tools, etc.
+|Time | Presentation | Presenter |
+|:--  | :--          | :--       |
+|1:30pm | Recent Advancements in mainline gem5 v20.0 -- v21.2 | Jason Lowe-Power |
+|       | Modeling an HBM2 Memory Controller | Ayaz Akram |
+|       | Porting the LupIO Devices into gem5 | Melissa Jost |
+|       | gem5/SST Integration 2021: Scaling Full-system Simulations| Hoa Nguyen |
+|2:15pm | The Case for Using Guix to Solve the gem5 Packing Problem | Christopher Batten |
+|2:30pm | **Coffee Break** | --- |
+|3:00pm | Booting OP-TEE and Penetration Testing with gem5 | Quentin Forcioli |
+|3:15pm | vSwam-u: Unlocking Microarchitectural Research for Severless | David Schall |
+|3:30pm | gem5 GPU Accuracy Profiler (GAP) | Charles Jamieson |
+|3:45pm | A Cycle-level Unified DRAM Cache Controller Model in gem5 | Maryam Babaie |
+|4:00pm | Validating gem5's Memory Components | Mahyar Samani |
+|4:15pm | Design Space Exploration for Custom Hardware Designs in gem5-SALAM | Zephan Spencer|
+|4:30pm | Arms Race in Microarchitectural Security and How gem5 can help! | Guruaj Saileshwar |
+|4:45pm | Loupe 2.0: A Noc Visualization Tool for Garnet | Tushar Krishna and Canlin Zhang |
+|5:00pm | Closing Remarks | Jason Lowe-Power |
 
-If you wish to present at this year's gem5 User's workshop please provide a presentation proposal (a 1 page PDF) here: <https://forms.gle/VZxXsWBniUPGBQdw5>. **Note: This is an in-person event. The presenter must attend the workshop**.
+### The Users' Workshop Program Committee
 
-The deadline for submitting a presentation proposal is **April 19th** with acceptance notifications sent out by **May 2nd**.
\ No newline at end of file
+* Jason Lowe-Power, UC Davis
+* Matt Sinclair, University of Wisconsin, Madison
+* Bobby R. Bruce, UC Davis
+* Srikant Bharadwaj, AMD
+* Daniel Carvaldo
+* Andreas Sandberg, ARM
+* Giacomo Travaglini, ARM
+* Nikos Nikoleris, ARM
+* Matt Poremba, AMD
+* Lena Olson, Google
+* Wendy Elsasser, Rambus
diff --git a/_pages/mailing_list.md b/_pages/mailing_list.md
index e5a9321..49b2a44 100644
--- a/_pages/mailing_list.md
+++ b/_pages/mailing_list.md
@@ -6,17 +6,12 @@
 
 There are three mailing lists for gem5:
 
-* gem5-dev ([subscribe](
-https://lists.gem5.org/postorius/lists/gem5-dev.gem5.org/)) --- Discussions
-regarding gem5 development. Bug reports should be submitted to our
-[Jira Issue Tracker](https://gem5.atlassian.net), though the gem5-dev mailing
-list can be used to discuss bugs in greater detail.
-* gem5-users ([subscribe](
-https://lists.gem5.org/postorius/lists/gem5-users.gem5.org/)) --- General
-discussions about gem5 and its use.
-* gem5-announce ([subscribe](
-https://lists.gem5.org/postorius/lists/gem5-announce.gem5.org)) --- General
-gem5 annoucements.
+* **gem5-dev@gem5.org** : For discussions regarding gem5 development.
+Those wishing to post to and/or receive mail from the list should subscribe by sending an email to [gem5-dev-join@gem5.org](mailto:gem5-dev-join@gem5.org) or at <https://harmonylists.io/list/gem5-dev.gem5.org>.
+* **gem5-users@gem5.org** : For general discussions about gem5 and its use. Those wishing to post to and/or receive mail from the list should subscribe by sending an email to [gem5-users-join@gem5.org](mailto:gem5-users-join@gem5.org) or at <https://harmonylists.io/list/gem5-users.gem5.org>.
+* **gem5-announce@gem5.org** : For general gem5 announcements. Those wishing to receive mail from this list should subscribe by sending an email to [gem5-announce-join@gem5.org](mailto:gem5-announce-join@gem5.org) or at <https://harmonylists.io/list/gem5-announce.gem5.org>.
+
+Bug reports should be submitted to our [Jira Issue Tracker](https://gem5.atlassian.net).
 
 # Mail Archive
 
diff --git a/_pages/publications.md b/_pages/publications.md
index 575c168..46f2b88 100644
--- a/_pages/publications.md
+++ b/_pages/publications.md
@@ -221,7 +221,7 @@
 * _Register Multimapping: Reducing Register Bank Conflicts Through One-To-Many Logical-To-Physical Register Mapping._ N. L. Duong and R. Kumar. Technical Report CHRC-08-07. <!-- XXX: Also published as doi:10.1109/SASP.2009.5226335. -->
 * _Cross-Layer Custimization Platform for Low-Power and Real-Time Embedded Applications._ X. Zhou. Dissertation at the University of Maryland. 2008.
 * _Probabilistic Replacement: Enabling Flexible Use of Shared Caches for CMPs_. W. Liu and D. Yeung. University of Maryland Technical Report UMIACS-TR-2008-13. 2008. [pdf](http://maggini.eng.umd.edu/pub/UMIACS-TR-2008-13.pdf)
-* _Observer Effect and Measurement Bias in Performance Analysis_. T. Mytkowicz, P. F. Sweeney, M. Hauswirth, and A. Diwan. University of Colorado at Boulder Technical Report CU-CS 1042-08. June, 2008. [pdf](https://www.inf.usi.ch/faculty/hauswirth/publications/CU-CS-1042-08.pdf)
+* _Observer Effect and Measurement Bias in Performance Analysis_. T. Mytkowicz, P. F. Sweeney, M. Hauswirth, and A. Diwan. University of Colorado at Boulder Technical Report CU-CS 1042-08. June, 2008. [pdf](https://scholar.colorado.edu/downloads/2v23vv18b)
 * _Power-Aware Dynamic Cache Partitioning for CMPs_. I. Kotera, K. Abe, R. Egawa, H. Takizawa, and H. Kobayashi. 3rd International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC). 2008. <!-- XXX: Published as doi:10.1007/978-3-642-19448-1_8 (2011). -->
 * [**Modeling of Cache Access Behavior Based on Zipf’s Law**](https://dl.acm.org/doi/10.1145/1509084.1509086). I. Kotera, H. Takizawa, R. Egawa, H. Kobayashi. MEDEA 2008. doi:[10.1145/1509084.1509086](https://dx.doi.org/10.1145/1509084.1509086).
 * [**Hierarchical Verification for Increasing Performance in Reliable Processors**](https://link.springer.com/article/10.1007%2Fs10836-007-5037-z). J. Yoo, M. Franklin. Journal of Electronic Testing. June 2008. doi:[10.1007/s10836-007-5037-z](https://dx.doi.org/10.1007/s10836-007-5037-z).
@@ -268,7 +268,7 @@
 * _When Homogeneous becomes Heterogeneous: Wearout Aware Task Scheduling for Streaming Applications_. D. Roberts, R. Dreslinski, E. Karl, T. Mudge, D. Sylvester, D. Blaauw. Workshop on Operating System Support for Heterogeneous Multicore Architectures (OSHMA). September 2007. [pdf](https://tnm.engin.umich.edu/wp-content/uploads/sites/353/2017/12/2007.09.When_Homogeneous_becomes_Heterogeneous_PACT.pdf)
 * [**On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology**](https://ieeexplore.ieee.org/document/4341526). D. Roberts, N. Kim,T. Mudge. Digital System Design Architectures, Methods and Tools (DSD). August 2007. doi:[10.1109/DSD.2007.4341526](https://dx.doi.org/10.1109/DSD.2007.4341526). [pdf](https://tnm.engin.umich.edu/wp-content/uploads/sites/353/2017/12/2007.08.On-chip-cache-device-scaling-limits-and-effective-fault-repair.pdf)
 * [**Energy Efficient Near-threshold Chip Multi-processing**](https://dl.acm.org/doi/10.1145/1283780.1283789). B. Zhai, R. Dreslinski, D. Blaauw, T. Mudge, D. Sylvester. International Symposium on Low Power Electronics and Design (ISLPED). August 2007. doi:[10.1145/1283780.1283789](https://dx.doi.org/10.1145/1283780.1283789). [pdf](https://blaauw.engin.umich.edu/wp-content/uploads/sites/342/2018/02/Zhai-Energy-Efficent-Near-threshold-Chip-Multi-processing.pdf)
-* [**A Burst Scheduling Access Reordering Mechanism**](https://ieeexplore.ieee.org/document/4147669). J. Shao, B.T. Davis. IEEE 13th International Symposium on High Performance Computer Architecture (HPCA). 2007. doi:[10.1109/HPCA.2007.346206](https://dx.doi.org/10.1109/HPCA.2007.346206). [pdf](http://mercury.pr.erau.edu/~davisb22/papers/burst_scheduling_hpca13.pdf)
+* [**A Burst Scheduling Access Reordering Mechanism**](https://ieeexplore.ieee.org/document/4147669). J. Shao, B.T. Davis. IEEE 13th International Symposium on High Performance Computer Architecture (HPCA). 2007. doi:[10.1109/HPCA.2007.346206](https://dx.doi.org/10.1109/HPCA.2007.346206).
 * _Enhancing LTP-Driven Cache Management Using Reuse Distance Information_. W. Liu, D. Yeung. University of Maryland Technical Report UMIACS-TR-2007-33. June 2007. [pdf](http://maggini.eng.umd.edu/pub/UMIACS-TR-2007-33.pdf)
 * [**Thermal modeling and management of DRAM memory systems**](https://ieeexplore.ieee.org/document/6212452). J. Lin, H. Zheng, Z. Zhu, H. David, and Z. Zhang. Proceedings of the 34th Annual international Symposium on Computer Architecture (ISCA). June 2007. doi:[10.1109/TC.2012.118](https://dx.doi.org/10.1109/TC.2012.118).
 * _Duplicating and Verifying LogTM with OS Support in the M5 Simulator_. G. Blake, T. Mudge. Sixth Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD). June 2007. [pdf](https://pharm.ece.wisc.edu/wddd/2007/papers/wddd_03.pdf)
diff --git a/_posts/2021-04-25-gem5-21-1-roadmap.md b/_posts/2021-04-25-gem5-21-1-roadmap.md
index cafb12f..2f2f95c 100644
--- a/_posts/2021-04-25-gem5-21-1-roadmap.md
+++ b/_posts/2021-04-25-gem5-21-1-roadmap.md
@@ -14,7 +14,7 @@
 
 1. Create a issue or an epic on our [issue tracker](https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/). If the contribution is large with many different individual contributions, it would be best to create an epic to group all of the separate issues together.
 2. Mark the issue as "Fix version 21.1" and assign yourself as the "Assignee".
-3. Update [this roadmap document](https://gem5.googlesource.com/public/gem5-website/+/refs/heads/stable/_posts/2021-05-01-gem5-21-1-roadmap.md) by [downloading the website source](https://gem5.googlesource.com/public/gem5-website/) and creating a changeset [on gerrit](https://gem5.googlesource.com/public/gem5-website/+/refs/heads/stable/README.md).
+3. Update [this roadmap document](https://gem5.googlesource.com/public/gem5-website/+/refs/heads/stable/_posts/2021-04-25-gem5-21-1-roadmap.md) by [downloading the website source](https://gem5.googlesource.com/public/gem5-website/) and creating a changeset [on gerrit](https://gem5.googlesource.com/public/gem5-website/+/refs/heads/stable/README.md).
 
 ## Roadmap for 21.1