diff --git a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
index 3bd3133..8f5e405 100644
--- a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
+++ b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
@@ -142,8 +142,8 @@
 the membus. In this example system, we have no caches.
 
 ```
-system.cpu.icache_port = system.membus.slave
-system.cpu.dcache_port = system.membus.slave
+system.cpu.icache_port = system.membus.cpu_side_ports
+system.cpu.dcache_port = system.membus.cpu_side_ports
 ```
 
 > **An aside on gem5 ports**
@@ -182,11 +182,11 @@
 
 ```
 system.cpu.createInterruptController()
-system.cpu.interrupts[0].pio = system.membus.master
-system.cpu.interrupts[0].int_master = system.membus.slave
-system.cpu.interrupts[0].int_slave = system.membus.master
+system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
 
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 ```
 
 Next, we need to create a memory controller and connect it to the
@@ -194,9 +194,10 @@
 be responsible for the entire memory range of our system.
 
 ```
-system.mem_ctrl = DDR3_1600_8x8()
-system.mem_ctrl.range = system.mem_ranges[0]
-system.mem_ctrl.port = system.membus.master
+system.mem_ctrl = MemCtrl()
+system.mem_ctrl.dram = DDR3_1600_8x8()
+system.mem_ctrl.dram.range = system.mem_ranges[0]
+system.mem_ctrl.dram.port = system.membus.mem_side_ports
 ```
 
 After those final connections, we've finished instantiating our
@@ -241,8 +242,13 @@
 execution contexts in the CPU.
 
 ```
+binary = 'tests/test-progs/hello/bin/x86/linux/hello'
+
+#for gem5 V21 and beyond, uncomment the following line
+#system.workload = SEWorkload.init_compatible(binary)
+
 process = Process()
-process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello']
+process.cmd = [binary]
 system.cpu.workload = process
 system.cpu.createThreads()
 ```
diff --git a/_pages/documentation/learning_gem5/part1/part1_3_cache_config.md b/_pages/documentation/learning_gem5/part1/part1_3_cache_config.md
index 8f51044..2cc018f 100644
--- a/_pages/documentation/learning_gem5/part1/part1_3_cache_config.md
+++ b/_pages/documentation/learning_gem5/part1/part1_3_cache_config.md
@@ -221,8 +221,8 @@
 ports directly to the memory bus.
 
 ```
-system.cpu.icache_port = system.membus.slave
-system.cpu.dcache_port = system.membus.slave
+system.cpu.icache_port = system.membus.cpu_side_ports
+system.cpu.dcache_port = system.membus.cpu_side_ports
 ```
 
 We can't directly connect the L1 caches to the L2 cache since the L2