| commit | f5147d8193aac94d9554b3197e2239266902776d | [log] [tgz] |
|---|---|---|
| author | Laura Hinman <llhinman@ucdavis.edu> | Thu Jul 08 17:16:53 2021 -0700 |
| committer | Laura Hinman <llhinman@ucdavis.edu> | Fri Jul 09 22:25:43 2021 +0000 |
| tree | d9c3c4c909281b909301a212a8b6ea76d0a3d516 | |
| parent | f63ae1e9eb9a0985f889bf8eb7102dbe416f79b5 [diff] |
website: Fixed typo in learning gem5 part 1 Change-Id: Ib650d8bdc2029b6d5b3122ffeea79623075b77f2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-website/+/47841 Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md index a8b495d..53fa0c7 100644 --- a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md +++ b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
@@ -221,7 +221,7 @@ system.mem_ctrl = MemCtrl() system.mem_ctrl.dram = DDR3_1600_8x8() system.mem_ctrl.dram.range = system.mem_ranges[0] -system.mem_ctrl.dram.port = system.membus.mem_side_ports +system.mem_ctrl.port = system.membus.mem_side_ports ``` After those final connections, we've finished instantiating our