diff --git a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
index 4443f44..e1b2f39 100644
--- a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
+++ b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
@@ -126,15 +126,20 @@
 ```
 
 Now, we can create a CPU. We'll start with the most simple timing-based
-CPU in gem5, *TimingSimpleCPU*. This CPU model executes each instruction
+CPU in gem5 for the X86 ISA, *X86TimingSimpleCPU*. This CPU model executes each instruction
 in a single clock cycle to execute, except memory requests, which flow
 through the memory system. To create the CPU you can simply just
 instantiate the object:
 
 ```
-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()
 ```
 
+If we wanted to use the RISCV ISA we could use `RiscvTimingSimpleCPU` or if
+we wanted to use the ARM ISA we could use `ArmTimingSimpleCPU`. However, we
+will continue to use the X86 ISA for this exercise.
+
+
 Next, we're going to create the system-wide memory bus:
 
 ```
@@ -346,11 +351,29 @@
 simulation should finish faster. Or, if you change the DDR controller to
 DDR4, the performance should be better.
 
-Additionally, you can change the CPU model to `MinorCPU` to model an
-in-order CPU, or `DerivO3CPU` to model an out-of-order CPU. However,
-note that `DerivO3CPU` currently does not work with simple.py, because
-`DerivO3CPU` requires a system with separate instruction and data caches
-(`DerivO3CPU` does work with the configuration in the next section).
+Additionally, you can change the CPU model to `X86MinorCPU` to model an
+in-order CPU, or `X86O3CPU` to model an out-of-order CPU. However,
+note that `X86O3CPU` currently does not work with simple.py, because
+`X86O3CPU` requires a system with separate instruction and data caches
+(`X86O3CPU` does work with the configuration in the next section).
+
+All gem5 BaseCPU's take the naming format `{ISA}{Type}CPU`. Ergo, if we wanted
+a RISCV Minor CPU we'd use `RiscvMinorCPU`.
+
+The Valid ISAs are:
+* Riscv
+* Arm
+* X86
+* Sparc
+* Power
+* Mips
+
+The CPU types are:
+* AtomicSimpleCPU
+* O3CPU
+* TimingSimpleCPu
+* KvmCPU
+* MinorCPU
 
 Next, we will add caches to our configuration file to model a more
 complex system.
diff --git a/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md b/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
index fa48250..3f42b81 100644
--- a/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
+++ b/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
@@ -187,7 +187,7 @@
 m5out/config.ini. The CPU is shown on line 51:
 
     [system.cpu]
-    type=AtomicSimpleCPU
+    type=X86AtomicSimpleCPU
     children=interrupts isa mmu power_state tracer workload
     branchPred=Null
     checker=Null
diff --git a/_pages/documentation/learning_gem5/part2/part2_5_memoryobject.md b/_pages/documentation/learning_gem5/part2/part2_5_memoryobject.md
index 9908007..0eb4174 100644
--- a/_pages/documentation/learning_gem5/part2/part2_5_memoryobject.md
+++ b/_pages/documentation/learning_gem5/part2/part2_5_memoryobject.md
@@ -698,7 +698,7 @@
 system.mem_mode = 'timing'
 system.mem_ranges = [AddrRange('512MB')]
 
-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()
 
 system.memobj = SimpleMemobj()
 
@@ -782,7 +782,7 @@
      ...
 
 You may also want to change the CPU model to the out-of-order model
-(`DerivO3CPU`). When using the out-of-order CPU you will potentially see
+(`X86O3CPU`). When using the out-of-order CPU you will potentially see
 a different address stream since it allows multiple memory requests
 outstanding at a once. When using the out-of-order CPU, there will now
 be many stalls because the `SimpleMemobj` is blocking.
diff --git a/_pages/documentation/learning_gem5/part3/part3_08_configuration.md b/_pages/documentation/learning_gem5/part3/part3_08_configuration.md
index 275c08d..059d318 100644
--- a/_pages/documentation/learning_gem5/part3/part3_08_configuration.md
+++ b/_pages/documentation/learning_gem5/part3/part3_08_configuration.md
@@ -23,7 +23,7 @@
 First, so we can test our *coherence* protocol, let's use two CPUs.
 
 ```python
-system.cpu = [TimingSimpleCPU(), TimingSimpleCPU()]
+system.cpu = [X86TimingSimpleCPU(), X86TimingSimpleCPU()]
 ```
 
 Next, after the memory controllers have been instantiated, we are going
@@ -113,15 +113,12 @@
 
 def sendEvicts(self, cpu):
     """True if the CPU model or ISA requires sending evictions from caches
-       to the CPU. Two scenarios warrant forwarding evictions to the CPU:
+       to the CPU. Three scenarios warrant forwarding evictions to the CPU:
        1. The O3 model must keep the LSQ coherent with the caches
        2. The x86 mwait instruction is built on top of coherence
        3. The local exclusive monitor in ARM systems
     """
-    if type(cpu) is DerivO3CPU or \
-       buildEnv['TARGET_ISA'] in ('x86', 'arm'):
-        return True
-    return False
+    return True
 ```
 
 Finally, we need to implement `connectQueues` to connect all of the
diff --git a/_pages/documentation/learning_gem5/part3/part3_11_simple-MI_example.md b/_pages/documentation/learning_gem5/part3/part3_11_simple-MI_example.md
index a00905b..c38e8bb 100644
--- a/_pages/documentation/learning_gem5/part3/part3_11_simple-MI_example.md
+++ b/_pages/documentation/learning_gem5/part3/part3_11_simple-MI_example.md
@@ -134,10 +134,7 @@
            2. The x86 mwait instruction is built on top of coherence
            3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or \
-           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
-            return True
-        return False
+        return True
 
     def connectQueues(self, ruby_system):
         """Connect all of the queues for this controller.
diff --git a/_pages/static/scripts/part1/simple.py b/_pages/static/scripts/part1/simple.py
index 69521fe..34defcd 100644
--- a/_pages/static/scripts/part1/simple.py
+++ b/_pages/static/scripts/part1/simple.py
@@ -53,7 +53,7 @@
 system.mem_ranges = [AddrRange('512MB')] # Create an address range
 
 # Create a simple CPU
-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()
 
 # Create a memory bus, a system crossbar, in this case
 system.membus = SystemXBar()
@@ -64,13 +64,12 @@
 
 # create the interrupt controller for the CPU and connect to the membus
 system.cpu.createInterruptController()
-
-# For x86 only, make sure the interrupts are connected to the memory
-# Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts[0].pio = system.membus.master
-    system.cpu.interrupts[0].int_master = system.membus.slave
-    system.cpu.interrupts[0].int_slave = system.membus.master
+system.cpu.interrupts[0].pio = system.membus.master
+# For x86 only, we make sure the interrupts are connected to the memory.
+# Note: These are directly connected to the memory bus and are not cached.
+# For other ISAs, the following two lines should be removed.
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
 
 # Create a DDR3 memory controller and connect it to the membus
 system.mem_ctrl = MemCtrl()
diff --git a/_pages/static/scripts/part1/two_level.py b/_pages/static/scripts/part1/two_level.py
index 64ee33c..4ca700e 100644
--- a/_pages/static/scripts/part1/two_level.py
+++ b/_pages/static/scripts/part1/two_level.py
@@ -53,7 +53,7 @@
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
 binary = os.path.join(thispath, '../../../',
-                      'tests/test-progs/hello/bin/', isa, 'linux/hello')
+                      'tests/test-progs/hello/bin/x86/linux/hello')
 
 # create the system we are going to simulate
 system = System()
@@ -68,7 +68,10 @@
 system.mem_ranges = [AddrRange('512MB')] # Create an address range
 
 # Create a simple CPU
-system.cpu = TimingSimpleCPU()
+# As this configuration script is for X86, we use `X86TimingSimpleCPU`
+# If a RISCV or ARM simple CPU is desired then `RiscvTimingSimpleCPU` or
+# `ArmTimingSimpleCPU` should be used.
+system.cpu = X86TimingSimpleCPU()
 
 # Create an L1 instruction and data cache
 system.cpu.icache = L1ICache()
@@ -97,13 +100,12 @@
 
 # create the interrupt controller for the CPU
 system.cpu.createInterruptController()
-
+system.cpu.interrupts[0].pio = system.membus.mem_side_ports
 # For x86 only, make sure the interrupts are connected to the memory
+# For other ISAs, these two lines should be removed
 # Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts[0].pio = system.membus.mem_side_ports
-    system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
-    system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
 
 # Connect the system up to the membus
 system.system_port = system.membus.cpu_side_ports
diff --git a/_pages/static/scripts/part1/two_level_opts.py b/_pages/static/scripts/part1/two_level_opts.py
index ce0dd47..91326f4 100644
--- a/_pages/static/scripts/part1/two_level_opts.py
+++ b/_pages/static/scripts/part1/two_level_opts.py
@@ -69,7 +69,7 @@
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
 binary = os.path.join(thispath, '../../../',
-                      'tests/test-progs/hello/bin/', isa, 'linux/hello')
+                      'tests/test-progs/hello/bin/x86/linux/hello')
 
 # If the executable is specified by user, run the hello program
 if hasattr(parser, "binary"):
@@ -88,7 +88,7 @@
 system.mem_ranges = [AddrRange('512MB')] # Create an address range
 
 # Create a simple CPU
-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()
 
 # Create an L1 instruction and data cache
 system.cpu.icache = L1ICache(options)
@@ -117,13 +117,9 @@
 
 # create the interrupt controller for the CPU
 system.cpu.createInterruptController()
-
-# For x86 only, make sure the interrupts are connected to the memory
-# Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts[0].pio = system.membus.mem_side_ports
-    system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
-    system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
+system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
 
 # Connect the system up to the membus
 system.system_port = system.membus.cpu_side_ports
diff --git a/_pages/static/scripts/part3/configs/msi_caches.py b/_pages/static/scripts/part3/configs/msi_caches.py
index 9228251..08664dd 100644
--- a/_pages/static/scripts/part3/configs/msi_caches.py
+++ b/_pages/static/scripts/part3/configs/msi_caches.py
@@ -153,10 +153,7 @@
            2. The x86 mwait instruction is built on top of coherence
            3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or \
-           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
-            return True
-        return False
+        return True
 
     def connectQueues(self, ruby_system):
         """Connect all of the queues for this controller.
diff --git a/_pages/static/scripts/part3/configs/ruby_caches_MI_example.py b/_pages/static/scripts/part3/configs/ruby_caches_MI_example.py
index 6103605..8556a27 100644
--- a/_pages/static/scripts/part3/configs/ruby_caches_MI_example.py
+++ b/_pages/static/scripts/part3/configs/ruby_caches_MI_example.py
@@ -148,10 +148,7 @@
            2. The x86 mwait instruction is built on top of coherence
            3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or \
-           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
-            return True
-        return False
+        return True
 
     def connectQueues(self, ruby_system):
         """Connect all of the queues for this controller.
diff --git a/_pages/static/scripts/part4/system.py b/_pages/static/scripts/part4/system.py
index ae0b620..623eb03 100644
--- a/_pages/static/scripts/part4/system.py
+++ b/_pages/static/scripts/part4/system.py
@@ -102,7 +102,7 @@
         # Note: If you use multiple CPUs, then the BIOS config needs to be
         #       updated as well.
 
-        self.cpu = AtomicSimpleCPU()
+        self.cpu = X86AtomicSimpleCPU()
         self.mem_mode = 'atomic'
         self.cpu.createThreads()