We are happy to announce the gem5 Tutorial and Users' Workshop, to be co-located with ISCA 2022, in New York City, on Saturday June 18th 2022. We intend for this event to be held in person assuming no worsening COVID travel restrictions.
The gem5 Tutorial will be held in the morning session and will focus on teaching those new to gem5 how to use the latest version. It will be “crash course” in gem5 and assume no prior knowledge of using computer architecture simulators. The tutorial will focus heavily on new features in gem5, such as the gem5 standard library, so may be suitable for those who have used gem5 before but wish to refresh their skills.
The gem5 Users' Workshop will be held in the afternoon session. This will be an opportunity for the users of gem5 to give presentations on their contributions to gem5 and related research. The workshop will start with a 30 minute keynote by Prof. Jason Lowe-Power, titled “Recent Advancements in Mainline gem5 v20.0 -- v21.2”. The workshop will continue with short presentations (15 minutes each) on gem5-related topics. We hope this will invoke discussions on gem5-related topics.
The gem5 tutorial is designed to give computer architecture researchers, particularly those with no prior experience using a computer architecture simulator, the opportunity to learn how to use gem5. It will be held on the morning session of Saturday June 18th 2022.
Please keep an eye on the ISCA 2022 event page for details on registering for this event.
Below is a preliminary schedule for the tutorial. It highlights the topics we intend to cover over the course of the 3-hour event.
The gem5 User's workshop will be held on Saturday June 18th 2022, in the afternoon session. The workshop will start with a 30 minute keynote presentation by Prof. Jason Lowe-Power titled “Recent Advancements in Mainline gem5 v20.0 -- v21.2”. This will be followed by a series of 15 minutes presentations. These presentations are an opportunity for users of gem5 to present gem5-related work and foster discussion.
|1:30pm||Recent Advancements in mainline gem5 v20.0 -- v21.2||Jason Lowe-Power|
|Modeling an HBM2 Memory Controller||Ayaz Akram|
|Porting the LupIO Devices into gem5||Melissa Jost|
|gem5/SST Integration 2021: Scaling Full-system Simulations||Hoa Nguyen|
|2:15pm||The Case for Using Guix to Solve the gem5 Packing Problem||Christopher Batten|
|3:00pm||Booting OP-TEE and Penetration Testing with gem5||Quentin Forcioli|
|3:15pm||vSwam-u: Unlocking Microarchitectural Research for Severless||David Schall|
|3:30pm||gem5 GPU Accuracy Profiler (GAP)||Charles Jamieson|
|3:45pm||A Cycle-level Unified DRAM Cache Controller Model in gem5||Maryam Babaie|
|4:00pm||Validating gem5's Memory Components||Mahyar Samani|
|4:15pm||Design Space Exploration for Custom Hardware Designs in gem5-SALAM||Zephan Spencer|
|4:30pm||Arms Race in Microarchitectural Security and How gem5 can help!||Guruaj Saileshwar|
|4:45pm||Loupe 2.0: A Noc Visualization Tool for Garnet||Tushar Krishna and Canlin Zhang|
|5:00pm||Closing Remarks||Jason Lowe-Power|