src/dev/riscv/lupv.hh

/*
 * Copyright (c) 2021 The Regents of the University of California
 * All rights reserved.
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 * this software without specific prior written permission.
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#ifndef __DEV_RISCV_LUPV_HH__
#define __DEV_RISCV_LUPV_HH__

#include "dev/platform.hh"
#include "dev/riscv/plic.hh"
#include "params/LupV.hh"

namespace gem5
{

using namespace RiscvISA;

/**
 * The LupV collection consists of a RISC-V processor, as well as the set of
 * LupiIO devices. This LupV platform allows for us to not only use these
 * devices, bu alsoseamlessly decide which interrupt controller we want to use.
 * For example, this platform has been tested to use both the LupioPIC for
 * interrupts, as well as the PLIC.
 **/

class LupV : public Platform
{
  public:
    Plic *pic;
    int uartIntID;

  public:

    PARAMS(LupV);
    LupV(const Params &params);

    void postConsoleInt() override;

    void clearConsoleInt() override;

    void postPciInt(int line) override;

    void clearPciInt(int line) override;

    virtual Addr pciToDma(Addr pciAddr) const;

    void serialize(CheckpointOut &cp) const override;

    void unserialize(CheckpointIn &cp) override;
};

} // namespace gem5

#endif  // __DEV_RISCV_LUPV_HH__