components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py

# Copyright (c) 2021 The Regents of the University of California
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from components_library.utils.override import overrides
from ..abstract_dma_controller import AbstractDMAController

from m5.objects import MessageBuffer


class DMAController(AbstractDMAController):
    def __init__(self, network, cache_line_size):
        super(DMAController, self).__init__(network, cache_line_size)

    @overrides(AbstractDMAController)
    def connectQueues(self, network):
        self.mandatoryQueue = MessageBuffer()
        self.responseFromDir = MessageBuffer(ordered=True)
        self.responseFromDir.in_port = network.out_port
        self.requestToDir = MessageBuffer()
        self.requestToDir.out_port = network.in_port