| # Copyright (c) 2021 The Regents of the University of California |
| # All Rights Reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| |
| from components_library.processors.abstract_core import AbstractCore |
| from components_library.isas import ISA |
| from ..abstract_l1_cache import AbstractL1Cache |
| from components_library.utils.override import * |
| |
| from m5.objects import ( |
| MessageBuffer, |
| RubyPrefetcher, |
| RubyCache, |
| ClockDomain, |
| ) |
| |
| import math |
| |
| |
| class L1Cache(AbstractL1Cache): |
| def __init__( |
| self, |
| l1i_size, |
| l1i_assoc, |
| l1d_size, |
| l1d_assoc, |
| network, |
| core: AbstractCore, |
| num_l2Caches, |
| cache_line_size, |
| target_isa: ISA, |
| clk_domain: ClockDomain, |
| ): |
| """Creating L1 cache controller. Consist of both instruction |
| and data cache. |
| """ |
| super(L1Cache, self).__init__(network, cache_line_size) |
| |
| # This is the cache memory object that stores the cache data and tags |
| self.L1Icache = RubyCache( |
| size=l1i_size, |
| assoc=l1i_assoc, |
| start_index_bit=self.getBlockSizeBits(), |
| is_icache=True, |
| ) |
| self.L1Dcache = RubyCache( |
| size=l1d_size, |
| assoc=l1d_assoc, |
| start_index_bit=self.getBlockSizeBits(), |
| is_icache=False, |
| ) |
| self.l2_select_num_bits = int(math.log(num_l2Caches, 2)) |
| self.clk_domain = clk_domain |
| self.prefetcher = RubyPrefetcher() |
| self.send_evictions = self.sendEvicts(core=core, target_isa=target_isa) |
| self.transitions_per_cycle = 4 |
| self.enable_prefetch = False |
| |
| @overrides(AbstractL1Cache) |
| def connectQueues(self, network): |
| self.mandatoryQueue = MessageBuffer() |
| self.requestFromL1Cache = MessageBuffer() |
| self.requestFromL1Cache.out_port = network.in_port |
| self.responseFromL1Cache = MessageBuffer() |
| self.responseFromL1Cache.out_port = network.in_port |
| self.unblockFromL1Cache = MessageBuffer() |
| self.unblockFromL1Cache.out_port = network.in_port |
| |
| self.optionalQueue = MessageBuffer() |
| |
| self.requestToL1Cache = MessageBuffer() |
| self.requestToL1Cache.in_port = network.out_port |
| self.responseToL1Cache = MessageBuffer() |
| self.responseToL1Cache.in_port = network.out_port |
