diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 53ade47..2bff11b 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -45,14 +45,14 @@
 // Locked read/write flags are can't be detected by the ISA parser
 const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
 
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
 
 // floating point register file entry type
-typedef double FloatReg;
-typedef uint64_t FloatRegBits;
+typedef FloatRegVal FloatReg;
+typedef RegVal FloatRegBits;
 
 // control register file contents
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
 
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 3c675cf..3e0a74e 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -59,11 +59,11 @@
 using ArmISAInst::MaxInstDestRegs;
 using ArmISAInst::MaxMiscDestRegs;
 
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
 
 // floating point register file entry type
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
 
 // Number of VecElem per Vector Register, computed based on the vector length
 constexpr unsigned NumVecElemPerVecReg = 4;
@@ -73,7 +73,7 @@
 using VecRegContainer = VecReg::Container;
 
 // cop-0/cop-1 system control register
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
 
 // condition code register; must be at least 32 bits for FpCondCodes
 typedef uint64_t CCReg;
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index dbac839..d2095d8 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -278,14 +278,14 @@
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
 
 // floating point register file entry type
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
 
 // cop-0/cop-1 system control register
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
 
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 5dd8732..527193c 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -46,11 +46,11 @@
 
 namespace NullISA {
 
-typedef uint64_t IntReg;
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
+typedef RegVal IntReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
 typedef uint8_t CCReg;
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
 const RegIndex ZeroReg = 0;
 
 // dummy typedefs since we don't have vector regs
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index adbaae5..39f7d34 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -34,6 +34,7 @@
 #include "arch/generic/vec_reg.hh"
 #include "arch/power/generated/max_inst_regs.hh"
 #include "arch/power/miscregs.hh"
+#include "base/types.hh"
 
 namespace PowerISA {
 
@@ -44,12 +45,12 @@
 // be detected by it. Manually add it here.
 const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
 
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
 
 // Floating point register file entry type
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
-typedef uint64_t MiscReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
+typedef RegVal MiscReg;
 
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index bd95cf8..75f74ef 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -63,11 +63,11 @@
 using RiscvISAInst::MaxInstDestRegs;
 const int MaxMiscDestRegs = 1;
 
-typedef uint64_t IntReg;
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
+typedef RegVal IntReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
 typedef uint8_t CCReg; // Not applicable to Riscv
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
 
 // dummy typedefs since we don't have vector regs
 const unsigned NumVecElemPerVecReg = 2;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index b5acaef..362126c 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -45,10 +45,10 @@
 using SparcISAInst::MaxInstDestRegs;
 using SparcISAInst::MaxMiscDestRegs;
 
-typedef uint64_t IntReg;
-typedef uint64_t MiscReg;
-typedef double FloatReg;
-typedef uint64_t FloatRegBits;
+typedef RegVal IntReg;
+typedef RegVal MiscReg;
+typedef FloatRegVal FloatReg;
+typedef RegVal FloatRegBits;
 
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index c2977f8..a2a74cc 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -90,9 +90,9 @@
 // value
 const int SyscallPseudoReturnReg = INTREG_RDX;
 
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
 typedef uint64_t CCReg;
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
 
 // dummy typedefs since we don't have vector regs
 constexpr unsigned NumVecElemPerVecReg = 2;
@@ -105,8 +105,8 @@
 
 //These floating point types are correct for mmx, but not
 //technically for x87 (80 bits) or at all for xmm (128 bits)
-typedef double FloatReg;
-typedef uint64_t FloatRegBits;
+typedef FloatRegVal FloatReg;
+typedef RegVal FloatRegBits;
 
 } // namespace X86ISA